Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	368648998	1			T3	2016		T4	2126		T5	1434
instr_valid_dis	323002754	1			T3	2016		T4	2126		T5	1434
instr_en	30549374	1			T16	42810		T23	143534		T131	4374

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12747909	1			T16	13620		T23	25562		T18	5170
sram_ifetch_valid_disable	318329335	1			T3	2016		T4	2126		T5	1434
sram_ifetch_enable	37571754	1			T16	30192		T17	81688		T23	118428

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	368648998	1			T3	2016		T4	2126		T5	1434
hw_debug_en_valid_off	317234560	1			T3	2016		T4	2126		T5	1434
hw_debug_en_on	36698020	1			T16	92550		T17	107184		T23	65702

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	318329335	1			T3	2016		T4	2126		T5	1434
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	300849793	1			T3	2016		T4	2126		T5	1434
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12131562	1			T16	29190		T23	31582		T131	4374
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4170952	1			T16	13620		T23	25562		T18	5170
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2086328	1			T18	5170		T145	20000		T129	24746
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1555140	1			T16	13620		T23	6524		T127	19482
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5323055	1			T56	2532		T126	12550		T127	76668
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2654433	1			T56	2532		T126	8058		T133	36230
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1852916	1			T127	76668		T137	104640		T145	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14821145	1			T16	92550		T17	54160		T23	13208
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3870587	1			T16	63360		T17	54160		T18	41516
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7698348	1			T16	29190		T23	13208		T127	80264

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	14285898	1			T23	105428		T126	42172		T127	42842
lc_exec_en	16553820	1			T17	53024		T23	52494		T131	19432
valid_exec_dis	311298758	1			T3	2016		T4	2126		T5	1434
invalid_exec_dis	50319663	1			T16	43812		T17	81688		T23	143990