Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1033
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.58 65.58 86.75 86.75 65.76 65.76 86.54 86.54 9.52 9.52 71.80 71.80 92.25 92.25 46.44 46.44 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1935147562
79.53 13.95 94.03 7.28 72.51 6.75 89.98 3.44 61.90 52.38 81.04 9.24 93.42 1.17 63.80 17.37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.924756026
84.79 5.26 95.67 1.64 73.46 0.95 89.98 0.00 90.48 28.57 85.07 4.03 94.15 0.73 64.72 0.91 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.63950716
89.51 4.72 97.14 1.47 82.58 9.12 94.15 4.17 90.48 0.00 90.05 4.98 95.76 1.61 76.42 11.70 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2235197761
92.46 2.95 98.45 1.31 85.90 3.32 95.39 1.24 100.00 9.52 93.36 3.32 96.64 0.88 77.51 1.10 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1023076988
93.92 1.46 98.69 0.25 88.27 2.37 96.56 1.17 100.00 0.00 95.02 1.66 96.64 0.00 82.27 4.75 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.575907133
94.70 0.77 98.86 0.16 89.93 1.66 96.83 0.28 100.00 0.00 95.97 0.95 96.64 0.00 84.64 2.38 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3221177759
95.43 0.73 98.86 0.00 90.28 0.36 96.83 0.00 100.00 0.00 95.97 0.00 96.64 0.00 89.40 4.75 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.649105549
95.92 0.50 98.86 0.00 90.28 0.00 96.83 0.00 100.00 0.00 95.97 0.00 96.64 0.00 92.87 3.47 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2342414823
96.24 0.31 98.86 0.00 90.40 0.12 97.45 0.62 100.00 0.00 95.97 0.00 96.64 0.00 94.33 1.46 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3428219147
96.50 0.26 99.10 0.25 90.40 0.00 98.62 1.17 100.00 0.00 96.21 0.24 96.64 0.00 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3216676687
96.74 0.24 99.10 0.00 90.64 0.24 98.69 0.07 100.00 0.00 96.21 0.00 97.66 1.02 94.88 0.37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.77364743
96.90 0.16 99.10 0.00 90.64 0.00 98.79 0.10 100.00 0.00 96.21 0.00 98.68 1.02 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2463544178
97.04 0.13 99.18 0.08 90.64 0.00 99.66 0.86 100.00 0.00 96.21 0.00 98.68 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2606958490
97.17 0.13 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.68 0.00 95.80 0.91 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1348648193
97.27 0.10 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.68 0.00 96.53 0.73 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1632525641
97.35 0.08 99.18 0.00 91.00 0.36 99.72 0.07 100.00 0.00 96.21 0.00 98.83 0.15 96.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.699379608
97.43 0.08 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.07 0.55 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3604305744
97.47 0.04 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.29 97.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2665357202
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1809271872
97.52 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1802079895

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2429947502
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1747448192
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3222049349
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2886654748
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3689555990
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.310037561
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1544672846
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3403050972
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.355457903
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3723267354
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.237848871
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1489599624
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3604519669
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1620637999
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2210492797
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3351098376
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.561803925
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2299473750
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2951982496
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.349208027
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.301746927
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1414451396
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2531194070
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1928273529
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1676161915
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1684550396
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.424390394
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1446633864
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3040032243
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1113190288
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1341311654
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3209250328
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3366105717
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4176661859
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1482983744
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2714370863
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3034125987
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1391866207
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.488412185
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.325985846
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.541860633
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1971227222
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2583388069
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1405772128
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2151057953
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.920739150
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3778909963
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2625626281
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3168215820
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1212427361
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1529553151
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3829427349
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2255994081
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2420127854
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3603543348
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2814487248
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.82864953
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1218289874
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3803045149
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.925082892
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3767240262
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2967136648
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.973581321
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.270465249
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1685195326
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3134344855
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1710453886
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.603606086
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.718766357
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3531838888
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1774187464
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1850596144
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2719255619
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1667609155
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.800348358
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3010922484
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.959903383
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.31401120
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.186227633
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3759468951
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2564438303
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3033707757
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2561926837
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3988441711
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3143657077
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2062924309
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1794666123
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.89222370
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3298428952
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/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.848905782
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/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3140530530
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1459663818
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3313777426
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3344159186
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1742352284
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1240195098
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1354236039
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3071307417
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2987550890
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3064578366
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1943194586
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1126717591
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1138638132
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.4207403166
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3035179159
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.4141925439
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3279880206
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.794482035
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2525639588
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1951777055
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3563999773
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3916646079
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1145246458
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2625557233
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2995699316
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2999455743
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1147343780
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.595155600
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.459110522
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1248847735
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.230242528
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3604233398
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.26609989
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1635580636
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1566078867
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.145720463
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2243701773
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.903398173
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3579726881
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3814859856
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1613647532
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1741591082
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.11174772
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2436976258
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3051330473
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1127325260
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.112193186
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1787409597
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2674449358
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2018348083
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2093944840
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3633136440
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2018791073
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2463960330
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.692276736
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.81739647
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3771338388
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3256972614
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3588817310
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.862337403



Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.699379608 Sep 04 03:02:35 AM UTC 24 Sep 04 03:02:44 AM UTC 24 24096478 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2606958490 Sep 04 03:02:34 AM UTC 24 Sep 04 03:02:46 AM UTC 24 699023777 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1023076988 Sep 04 03:02:42 AM UTC 24 Sep 04 03:02:47 AM UTC 24 379692082 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3999576944 Sep 04 03:02:35 AM UTC 24 Sep 04 03:02:48 AM UTC 24 923136512 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.739354029 Sep 04 03:02:44 AM UTC 24 Sep 04 03:02:49 AM UTC 24 16760142 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2235197761 Sep 04 03:02:35 AM UTC 24 Sep 04 03:02:52 AM UTC 24 814916539 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3886680790 Sep 04 03:02:36 AM UTC 24 Sep 04 03:02:53 AM UTC 24 1358422827 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1935147562 Sep 04 03:02:41 AM UTC 24 Sep 04 03:02:53 AM UTC 24 1030112838 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2905285245 Sep 04 03:02:47 AM UTC 24 Sep 04 03:02:54 AM UTC 24 365528176 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.374801134 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:55 AM UTC 24 970172737 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.566037829 Sep 04 03:02:35 AM UTC 24 Sep 04 03:02:55 AM UTC 24 2332890437 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.47798387 Sep 04 03:02:35 AM UTC 24 Sep 04 03:03:03 AM UTC 24 1444247406 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1486278567 Sep 04 03:02:32 AM UTC 24 Sep 04 03:03:03 AM UTC 24 2998896896 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1235558601 Sep 04 03:03:04 AM UTC 24 Sep 04 03:03:11 AM UTC 24 359621647 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3832573089 Sep 04 03:02:51 AM UTC 24 Sep 04 03:03:20 AM UTC 24 1022993036 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1584134597 Sep 04 03:02:35 AM UTC 24 Sep 04 03:03:24 AM UTC 24 2992107577 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2310513002 Sep 04 03:02:54 AM UTC 24 Sep 04 03:03:29 AM UTC 24 751067894 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2138258882 Sep 04 03:03:21 AM UTC 24 Sep 04 03:03:30 AM UTC 24 496797518 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2091091686 Sep 04 03:03:30 AM UTC 24 Sep 04 03:03:32 AM UTC 24 48023788 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.906098017 Sep 04 03:02:32 AM UTC 24 Sep 04 03:03:32 AM UTC 24 2962599859 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.788779290 Sep 04 03:03:29 AM UTC 24 Sep 04 03:03:34 AM UTC 24 1104443395 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.924756026 Sep 04 03:02:35 AM UTC 24 Sep 04 03:03:36 AM UTC 24 925616461 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1227019170 Sep 04 03:03:33 AM UTC 24 Sep 04 03:03:49 AM UTC 24 3997214330 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.31606675 Sep 04 03:02:54 AM UTC 24 Sep 04 03:03:54 AM UTC 24 2924428198 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.912941936 Sep 04 03:02:32 AM UTC 24 Sep 04 03:03:58 AM UTC 24 3395638622 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2726310306 Sep 04 03:02:55 AM UTC 24 Sep 04 03:04:01 AM UTC 24 26184163161 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3150498369 Sep 04 03:02:38 AM UTC 24 Sep 04 03:04:05 AM UTC 24 5577331197 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1802090840 Sep 04 03:02:32 AM UTC 24 Sep 04 03:04:08 AM UTC 24 45595274310 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1111204915 Sep 04 03:04:09 AM UTC 24 Sep 04 03:04:16 AM UTC 24 6685117142 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3251042377 Sep 04 03:03:51 AM UTC 24 Sep 04 03:04:24 AM UTC 24 779848434 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2333297896 Sep 04 03:02:34 AM UTC 24 Sep 04 03:04:44 AM UTC 24 8219331984 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.923248576 Sep 04 03:03:12 AM UTC 24 Sep 04 03:04:58 AM UTC 24 1439102761 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3216676687 Sep 04 03:03:55 AM UTC 24 Sep 04 03:04:59 AM UTC 24 787800592 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1199526 Sep 04 03:04:00 AM UTC 24 Sep 04 03:05:00 AM UTC 24 6344138657 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.877646976 Sep 04 03:03:59 AM UTC 24 Sep 04 03:05:02 AM UTC 24 786511911 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.76760860 Sep 04 03:05:01 AM UTC 24 Sep 04 03:05:03 AM UTC 24 13032720 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2027968664 Sep 04 03:05:00 AM UTC 24 Sep 04 03:05:03 AM UTC 24 386163825 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.513380675 Sep 04 03:02:35 AM UTC 24 Sep 04 03:05:05 AM UTC 24 26426353864 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2444310737 Sep 04 03:02:35 AM UTC 24 Sep 04 03:05:06 AM UTC 24 1597565070 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2981471097 Sep 04 03:02:33 AM UTC 24 Sep 04 03:05:10 AM UTC 24 13512140929 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1315730296 Sep 04 03:05:07 AM UTC 24 Sep 04 03:05:23 AM UTC 24 4077542458 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2361634338 Sep 04 03:02:32 AM UTC 24 Sep 04 03:05:33 AM UTC 24 3114126719 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4070121119 Sep 04 03:02:36 AM UTC 24 Sep 04 03:05:40 AM UTC 24 9267371644 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3820707455 Sep 04 03:05:12 AM UTC 24 Sep 04 03:05:45 AM UTC 24 3577264571 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1275174601 Sep 04 03:05:03 AM UTC 24 Sep 04 03:06:09 AM UTC 24 6858444427 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2463544178 Sep 04 03:04:25 AM UTC 24 Sep 04 03:06:11 AM UTC 24 23147764364 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3954810030 Sep 04 03:02:53 AM UTC 24 Sep 04 03:06:14 AM UTC 24 3121992139 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3863082800 Sep 04 03:06:12 AM UTC 24 Sep 04 03:06:18 AM UTC 24 693660932 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1640111056 Sep 04 03:03:37 AM UTC 24 Sep 04 03:06:29 AM UTC 24 5045494047 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3549367173 Sep 04 03:05:23 AM UTC 24 Sep 04 03:06:42 AM UTC 24 5495070921 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2850876760 Sep 04 03:06:43 AM UTC 24 Sep 04 03:06:47 AM UTC 24 195696540 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3806306704 Sep 04 03:06:48 AM UTC 24 Sep 04 03:06:50 AM UTC 24 15598089 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.2541372344 Sep 04 03:06:51 AM UTC 24 Sep 04 03:07:04 AM UTC 24 1413319136 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.63950716 Sep 04 03:04:44 AM UTC 24 Sep 04 03:07:07 AM UTC 24 3706016133 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.871862754 Sep 04 03:05:34 AM UTC 24 Sep 04 03:07:10 AM UTC 24 8153667284 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2369023849 Sep 04 03:04:17 AM UTC 24 Sep 04 03:07:12 AM UTC 24 7205553338 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.223247988 Sep 04 03:03:05 AM UTC 24 Sep 04 03:07:49 AM UTC 24 41277414367 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3602340303 Sep 04 03:02:35 AM UTC 24 Sep 04 03:07:51 AM UTC 24 4167753480 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2343923058 Sep 04 03:02:35 AM UTC 24 Sep 04 03:08:26 AM UTC 24 15132875863 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.1216303220 Sep 04 03:02:36 AM UTC 24 Sep 04 03:08:29 AM UTC 24 6864697423 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.222252738 Sep 04 03:08:27 AM UTC 24 Sep 04 03:08:34 AM UTC 24 351678472 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3891389660 Sep 04 03:02:49 AM UTC 24 Sep 04 03:08:42 AM UTC 24 20883521802 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3753733390 Sep 04 03:08:52 AM UTC 24 Sep 04 03:08:54 AM UTC 24 44668142 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3144476711 Sep 04 03:07:12 AM UTC 24 Sep 04 03:08:57 AM UTC 24 892374511 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2589829395 Sep 04 03:07:50 AM UTC 24 Sep 04 03:08:59 AM UTC 24 1139425036 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2347793384 Sep 04 03:06:18 AM UTC 24 Sep 04 03:09:08 AM UTC 24 9253667926 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.13424995 Sep 04 03:02:56 AM UTC 24 Sep 04 03:09:18 AM UTC 24 17635254727 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2636183636 Sep 04 03:05:42 AM UTC 24 Sep 04 03:09:25 AM UTC 24 2685830279 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1180049893 Sep 04 03:02:35 AM UTC 24 Sep 04 03:09:26 AM UTC 24 29971220160 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1862710053 Sep 04 03:07:05 AM UTC 24 Sep 04 03:09:34 AM UTC 24 1462274735 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.607759402 Sep 04 03:08:42 AM UTC 24 Sep 04 03:09:39 AM UTC 24 5717040979 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2710171142 Sep 04 03:09:19 AM UTC 24 Sep 04 03:09:44 AM UTC 24 841711317 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3313777426 Sep 04 03:08:55 AM UTC 24 Sep 04 03:09:45 AM UTC 24 1140482267 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3848043964 Sep 04 03:07:50 AM UTC 24 Sep 04 03:09:47 AM UTC 24 8469359490 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3221177759 Sep 04 03:07:52 AM UTC 24 Sep 04 03:09:50 AM UTC 24 11715203762 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.848905782 Sep 04 03:09:27 AM UTC 24 Sep 04 03:09:51 AM UTC 24 2958344753 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3140530530 Sep 04 03:09:45 AM UTC 24 Sep 04 03:09:53 AM UTC 24 360881946 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.852017797 Sep 04 03:06:28 AM UTC 24 Sep 04 03:10:19 AM UTC 24 3069319264 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.882350848 Sep 04 03:10:19 AM UTC 24 Sep 04 03:10:21 AM UTC 24 110815721 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1951777055 Sep 04 03:10:20 AM UTC 24 Sep 04 03:10:33 AM UTC 24 878120194 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1386737672 Sep 04 03:02:32 AM UTC 24 Sep 04 03:10:52 AM UTC 24 16732844892 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.367706032 Sep 04 03:08:35 AM UTC 24 Sep 04 03:10:57 AM UTC 24 5014310534 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3309710925 Sep 04 03:06:15 AM UTC 24 Sep 04 03:10:57 AM UTC 24 16418112495 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1240195098 Sep 04 03:09:27 AM UTC 24 Sep 04 03:11:01 AM UTC 24 772514026 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2342414823 Sep 04 03:03:51 AM UTC 24 Sep 04 03:11:06 AM UTC 24 14901558529 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.4141925439 Sep 04 03:10:53 AM UTC 24 Sep 04 03:11:09 AM UTC 24 813261732 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3731512613 Sep 04 03:07:11 AM UTC 24 Sep 04 03:11:12 AM UTC 24 2970215888 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2625557233 Sep 04 03:11:02 AM UTC 24 Sep 04 03:11:25 AM UTC 24 733410821 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3347187654 Sep 04 03:02:47 AM UTC 24 Sep 04 03:11:26 AM UTC 24 30873250878 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.794482035 Sep 04 03:11:28 AM UTC 24 Sep 04 03:11:35 AM UTC 24 1408934735 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1742352284 Sep 04 03:09:09 AM UTC 24 Sep 04 03:11:37 AM UTC 24 2966572189 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2656104974 Sep 04 03:09:35 AM UTC 24 Sep 04 03:11:48 AM UTC 24 7260611602 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3584881445 Sep 04 03:09:34 AM UTC 24 Sep 04 03:12:01 AM UTC 24 76082153736 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1943194586 Sep 04 03:11:06 AM UTC 24 Sep 04 03:12:05 AM UTC 24 29919726325 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3071307417 Sep 04 03:12:06 AM UTC 24 Sep 04 03:12:08 AM UTC 24 11064166 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3064578366 Sep 04 03:11:12 AM UTC 24 Sep 04 03:12:21 AM UTC 24 8416450233 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3916646079 Sep 04 03:11:49 AM UTC 24 Sep 04 03:12:23 AM UTC 24 930615811 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.903398173 Sep 04 03:12:09 AM UTC 24 Sep 04 03:12:23 AM UTC 24 736840791 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3386843534 Sep 04 03:07:19 AM UTC 24 Sep 04 03:12:25 AM UTC 24 79473342327 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2684629694 Sep 04 03:09:48 AM UTC 24 Sep 04 03:12:32 AM UTC 24 28854106740 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.3714940732 Sep 04 03:03:03 AM UTC 24 Sep 04 03:12:33 AM UTC 24 8861436532 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1635580636 Sep 04 03:12:25 AM UTC 24 Sep 04 03:12:34 AM UTC 24 1414146892 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1275634254 Sep 04 03:08:31 AM UTC 24 Sep 04 03:12:37 AM UTC 24 24619859322 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1126717591 Sep 04 03:10:59 AM UTC 24 Sep 04 03:12:44 AM UTC 24 1565523585 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1248847735 Sep 04 03:12:35 AM UTC 24 Sep 04 03:12:49 AM UTC 24 8587819650 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1336254894 Sep 04 03:08:27 AM UTC 24 Sep 04 03:12:49 AM UTC 24 27225862312 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1790511566 Sep 04 03:05:05 AM UTC 24 Sep 04 03:12:56 AM UTC 24 31994521952 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1741591082 Sep 04 03:12:35 AM UTC 24 Sep 04 03:13:01 AM UTC 24 3905273781 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.670172842 Sep 04 03:04:03 AM UTC 24 Sep 04 03:13:03 AM UTC 24 24951892552 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.145720463 Sep 04 03:12:56 AM UTC 24 Sep 04 03:13:04 AM UTC 24 710940614 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.639437067 Sep 04 03:09:51 AM UTC 24 Sep 04 03:13:06 AM UTC 24 20120233869 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3428219147 Sep 04 03:09:52 AM UTC 24 Sep 04 03:13:23 AM UTC 24 2508144331 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2999455743 Sep 04 03:13:25 AM UTC 24 Sep 04 03:13:27 AM UTC 24 15815139 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1138638132 Sep 04 03:11:38 AM UTC 24 Sep 04 03:13:32 AM UTC 24 18054075153 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1895993315 Sep 04 03:05:04 AM UTC 24 Sep 04 03:13:36 AM UTC 24 5007902425 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.459110522 Sep 04 03:12:38 AM UTC 24 Sep 04 03:13:42 AM UTC 24 18985206107 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.81739647 Sep 04 03:13:28 AM UTC 24 Sep 04 03:13:46 AM UTC 24 1061883685 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3633136440 Sep 04 03:13:43 AM UTC 24 Sep 04 03:14:05 AM UTC 24 1229417217 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.862337403 Sep 04 03:14:02 AM UTC 24 Sep 04 03:14:11 AM UTC 24 1361240840 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1787409597 Sep 04 03:13:47 AM UTC 24 Sep 04 03:14:14 AM UTC 24 764836239 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3825938498 Sep 04 03:02:32 AM UTC 24 Sep 04 03:14:28 AM UTC 24 24860520316 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.26609989 Sep 04 03:12:22 AM UTC 24 Sep 04 03:14:51 AM UTC 24 3404796453 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2463960330 Sep 04 03:14:51 AM UTC 24 Sep 04 03:14:58 AM UTC 24 346744785 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.4207403166 Sep 04 03:11:36 AM UTC 24 Sep 04 03:15:03 AM UTC 24 11108465191 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1701459268 Sep 04 03:09:40 AM UTC 24 Sep 04 03:15:23 AM UTC 24 39315865172 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1145246458 Sep 04 03:10:49 AM UTC 24 Sep 04 03:15:34 AM UTC 24 7185734936 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.575907133 Sep 04 03:04:06 AM UTC 24 Sep 04 03:15:36 AM UTC 24 9562912506 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2436976258 Sep 04 03:15:37 AM UTC 24 Sep 04 03:15:39 AM UTC 24 15207259 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1559106418 Sep 04 03:05:10 AM UTC 24 Sep 04 03:15:45 AM UTC 24 48163976329 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.692276736 Sep 04 03:14:28 AM UTC 24 Sep 04 03:15:52 AM UTC 24 5266734370 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3256972614 Sep 04 03:15:24 AM UTC 24 Sep 04 03:15:59 AM UTC 24 968691829 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.4234626761 Sep 04 03:09:22 AM UTC 24 Sep 04 03:16:05 AM UTC 24 7960859177 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1613647532 Sep 04 03:12:24 AM UTC 24 Sep 04 03:16:19 AM UTC 24 12329175354 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2674449358 Sep 04 03:15:03 AM UTC 24 Sep 04 03:16:29 AM UTC 24 1514846496 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.995611730 Sep 04 03:15:40 AM UTC 24 Sep 04 03:16:32 AM UTC 24 1259459515 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1305293502 Sep 04 03:16:06 AM UTC 24 Sep 04 03:16:34 AM UTC 24 2437918436 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3604233398 Sep 04 03:13:01 AM UTC 24 Sep 04 03:16:40 AM UTC 24 42801523837 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.230242528 Sep 04 03:13:03 AM UTC 24 Sep 04 03:16:46 AM UTC 24 4382513355 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2443374469 Sep 04 03:16:30 AM UTC 24 Sep 04 03:16:48 AM UTC 24 8947706619 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3016291833 Sep 04 03:16:47 AM UTC 24 Sep 04 03:16:54 AM UTC 24 374858847 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.161976185 Sep 04 03:16:20 AM UTC 24 Sep 04 03:16:56 AM UTC 24 729669673 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3598635965 Sep 04 03:16:25 AM UTC 24 Sep 04 03:17:07 AM UTC 24 751359463 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3814859856 Sep 04 03:13:04 AM UTC 24 Sep 04 03:17:18 AM UTC 24 4878926395 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.4150918568 Sep 04 03:17:20 AM UTC 24 Sep 04 03:17:21 AM UTC 24 22636694 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3279880206 Sep 04 03:10:58 AM UTC 24 Sep 04 03:17:29 AM UTC 24 12873180864 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.112193186 Sep 04 03:14:06 AM UTC 24 Sep 04 03:17:36 AM UTC 24 151538829288 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.55536903 Sep 04 03:17:23 AM UTC 24 Sep 04 03:17:36 AM UTC 24 2908164204 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.4265619022 Sep 04 03:02:32 AM UTC 24 Sep 04 03:17:52 AM UTC 24 22304782026 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2018348083 Sep 04 03:14:59 AM UTC 24 Sep 04 03:17:54 AM UTC 24 2658178445 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.798792700 Sep 04 03:16:57 AM UTC 24 Sep 04 03:18:02 AM UTC 24 7683798975 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1632525641 Sep 04 03:04:05 AM UTC 24 Sep 04 03:18:14 AM UTC 24 21473853066 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1522490376 Sep 04 03:17:53 AM UTC 24 Sep 04 03:18:18 AM UTC 24 3380698604 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.131558066 Sep 04 03:08:58 AM UTC 24 Sep 04 03:18:32 AM UTC 24 6493991741 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.725895263 Sep 04 03:02:35 AM UTC 24 Sep 04 03:18:44 AM UTC 24 20336296729 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2418002328 Sep 04 03:08:17 AM UTC 24 Sep 04 03:18:53 AM UTC 24 6596607707 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1125779902 Sep 04 03:18:02 AM UTC 24 Sep 04 03:19:01 AM UTC 24 748300827 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.955870985 Sep 04 03:18:14 AM UTC 24 Sep 04 03:19:05 AM UTC 24 1639141687 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.4194437492 Sep 04 03:19:02 AM UTC 24 Sep 04 03:19:08 AM UTC 24 688837533 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2884697918 Sep 04 03:18:18 AM UTC 24 Sep 04 03:19:50 AM UTC 24 9696556213 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1317521500 Sep 04 03:16:54 AM UTC 24 Sep 04 03:20:12 AM UTC 24 5564428725 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.671673745 Sep 04 03:16:00 AM UTC 24 Sep 04 03:20:15 AM UTC 24 17236360927 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2929839019 Sep 04 03:20:16 AM UTC 24 Sep 04 03:20:18 AM UTC 24 21479464 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2055272430 Sep 04 03:05:46 AM UTC 24 Sep 04 03:20:30 AM UTC 24 32629941463 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3588817310 Sep 04 03:13:36 AM UTC 24 Sep 04 03:20:32 AM UTC 24 16698459676 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1703270607 Sep 04 03:19:51 AM UTC 24 Sep 04 03:20:39 AM UTC 24 4304685018 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.637744352 Sep 04 03:20:19 AM UTC 24 Sep 04 03:20:46 AM UTC 24 1111083351 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3290577252 Sep 04 03:19:09 AM UTC 24 Sep 04 03:20:48 AM UTC 24 1398106337 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2285011082 Sep 04 03:02:32 AM UTC 24 Sep 04 03:21:00 AM UTC 24 16905030358 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2241272887 Sep 04 03:20:46 AM UTC 24 Sep 04 03:21:23 AM UTC 24 17627679723 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.699828505 Sep 04 03:15:48 AM UTC 24 Sep 04 03:21:33 AM UTC 24 10089545638 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2186768887 Sep 04 03:21:09 AM UTC 24 Sep 04 03:21:38 AM UTC 24 2021052648 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1745151818 Sep 04 03:20:31 AM UTC 24 Sep 04 03:21:39 AM UTC 24 1646512249 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2018791073 Sep 04 03:13:46 AM UTC 24 Sep 04 03:21:39 AM UTC 24 120620138926 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1011526473 Sep 04 03:21:40 AM UTC 24 Sep 04 03:21:46 AM UTC 24 1972569819 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.460854263 Sep 04 03:21:40 AM UTC 24 Sep 04 03:21:52 AM UTC 24 421537401 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1720045958 Sep 04 03:16:49 AM UTC 24 Sep 04 03:22:00 AM UTC 24 129516849246 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1566078867 Sep 04 03:12:34 AM UTC 24 Sep 04 03:22:32 AM UTC 24 249528672783 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.963344937 Sep 04 03:21:24 AM UTC 24 Sep 04 03:22:35 AM UTC 24 18822312326 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.476551114 Sep 04 03:22:36 AM UTC 24 Sep 04 03:22:38 AM UTC 24 19673312 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1629006896 Sep 04 03:21:00 AM UTC 24 Sep 04 03:22:45 AM UTC 24 3630626813 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1597915685 Sep 04 03:22:39 AM UTC 24 Sep 04 03:22:45 AM UTC 24 747442605 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2872064462 Sep 04 03:03:33 AM UTC 24 Sep 04 03:23:05 AM UTC 24 47402349220 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1986611406 Sep 04 03:19:05 AM UTC 24 Sep 04 03:23:05 AM UTC 24 86684412229 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2162551928 Sep 04 03:02:35 AM UTC 24 Sep 04 03:23:18 AM UTC 24 17388303116 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.968342373 Sep 04 03:23:06 AM UTC 24 Sep 04 03:23:34 AM UTC 24 7197096713 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.11174772 Sep 04 03:14:11 AM UTC 24 Sep 04 03:23:37 AM UTC 24 33826599229 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.610883707 Sep 04 03:17:37 AM UTC 24 Sep 04 03:23:44 AM UTC 24 67846249397 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2525639588 Sep 04 03:11:25 AM UTC 24 Sep 04 03:23:47 AM UTC 24 11952176616 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1314666765 Sep 04 03:23:35 AM UTC 24 Sep 04 03:24:00 AM UTC 24 934769895 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.4101569335 Sep 04 03:21:54 AM UTC 24 Sep 04 03:24:01 AM UTC 24 3290552327 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.595155600 Sep 04 03:12:50 AM UTC 24 Sep 04 03:24:06 AM UTC 24 9457663738 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3780972079 Sep 04 03:24:02 AM UTC 24 Sep 04 03:24:09 AM UTC 24 365660196 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3548370689 Sep 04 03:22:01 AM UTC 24 Sep 04 03:24:21 AM UTC 24 9318447248 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2447200567 Sep 04 03:02:56 AM UTC 24 Sep 04 03:24:23 AM UTC 24 60257920641 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1805135802 Sep 04 03:23:38 AM UTC 24 Sep 04 03:24:38 AM UTC 24 770389795 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2791973381 Sep 04 03:24:39 AM UTC 24 Sep 04 03:24:41 AM UTC 24 34111855 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.993734841 Sep 04 03:16:12 AM UTC 24 Sep 04 03:24:50 AM UTC 24 6515055532 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.460009521 Sep 04 03:06:10 AM UTC 24 Sep 04 03:24:50 AM UTC 24 157811386286 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.285708169 Sep 04 03:24:42 AM UTC 24 Sep 04 03:25:00 AM UTC 24 463399127 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.28424366 Sep 04 03:07:08 AM UTC 24 Sep 04 03:25:05 AM UTC 24 30777873296 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2971748915 Sep 04 03:24:09 AM UTC 24 Sep 04 03:25:20 AM UTC 24 3978176634 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.136061073 Sep 04 03:24:23 AM UTC 24 Sep 04 03:25:28 AM UTC 24 1215927655 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3769001577 Sep 04 03:22:46 AM UTC 24 Sep 04 03:25:28 AM UTC 24 19752584474 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2995699316 Sep 04 03:12:44 AM UTC 24 Sep 04 03:25:47 AM UTC 24 60733390323 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.4124119948 Sep 04 03:24:01 AM UTC 24 Sep 04 03:25:55 AM UTC 24 1004545019 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1076766685 Sep 04 03:20:39 AM UTC 24 Sep 04 03:25:59 AM UTC 24 4443193468 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.433820645 Sep 04 03:25:28 AM UTC 24 Sep 04 03:26:06 AM UTC 24 2846446205 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.374065244 Sep 04 03:18:33 AM UTC 24 Sep 04 03:26:11 AM UTC 24 37066421232 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1303902928 Sep 04 03:26:07 AM UTC 24 Sep 04 03:26:13 AM UTC 24 692436575 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3266883589 Sep 04 03:25:05 AM UTC 24 Sep 04 03:26:15 AM UTC 24 874884672 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1755301134 Sep 04 03:26:15 AM UTC 24 Sep 04 03:26:30 AM UTC 24 345925392 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3374319455 Sep 04 03:23:46 AM UTC 24 Sep 04 03:26:32 AM UTC 24 96520196037 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.3416056006 Sep 04 03:25:28 AM UTC 24 Sep 04 03:26:33 AM UTC 24 760231509 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2837396253 Sep 04 03:26:33 AM UTC 24 Sep 04 03:26:34 AM UTC 24 13613715 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.623446411 Sep 04 03:25:34 AM UTC 24 Sep 04 03:26:59 AM UTC 24 7770174773 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.923058113 Sep 04 03:26:34 AM UTC 24 Sep 04 03:27:07 AM UTC 24 1367930070 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2532276933 Sep 04 03:17:30 AM UTC 24 Sep 04 03:27:21 AM UTC 24 20521185903 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2987550890 Sep 04 03:10:33 AM UTC 24 Sep 04 03:27:26 AM UTC 24 90633481612 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1127325260 Sep 04 03:14:15 AM UTC 24 Sep 04 03:27:26 AM UTC 24 23839622718 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1079475940 Sep 04 03:16:35 AM UTC 24 Sep 04 03:27:47 AM UTC 24 24633785045 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.894072054 Sep 04 03:27:21 AM UTC 24 Sep 04 03:27:51 AM UTC 24 893143617 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3879146308 Sep 04 03:17:55 AM UTC 24 Sep 04 03:28:07 AM UTC 24 44343157404 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2243701773 Sep 04 03:12:50 AM UTC 24 Sep 04 03:28:25 AM UTC 24 9977604319 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.4102530382 Sep 04 03:21:47 AM UTC 24 Sep 04 03:28:32 AM UTC 24 137864273563 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1592683732 Sep 04 03:08:00 AM UTC 24 Sep 04 03:28:33 AM UTC 24 46052512794 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.102911422 Sep 04 03:28:34 AM UTC 24 Sep 04 03:28:40 AM UTC 24 1346341795 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1919580322 Sep 04 03:27:27 AM UTC 24 Sep 04 03:28:41 AM UTC 24 2998755967 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2615917707 Sep 04 03:23:05 AM UTC 24 Sep 04 03:28:44 AM UTC 24 11448012421 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1866460527 Sep 04 03:24:07 AM UTC 24 Sep 04 03:28:58 AM UTC 24 4027325620 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2592053706 Sep 04 03:27:47 AM UTC 24 Sep 04 03:29:06 AM UTC 24 1535362238 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2823579950 Sep 04 03:29:07 AM UTC 24 Sep 04 03:29:09 AM UTC 24 19658107 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.338725488 Sep 04 03:25:00 AM UTC 24 Sep 04 03:29:11 AM UTC 24 3308595978 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1354236039 Sep 04 03:11:09 AM UTC 24 Sep 04 03:29:23 AM UTC 24 15477098968 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.3018258425 Sep 04 03:02:48 AM UTC 24 Sep 04 03:29:25 AM UTC 24 23943810933 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2826591838 Sep 04 03:29:10 AM UTC 24 Sep 04 03:29:27 AM UTC 24 1450137008 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3286045547 Sep 04 03:28:44 AM UTC 24 Sep 04 03:29:28 AM UTC 24 1243988641 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1291991011 Sep 04 03:29:28 AM UTC 24 Sep 04 03:29:34 AM UTC 24 354517322 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1837524940 Sep 04 03:27:52 AM UTC 24 Sep 04 03:29:37 AM UTC 24 42299329977 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3035179159 Sep 04 03:10:21 AM UTC 24 Sep 04 03:29:40 AM UTC 24 12262825997 ps
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