Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	356848508	1			T1	10104		T2	5588		T3	5004
instr_valid_dis	315646123	1			T1	10104		T2	5588		T3	5004
instr_en	32450751	1			T16	105592		T27	40000		T41	58

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10759896	1			T26	54866		T40	50568		T41	59066
sram_ifetch_valid_disable	315794418	1			T1	10104		T2	5588		T3	5004
sram_ifetch_enable	30294194	1			T16	18548		T26	55734		T27	97652

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	356848508	1			T1	10104		T2	5588		T3	5004
hw_debug_en_valid_off	314404613	1			T1	10104		T2	5588		T3	5004
hw_debug_en_on	27197909	1			T16	93736		T26	54866		T40	77708

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	315794418	1			T1	10104		T2	5588		T3	5004
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	299074717	1			T1	10104		T2	5588		T3	5004
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13846529	1			T16	87106		T17	3134		T157	60028
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4103132	1			T41	13722		T17	19546		T161	46568
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1868084	1			T41	13722		T17	19546		T161	36662
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1739452	1			T161	9906		T155	15336		T18	44408
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4633976	1			T26	54866		T40	50568		T41	45344
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1943944	1			T26	54866		T40	50568		T41	45344
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1811588	1			T157	64		T155	19856		T164	33096
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11176797	1			T16	75992		T40	27140		T17	23780
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3877014	1			T17	23780		T157	106654		T154	26054
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6267799	1			T16	75992		T161	12058		T164	85656

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13995826	1			T16	18486		T27	40000		T41	58
lc_exec_en	11387136	1			T16	17744		T41	4698		T157	46676
valid_exec_dis	311020815	1			T1	10104		T2	5588		T3	5004
invalid_exec_dis	41054090	1			T16	18548		T26	110600		T27	97652