Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1034
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.39 68.39 92.23 92.23 70.38 70.38 83.68 83.68 33.33 33.33 82.70 82.70 93.57 93.57 22.85 22.85 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2477497330
87.18 18.79 97.79 5.56 84.12 13.74 92.77 9.09 90.48 57.14 90.76 8.06 96.20 2.63 58.14 35.28 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2360895490
90.80 3.62 98.12 0.33 86.14 2.01 95.70 2.93 90.48 0.00 92.18 1.42 96.78 0.58 76.23 18.10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2950486138
92.50 1.69 98.61 0.49 86.14 0.00 95.70 0.00 100.00 9.52 93.13 0.95 97.66 0.88 76.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1984847046
93.94 1.45 98.86 0.25 89.10 2.96 96.52 0.83 100.00 0.00 95.02 1.90 97.66 0.00 80.44 4.20 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.843331399
94.72 0.78 98.86 0.00 89.81 0.71 98.76 2.24 100.00 0.00 95.50 0.47 97.66 0.00 82.45 2.01 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1360666597
95.48 0.76 98.86 0.00 90.17 0.36 98.76 0.00 100.00 0.00 95.50 0.00 97.66 0.00 87.39 4.94 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1343340875
96.03 0.56 99.10 0.25 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.24 97.81 0.15 90.68 3.29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2654665920
96.32 0.29 99.10 0.00 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.00 97.81 0.00 92.69 2.01 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2278368496
96.48 0.16 99.18 0.08 90.17 0.00 99.59 0.83 100.00 0.00 95.73 0.00 97.81 0.00 92.87 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2522949501
96.61 0.14 99.18 0.00 90.17 0.00 99.66 0.07 100.00 0.00 95.73 0.00 98.68 0.88 92.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3268890178
96.74 0.13 99.18 0.00 90.17 0.00 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 93.78 0.91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3335543092
96.86 0.11 99.18 0.00 90.40 0.24 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 94.33 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3398847282
96.96 0.10 99.18 0.00 90.40 0.00 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 95.06 0.73 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1839283014
97.05 0.09 99.18 0.00 90.76 0.36 99.72 0.07 100.00 0.00 95.73 0.00 98.68 0.00 95.25 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1729250817
97.13 0.08 99.18 0.00 90.88 0.12 99.72 0.00 100.00 0.00 96.21 0.47 98.68 0.00 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3768478288
97.21 0.08 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.68 0.00 95.80 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3595310330
97.28 0.07 99.18 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.21 0.00 98.68 0.00 96.16 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.323181055
97.34 0.06 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.44 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3753620047
97.39 0.05 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4136666043
97.42 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.71 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3065585998
97.45 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1014568472
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3481780082
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1159154091

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779782087
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2306030330
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1278456786
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223699099
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.326656827
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2153090999
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.450527380
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.796959038
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4205872414
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4158012526
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2766551116
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.816664740
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61107819
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1298845910
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.962079567
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2257344710
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2064118992
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2168635177
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.152054983
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1937168217
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3741624309
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3517336145
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2393116725
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1583069599
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.714746564
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3316091639
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3192778756
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1696871599
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1634216345
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.928710998
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2165211593
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.343888688
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4113846924
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.452299235
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2308227210
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.920155578
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3176042476
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.781047248
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1387852168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1847548202
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2154646461
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2514694958
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2803788174
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2326938022
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2115888729
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3669046291
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3741474874
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.948965705
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730244314
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.414602708
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2008458932
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3887949007
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1130249595
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.408350002
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2110102541
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.114630325
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2944493440
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2848766194
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.147888327
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2100792613
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2207535632
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1026607163
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3449193498
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670932546
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3784477556
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1882678657
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3042070500
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.673749070
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.220746348
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.943839782
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2328550734
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3306959132
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3739927501
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.748282670
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2549364997
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2553478592
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3379709561
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1265302495
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3920737204
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3820336260
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.622369848
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.567221264
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3999353506
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3687578577
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.252197075
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3102882227
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4290462407
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2516530198
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1117367173
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.380920192
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2752365856
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1431041913
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3236973876
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2934053289
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3600834163
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1591996807
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2550068932
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1239964770
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.270011213
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1338908667
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2908235678
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4074459146
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1575206583
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3301115381
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1517073748
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2766588561
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1785441480
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2512742899
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2779187689
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3968264716
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1736450766
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1358168419
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.861661355
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3439416979
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3434589720
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1270914001
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.939011170
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2917335084
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1091146166
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3001345541
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1908049152
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.814709857
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3616221054
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.118471559
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1354180109
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3197810961
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.211169779
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3096486494
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3406739442
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1193304196
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3180145993
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1828843793
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3471559393
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3908435718
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2707502035
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3344526823
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3574540870
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3389530582
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3537194487
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2463732049
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.306013334
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1299199677
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3758140137
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.4152120281
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3024885257
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.110634896
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3507314864
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2095776742
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1033225595
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1769118820
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2018987034
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.44858776
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3350000271
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3347682005
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4094749027
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3406798706
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3177440272
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1732622809
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.904192339
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2589247472
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2594746971
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2751229789
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.83593616
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3465473786
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2372954959
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1162756851
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2133902633
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1159426286
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3190544597
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.323637416
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1150746653
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.2208569828
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3065377947
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2682597683
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1067317893
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.2130303833
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.463194262
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.4153424089
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3267960598
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3675364201
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.4105798877
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2699909711
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3779059369
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3986742944
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.592085933
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.3792960676
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4056664939
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.779268850
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1652196189
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1142826303
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1566547411
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.3606315561
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1481960934
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.775160611
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3733023290
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2303266365
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2674670455
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.793127706
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1106211710
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.482197179
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.3244894247
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2699922161
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3740617569
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2105075487
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1663137938
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3466821170
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3705783208
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1548971805
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3666970065
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2442574936
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.428255524
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1468116826
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2255419620
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.75953749
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.872933422
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2163423527
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2062379302
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3493414352
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1539452071
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3602964608
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.154462937
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.932196942
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2280842956
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1381719672
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2371703859
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2175482575
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3286437881
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2798928505
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3868478981
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2054580750
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3178913853
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2255725563
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3752143790
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1409148013
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2556960213
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2325654633
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.176325074
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.374263767
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3528759691
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.791701498
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3286643821
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.453284975
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1692350893
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1812444271
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3659220675
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1505040727
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3455854331
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2402794493
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2072652230
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2498043542
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.361201658
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3348815258
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.600466378
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3643806126
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2797206904
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1245771894
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.251621600
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.605165934
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2138982123
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3953818620
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2975614805
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.664182369
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3593479228
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4247335746
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3752803913
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3113419903
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1232976746
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3308068797
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2609355914
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3819829819
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.102934987
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2360433228
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2127068643
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2399535395
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2874736750
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2676075222
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1058411391
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1154657172
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2340056605
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1186498058
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.324457568
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1373025755
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1428635913
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.386934981
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1615711731
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3083743235
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2807507266
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.489615600
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2550619966
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.3443376033
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4189920954
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1874110667
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.339234159
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3689734554
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.666594071
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.586002399
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.185854523
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.525132315
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3669949447
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1844985133
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1505358876
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1108687468
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3222006282
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.229356705
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2101853048
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.981256919
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.450838821
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1397169685
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1027283576
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3252228075
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2370202361
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2140285088
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2058044486
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1817354116
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2072812288
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3699422827
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1218482450
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3330927235
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.409357295
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1842753099
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1008760293
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1807217259
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3697449080
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1849644674
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2550650185
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4174092251
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3373551301
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3954098617
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3373333271
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2304939763
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1060375774
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1094856094
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1181491619
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.851991054
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3902436750
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4275591732
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3078074156
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3626089826
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.259432941
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1784255457
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.252503001
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1370613547
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2830307980
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2283954331
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.888896352
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3617126759
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.636564896
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3528349720
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4161371944
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2553356207
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.151067424
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2069462775
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.729940951
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.61475279
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3745318032
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.4202804145
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3990007628
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2005784611
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.218109421
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2836172588
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2472592140
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.2971642996
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3147750037
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1492234369
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.205933558
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3615986500
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1358415726
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1934833044
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3901148689
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.4238058969
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1536196243
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3805150269
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.721053886
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.837526956
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.900634805
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.629212123
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3535355720
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1319861305
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3126016557
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.791591983
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.815424339
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.49163361
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1821591055
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2263723992
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.829733757
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.3027292770
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2771370353
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2405356924
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.32754984
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3166817589
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1360280087
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.979694895
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4126455180
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.224456286
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.868851124
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.4151667948
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.124412370
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.429758838
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3009241809
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4064596041
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.443080740
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2287480238
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1765299295
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.887505067
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.719560016
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2252874030
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.4169268110
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.533515180
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.216524267
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2491177508
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2177361193
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.200796419
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.530367391
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.98720354
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2373678466
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2862607420
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1005357363
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1663408797
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3941755847
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1483176785
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2565101136
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.504023680
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.3062886768
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2338235005
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3763439050
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2278084596
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.4197718861
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2879164164
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4274573972
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3694015566
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.597105352
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.86498721
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2816639337
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3506037682
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2112685590
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2390549396
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3214490106
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.172284563
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1088166065
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3678663303
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2499557800
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4082896481
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.853092319
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4141733600
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2064161984
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1505279636
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1991849371
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3462978033
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3615369424
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2197540819
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1610447787
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.37618731
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3529914354
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4063838899
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3636338680
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3863321686
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.71673342
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.540818379
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2213371978
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.924585055
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2643048965
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2469851739
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1315858383
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1540826949
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2554172753
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1352235407
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2658327333
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2218073261
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3370383552
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.273169254
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3991020621
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1303279681
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2645049040
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3867585495
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1567359525
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3142836200
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1629868834
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3856332639
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.685540150
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1038635984
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2019676441
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.326882739
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.792747299
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.4029352403
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.484485187
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3601120437
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2135502752
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1698743989
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3369305634
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2801966610
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3903120321
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3134159662
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4027090839
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3954301576
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2231202742
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2005361474
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.619980504
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3778776758
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3088112633
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.494718891
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2035246862
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.204172042
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3525914392
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2827863905
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1447055729
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1391818688
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1315028230
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1994008337
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4099436776
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1894696815
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.238992735
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2255445272
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1653374338
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1461911722
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1336135951
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4139534721
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.197909020
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1040987720
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1883573326
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.4007790544
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1673867468
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3355917715
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.4030694778
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1385765913
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.319659805
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2076292969
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2827324604
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2462828288
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1945749026
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1386717389
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1418619687
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1587564728
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1666350431
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1786054221
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2386539427
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.250755236
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.43711425
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2628677004
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.436386961
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3282509353
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1935446486
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3367334041
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3856756271
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1739859713
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2535789644
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1386655849
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.3217136943
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.45445904
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.297979620
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.4286057200
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1595024537
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.410303357
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1696299883
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1944259933
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.295398636
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.136746607
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2833819265
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3574568058
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.503788914
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4268467326
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3260570205
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.472000388
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1383280098
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2933087887
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.619104608
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2822966776
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.128023749
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1746559105
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.506702908
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1722880398
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.249025513
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.130174071
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3989497544
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1015817160
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.3671434135
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1322713030
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3357457457
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.137934318
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3829263508
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.95192073
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.50623994
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2015333807
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.4293368086
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3637250129
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2151272700
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.164803511
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4224804638
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.321891078
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1118599913
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3420727789
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2388737808
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1117189878
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2283683548
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1490589603
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3035126371
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1946392605
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3897404847
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1565717028
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3777437433
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3006284262
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.13456012
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1255764005
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2533672184
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4265018459
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.709406775
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.610982566
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2131384018
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1969065523
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2776301273
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3869211840
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1143242267
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3517903795
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.713474485
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3125826037
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.638975515
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1063091894
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.681948987
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2769097883
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3545970726
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.121171711
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3186870136
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1920812662
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1740584437
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.373313663
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2794737644
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1843334521
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3280014439
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3102154367
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2924926570
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.384995046
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3059529619
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.89953366
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1181887244
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3799803213
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3240158493
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.477209104
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.924515653
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3692419517
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1234630323
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.4270670523
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3057036599
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.4283885842
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2579468904
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1928236202
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1336812217
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3802574486
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2644811520
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.913869009
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.585696631
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3987656674
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.4265315575
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.29218038
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1913986803
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3868121800
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.252677569
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1521565527
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.4093184306
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2396893325
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.882225977
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.566006441
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.450805851
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1855661523
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3664759502
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.55808048
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1401441797
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3809659221
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3499262308
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1438480774
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2216565661
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1750912152
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.3307694659
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2355541617
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.4184838484
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.600756024
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3973224230
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3316055793
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.611707294
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3861940622
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1462655284
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2152469198
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1937200107
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3778144847
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.470184547
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.565675583
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1237276991
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4065281646
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1512896303
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1420077716
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2709193254
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.2899992615
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.801154762
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2323897540
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.293868261
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3180000978
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.723555372
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2168580136
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3966385719
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2588933452
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.816413196
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2478498987
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.108462086
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3091186206
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.753627658
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2166473636
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.4115418921
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.268542940
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3060460245
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.4292267135
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3831233107
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.115156058
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4009818366
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.4124069408
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4266105892
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1240299438
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.4213064718
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1821972507
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1339760206
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.2432932572
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2563012590
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1157750052
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.754683765
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1963880408
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2787071700
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2970881932
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1235078819
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2793162932
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3019136157
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1639734063
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1230942985
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.414517861
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3770843462
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1160193093
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2707733415
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.493043182
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3854333106
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1747698358
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1288708408
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1902957294
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4270326613
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2092026275
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1561653755
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.203618974
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.859087773
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.497192067
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1926310457
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2325990755
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.731892633
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2753987199
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4117433634
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2164970347
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3746469350
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1668407082
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4275302981
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.1470492672
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.3309677816
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2758002401
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2122624899
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.191807688
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.388930063
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2136849973
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.4231771778
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.2102032535
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.430096722
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.4274561782
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1068617612
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.835148132
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2246604127
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1637906136
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2611601559
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3863718098
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3425890202
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1868425502
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3744883477
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.794485295
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3585303668
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2136611648
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3896626724
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1166981360
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.4097738294
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.502498665
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3133019986
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3032263409
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1807015838
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.732329771
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1015931478
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1294920156
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3066630427
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.554937362
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.767266395
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2279488285
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4243739667
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1664852663
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2801862276
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1252961750
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.739659858
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2944270971
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3251268151
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3443954857
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.693554195
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.191360988
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3502034961
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.338164237
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.504856565
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.886149522
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1172257276
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.382844081
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.799812708
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.4029095511
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3085936655
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2536823492
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1073226097
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2060908959
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3750242187
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4239094840
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4255114764
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.1460810229
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1109386376
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1407571254
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3374799834
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.338180484
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2296925361
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4084577727
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2444955843
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.113472186
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1680300894
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.1564975540
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3721328647
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3519724607
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.808298950
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.777216157
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1075383928
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2558446096
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.528084871
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.2208340613
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3060700541
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3521597351
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1674580132
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3745665935
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2919908435
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2151451884
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2519561904
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3301130527
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.326745331
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1240164867
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.48950302
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2730802694
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3798670730
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.987462530
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.522749934
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3755300000
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4188821977
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.625645811
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.818259151
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1974522976
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.521240831
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1078350142
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2040178690
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2221025235
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3889882195
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3954814107
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.455645984
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2428185987
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.3116318645
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3573004643
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2660602194
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3307316790
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3304446248
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1973639300
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2267950474
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.4126379037
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.1403421269
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2306236992
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3427764055
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.806705381
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2753129961
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1958995400
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3391918403
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2716324579
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3094256307
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3585878141
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3013006989
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2827803435
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2243453528
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3706607729
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.512280452
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.446672071
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3629879262
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3821329183
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2007603016
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3696737507
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.565830468
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.183646405
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2980291539
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.821165191
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4214083997
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1350527540
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2286131678
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3406066262
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3503656142
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1081213043
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3718516082
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2334920315
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1694448238
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3704999083
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3864324878
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.319518944
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.3939306905
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.731419478
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.670120510
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4010940515
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.866603785
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4281778496
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1140811703
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1346786086
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.138399780
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2979678121
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2979954553
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3024996293
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3610860077
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3225773954
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.707848850
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2067822116
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1769877684
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2319289488
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2182251324
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.19731096
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2334085440
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2450750050
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1308526782
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1784737969
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1291961487
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3049079768
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.729601205
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2481448933
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.28286458
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1657126137
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1048341854
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.166357571
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.336370058
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3058816451
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.997358908
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.97996287
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2202582467
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.625558885
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3826448577
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.193633049
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3825688448
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3135237491
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1405778992
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1055065689
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3381608035
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1929488193
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2570086935
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1097636433
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.305421519
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3105012642
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3763562323
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.465037694
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2444204723
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2836076021
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.621301168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2571984786
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3370100282
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2458606356
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2221023664
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1611453286
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2745452535
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3885509926
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.238110757
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.48786001
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3455558572
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2855524537
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3071396588
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.208185615
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3504498624
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.792184380
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2390432760
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1691496631
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1442836208
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4256720594
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1921548294
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3584488949
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1036442335
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.20154864
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2268246566
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3973091417
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.514248988
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1026676301
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.766459683
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3153919316
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2988901475
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1855889985
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4054331882
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.364709168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.371619619
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1675432691
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3871004697
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.174936637
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2959549791
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1555866013
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1948296575
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.876575732
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1285553090
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3112610800
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1373059552
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.987878021
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.789801506
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3606557733
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4280926761
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2097558287



Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3389530582 Sep 09 08:02:43 AM UTC 24 Sep 09 08:02:57 AM UTC 24 740556555 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1014568472 Sep 09 08:02:58 AM UTC 24 Sep 09 08:03:13 AM UTC 24 3894018177 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1828843793 Sep 09 08:03:02 AM UTC 24 Sep 09 08:03:15 AM UTC 24 2562511511 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1729250817 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:46 AM UTC 24 16499453 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3574540870 Sep 09 08:03:43 AM UTC 24 Sep 09 08:03:48 AM UTC 24 361114044 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2950486138 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:49 AM UTC 24 538811499 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2477497330 Sep 09 08:03:15 AM UTC 24 Sep 09 08:03:50 AM UTC 24 7929445292 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.4152120281 Sep 09 08:03:49 AM UTC 24 Sep 09 08:03:51 AM UTC 24 25340910 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2522949501 Sep 09 08:03:48 AM UTC 24 Sep 09 08:03:53 AM UTC 24 2387570671 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2463732049 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:54 AM UTC 24 1001721717 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.44858776 Sep 09 08:03:49 AM UTC 24 Sep 09 08:03:54 AM UTC 24 392290646 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1181491619 Sep 09 08:03:53 AM UTC 24 Sep 09 08:03:55 AM UTC 24 19563763 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2830307980 Sep 09 08:03:53 AM UTC 24 Sep 09 08:03:57 AM UTC 24 494697764 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1370613547 Sep 09 08:03:51 AM UTC 24 Sep 09 08:03:58 AM UTC 24 354492836 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1360666597 Sep 09 08:03:45 AM UTC 24 Sep 09 08:04:02 AM UTC 24 7323795046 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3406798706 Sep 09 08:03:47 AM UTC 24 Sep 09 08:04:03 AM UTC 24 2930268467 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2628677004 Sep 09 08:04:01 AM UTC 24 Sep 09 08:04:08 AM UTC 24 1399153583 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2462828288 Sep 09 08:04:09 AM UTC 24 Sep 09 08:04:11 AM UTC 24 77690293 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3617126759 Sep 09 08:03:52 AM UTC 24 Sep 09 08:04:14 AM UTC 24 6474219323 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.252503001 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:15 AM UTC 24 1537014846 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3282509353 Sep 09 08:04:09 AM UTC 24 Sep 09 08:04:16 AM UTC 24 838559041 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3528349720 Sep 09 08:03:51 AM UTC 24 Sep 09 08:04:17 AM UTC 24 2969245123 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1299199677 Sep 09 08:03:14 AM UTC 24 Sep 09 08:04:17 AM UTC 24 1566456394 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1288708408 Sep 09 08:04:12 AM UTC 24 Sep 09 08:04:20 AM UTC 24 412547077 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1935446486 Sep 09 08:03:53 AM UTC 24 Sep 09 08:04:21 AM UTC 24 1337057387 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2018987034 Sep 09 08:03:46 AM UTC 24 Sep 09 08:04:27 AM UTC 24 2130320617 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1639734063 Sep 09 08:04:20 AM UTC 24 Sep 09 08:04:31 AM UTC 24 677569534 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3347682005 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:33 AM UTC 24 13912268389 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1587564728 Sep 09 08:03:57 AM UTC 24 Sep 09 08:04:38 AM UTC 24 736818417 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1160193093 Sep 09 08:04:18 AM UTC 24 Sep 09 08:04:39 AM UTC 24 4485287898 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1561653755 Sep 09 08:04:22 AM UTC 24 Sep 09 08:04:39 AM UTC 24 4896563317 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2360895490 Sep 09 08:04:04 AM UTC 24 Sep 09 08:04:40 AM UTC 24 1898331432 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2095776742 Sep 09 08:03:47 AM UTC 24 Sep 09 08:04:41 AM UTC 24 2715769056 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2283954331 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:46 AM UTC 24 1335152009 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.493043182 Sep 09 08:04:40 AM UTC 24 Sep 09 08:04:46 AM UTC 24 1399164132 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1739859713 Sep 09 08:03:57 AM UTC 24 Sep 09 08:04:47 AM UTC 24 760327565 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2970881932 Sep 09 08:04:47 AM UTC 24 Sep 09 08:04:49 AM UTC 24 14610061 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1747698358 Sep 09 08:04:47 AM UTC 24 Sep 09 08:04:52 AM UTC 24 369304889 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1418619687 Sep 09 08:03:58 AM UTC 24 Sep 09 08:04:55 AM UTC 24 93466507434 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4270326613 Sep 09 08:04:41 AM UTC 24 Sep 09 08:04:59 AM UTC 24 393004042 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3019136157 Sep 09 08:04:28 AM UTC 24 Sep 09 08:05:04 AM UTC 24 12471860921 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3078074156 Sep 09 08:03:51 AM UTC 24 Sep 09 08:05:10 AM UTC 24 3433357760 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4275591732 Sep 09 08:03:51 AM UTC 24 Sep 09 08:05:10 AM UTC 24 34849462587 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.28286458 Sep 09 08:04:48 AM UTC 24 Sep 09 08:05:11 AM UTC 24 850207824 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1291961487 Sep 09 08:04:56 AM UTC 24 Sep 09 08:05:14 AM UTC 24 1067843074 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.250755236 Sep 09 08:03:56 AM UTC 24 Sep 09 08:05:17 AM UTC 24 4027052325 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3507314864 Sep 09 08:03:47 AM UTC 24 Sep 09 08:05:19 AM UTC 24 48129296682 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.166357571 Sep 09 08:05:06 AM UTC 24 Sep 09 08:05:21 AM UTC 24 4858756848 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2334085440 Sep 09 08:05:05 AM UTC 24 Sep 09 08:05:21 AM UTC 24 2838708947 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1984847046 Sep 09 08:03:49 AM UTC 24 Sep 09 08:05:22 AM UTC 24 11139537997 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.729601205 Sep 09 08:05:18 AM UTC 24 Sep 09 08:05:24 AM UTC 24 680066266 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1769877684 Sep 09 08:05:25 AM UTC 24 Sep 09 08:05:27 AM UTC 24 44954369 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1657126137 Sep 09 08:05:22 AM UTC 24 Sep 09 08:05:41 AM UTC 24 376854608 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1929488193 Sep 09 08:05:29 AM UTC 24 Sep 09 08:05:46 AM UTC 24 2280098127 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.19731096 Sep 09 08:05:10 AM UTC 24 Sep 09 08:06:02 AM UTC 24 9707079025 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3135237491 Sep 09 08:06:03 AM UTC 24 Sep 09 08:06:22 AM UTC 24 861708607 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3471559393 Sep 09 08:03:44 AM UTC 24 Sep 09 08:06:25 AM UTC 24 8435276562 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.625558885 Sep 09 08:06:26 AM UTC 24 Sep 09 08:06:36 AM UTC 24 1388133209 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3908435718 Sep 09 08:03:43 AM UTC 24 Sep 09 08:06:42 AM UTC 24 13276649799 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.843331399 Sep 09 08:03:48 AM UTC 24 Sep 09 08:06:59 AM UTC 24 24065023351 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3626089826 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:07 AM UTC 24 24344423233 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3335543092 Sep 09 08:03:42 AM UTC 24 Sep 09 08:07:17 AM UTC 24 1199498890 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3105012642 Sep 09 08:06:36 AM UTC 24 Sep 09 08:07:19 AM UTC 24 3047833965 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1055065689 Sep 09 08:07:20 AM UTC 24 Sep 09 08:07:26 AM UTC 24 1399287552 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.259432941 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:27 AM UTC 24 19134591040 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.43711425 Sep 09 08:03:56 AM UTC 24 Sep 09 08:07:30 AM UTC 24 6573933688 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2450750050 Sep 09 08:05:22 AM UTC 24 Sep 09 08:07:36 AM UTC 24 3291571945 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1666350431 Sep 09 08:04:04 AM UTC 24 Sep 09 08:07:42 AM UTC 24 5018562823 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3058816451 Sep 09 08:07:43 AM UTC 24 Sep 09 08:07:45 AM UTC 24 23203143 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1230942985 Sep 09 08:04:41 AM UTC 24 Sep 09 08:07:46 AM UTC 24 18263191541 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2654665920 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:59 AM UTC 24 36396042668 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1097636433 Sep 09 08:07:31 AM UTC 24 Sep 09 08:08:02 AM UTC 24 2990351343 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.48786001 Sep 09 08:07:46 AM UTC 24 Sep 09 08:08:07 AM UTC 24 528737498 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2202582467 Sep 09 08:06:42 AM UTC 24 Sep 09 08:08:16 AM UTC 24 13662741248 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2787071700 Sep 09 08:04:32 AM UTC 24 Sep 09 08:08:20 AM UTC 24 8828543570 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3856756271 Sep 09 08:03:56 AM UTC 24 Sep 09 08:08:25 AM UTC 24 5845036483 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1026676301 Sep 09 08:10:06 AM UTC 24 Sep 09 08:10:36 AM UTC 24 8200634036 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1786054221 Sep 09 08:04:01 AM UTC 24 Sep 09 08:08:31 AM UTC 24 3945714695 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1308526782 Sep 09 08:05:20 AM UTC 24 Sep 09 08:08:32 AM UTC 24 115427411566 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1611453286 Sep 09 08:08:09 AM UTC 24 Sep 09 08:08:32 AM UTC 24 595967897 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3770843462 Sep 09 08:04:15 AM UTC 24 Sep 09 08:08:36 AM UTC 24 6376715405 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.208185615 Sep 09 08:08:26 AM UTC 24 Sep 09 08:08:37 AM UTC 24 670271206 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3885509926 Sep 09 08:08:38 AM UTC 24 Sep 09 08:08:47 AM UTC 24 3047523011 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.636564896 Sep 09 08:03:49 AM UTC 24 Sep 09 08:08:49 AM UTC 24 10870121085 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.110634896 Sep 09 08:03:48 AM UTC 24 Sep 09 08:09:01 AM UTC 24 1934822523 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.621301168 Sep 09 08:08:32 AM UTC 24 Sep 09 08:10:01 AM UTC 24 9310821124 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.306013334 Sep 09 08:02:57 AM UTC 24 Sep 09 08:10:04 AM UTC 24 20028093445 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3370100282 Sep 09 08:08:49 AM UTC 24 Sep 09 08:10:05 AM UTC 24 11853402242 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.465037694 Sep 09 08:10:05 AM UTC 24 Sep 09 08:10:07 AM UTC 24 49060908 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2836076021 Sep 09 08:08:33 AM UTC 24 Sep 09 08:10:12 AM UTC 24 11429429748 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2571984786 Sep 09 08:08:22 AM UTC 24 Sep 09 08:10:12 AM UTC 24 12662093449 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1048341854 Sep 09 08:04:53 AM UTC 24 Sep 09 08:10:18 AM UTC 24 54220401385 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4136666043 Sep 09 08:03:47 AM UTC 24 Sep 09 08:10:27 AM UTC 24 26112462122 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.20154864 Sep 09 08:10:18 AM UTC 24 Sep 09 08:10:31 AM UTC 24 769444534 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2182251324 Sep 09 08:05:12 AM UTC 24 Sep 09 08:10:31 AM UTC 24 20750812877 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2855524537 Sep 09 08:09:01 AM UTC 24 Sep 09 08:10:43 AM UTC 24 5039039209 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2092026275 Sep 09 08:04:17 AM UTC 24 Sep 09 08:10:45 AM UTC 24 24241619105 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3826448577 Sep 09 08:07:28 AM UTC 24 Sep 09 08:10:46 AM UTC 24 4385589627 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2827324604 Sep 09 08:03:58 AM UTC 24 Sep 09 08:10:47 AM UTC 24 25990709668 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3854333106 Sep 09 08:04:39 AM UTC 24 Sep 09 08:10:49 AM UTC 24 7722445337 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3973091417 Sep 09 08:10:48 AM UTC 24 Sep 09 08:10:55 AM UTC 24 2092246514 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1386717389 Sep 09 08:04:00 AM UTC 24 Sep 09 08:10:59 AM UTC 24 4806441404 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.305421519 Sep 09 08:05:47 AM UTC 24 Sep 09 08:10:59 AM UTC 24 41300389994 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4256720594 Sep 09 08:10:31 AM UTC 24 Sep 09 08:11:01 AM UTC 24 718677919 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4094749027 Sep 09 08:03:46 AM UTC 24 Sep 09 08:11:04 AM UTC 24 5785142986 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.792184380 Sep 09 08:11:02 AM UTC 24 Sep 09 08:11:04 AM UTC 24 40312512 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1033225595 Sep 09 08:03:48 AM UTC 24 Sep 09 08:11:19 AM UTC 24 86150882576 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1948296575 Sep 09 08:11:05 AM UTC 24 Sep 09 08:11:20 AM UTC 24 8552650221 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3153919316 Sep 09 08:11:00 AM UTC 24 Sep 09 08:11:21 AM UTC 24 624533217 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.414517861 Sep 09 08:04:40 AM UTC 24 Sep 09 08:11:22 AM UTC 24 22017222502 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.193633049 Sep 09 08:07:28 AM UTC 24 Sep 09 08:11:29 AM UTC 24 39415883044 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3825688448 Sep 09 08:05:42 AM UTC 24 Sep 09 08:11:33 AM UTC 24 19863417862 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1855889985 Sep 09 08:10:33 AM UTC 24 Sep 09 08:11:34 AM UTC 24 1092560858 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3049079768 Sep 09 08:05:00 AM UTC 24 Sep 09 08:11:34 AM UTC 24 19353397870 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.987878021 Sep 09 08:11:04 AM UTC 24 Sep 09 08:11:34 AM UTC 24 750537393 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.876575732 Sep 09 08:11:22 AM UTC 24 Sep 09 08:11:35 AM UTC 24 1418354102 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2097558287 Sep 09 08:11:34 AM UTC 24 Sep 09 08:11:52 AM UTC 24 2769669702 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1442836208 Sep 09 08:10:37 AM UTC 24 Sep 09 08:11:55 AM UTC 24 9831799617 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3112610800 Sep 09 08:11:52 AM UTC 24 Sep 09 08:11:59 AM UTC 24 352228012 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2707733415 Sep 09 08:04:18 AM UTC 24 Sep 09 08:12:05 AM UTC 24 72724170325 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1921548294 Sep 09 08:10:55 AM UTC 24 Sep 09 08:12:16 AM UTC 24 4163056586 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2745452535 Sep 09 08:08:17 AM UTC 24 Sep 09 08:12:20 AM UTC 24 87092410947 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.364709168 Sep 09 08:12:21 AM UTC 24 Sep 09 08:12:23 AM UTC 24 14428589 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3606557733 Sep 09 08:12:06 AM UTC 24 Sep 09 08:12:24 AM UTC 24 420317777 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.323181055 Sep 09 08:05:23 AM UTC 24 Sep 09 08:12:26 AM UTC 24 79390436687 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3344526823 Sep 09 08:03:00 AM UTC 24 Sep 09 08:12:32 AM UTC 24 24813990156 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3190544597 Sep 09 08:12:24 AM UTC 24 Sep 09 08:12:33 AM UTC 24 1481199404 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.174936637 Sep 09 08:11:30 AM UTC 24 Sep 09 08:12:34 AM UTC 24 4253704346 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3871004697 Sep 09 08:11:34 AM UTC 24 Sep 09 08:12:46 AM UTC 24 15092179429 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1162756851 Sep 09 08:12:33 AM UTC 24 Sep 09 08:13:01 AM UTC 24 2149973545 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.514248988 Sep 09 08:10:47 AM UTC 24 Sep 09 08:13:06 AM UTC 24 5561034522 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3758140137 Sep 09 08:03:47 AM UTC 24 Sep 09 08:13:07 AM UTC 24 10846547294 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1769118820 Sep 09 08:03:45 AM UTC 24 Sep 09 08:13:18 AM UTC 24 10276310240 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1193304196 Sep 09 08:03:16 AM UTC 24 Sep 09 08:13:21 AM UTC 24 13193284715 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2793162932 Sep 09 08:04:33 AM UTC 24 Sep 09 08:13:31 AM UTC 24 26222124542 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1159426286 Sep 09 08:13:32 AM UTC 24 Sep 09 08:13:39 AM UTC 24 697122836 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3065377947 Sep 09 08:13:01 AM UTC 24 Sep 09 08:13:41 AM UTC 24 1463463833 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3584488949 Sep 09 08:10:50 AM UTC 24 Sep 09 08:13:44 AM UTC 24 49898798415 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3071396588 Sep 09 08:08:02 AM UTC 24 Sep 09 08:13:45 AM UTC 24 4557516710 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2751229789 Sep 09 08:12:47 AM UTC 24 Sep 09 08:13:53 AM UTC 24 828135283 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1732622809 Sep 09 08:13:53 AM UTC 24 Sep 09 08:13:55 AM UTC 24 29788752 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1150746653 Sep 09 08:13:45 AM UTC 24 Sep 09 08:14:01 AM UTC 24 610376113 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3180145993 Sep 09 08:02:45 AM UTC 24 Sep 09 08:14:13 AM UTC 24 22092896706 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.97996287 Sep 09 08:07:08 AM UTC 24 Sep 09 08:14:50 AM UTC 24 36486201286 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1405778992 Sep 09 08:06:23 AM UTC 24 Sep 09 08:14:50 AM UTC 24 36497418670 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2594746971 Sep 09 08:13:07 AM UTC 24 Sep 09 08:14:59 AM UTC 24 84137240044 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2481448933 Sep 09 08:05:15 AM UTC 24 Sep 09 08:15:03 AM UTC 24 3141385950 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1555866013 Sep 09 08:11:55 AM UTC 24 Sep 09 08:15:14 AM UTC 24 57415247315 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2959549791 Sep 09 08:12:00 AM UTC 24 Sep 09 08:15:16 AM UTC 24 4993181448 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2699909711 Sep 09 08:14:51 AM UTC 24 Sep 09 08:15:19 AM UTC 24 15897418772 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.3792960676 Sep 09 08:13:56 AM UTC 24 Sep 09 08:15:23 AM UTC 24 444245124 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.4153424089 Sep 09 08:15:03 AM UTC 24 Sep 09 08:15:26 AM UTC 24 743146291 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1652196189 Sep 09 08:15:14 AM UTC 24 Sep 09 08:15:27 AM UTC 24 2667761340 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3986742944 Sep 09 08:15:28 AM UTC 24 Sep 09 08:15:33 AM UTC 24 3372059085 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2458606356 Sep 09 08:08:47 AM UTC 24 Sep 09 08:15:59 AM UTC 24 86229824383 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2707502035 Sep 09 08:02:43 AM UTC 24 Sep 09 08:16:00 AM UTC 24 59638820500 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2988901475 Sep 09 08:10:13 AM UTC 24 Sep 09 08:16:01 AM UTC 24 23239794022 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4056664939 Sep 09 08:16:01 AM UTC 24 Sep 09 08:16:19 AM UTC 24 402595977 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1067317893 Sep 09 08:16:20 AM UTC 24 Sep 09 08:16:23 AM UTC 24 19511519 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2699922161 Sep 09 08:16:24 AM UTC 24 Sep 09 08:16:36 AM UTC 24 930972903 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3504498624 Sep 09 08:10:44 AM UTC 24 Sep 09 08:16:37 AM UTC 24 8285268805 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.83593616 Sep 09 08:13:41 AM UTC 24 Sep 09 08:16:41 AM UTC 24 5799135574 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.779268850 Sep 09 08:14:51 AM UTC 24 Sep 09 08:16:49 AM UTC 24 2258414150 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2067822116 Sep 09 08:05:11 AM UTC 24 Sep 09 08:16:54 AM UTC 24 9849408157 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4280926761 Sep 09 08:11:21 AM UTC 24 Sep 09 08:17:06 AM UTC 24 10504538371 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3267960598 Sep 09 08:16:00 AM UTC 24 Sep 09 08:17:17 AM UTC 24 2895174498 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3465473786 Sep 09 08:13:39 AM UTC 24 Sep 09 08:17:20 AM UTC 24 27724227252 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1839283014 Sep 09 08:03:51 AM UTC 24 Sep 09 08:17:21 AM UTC 24 65959401149 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2386539427 Sep 09 08:03:54 AM UTC 24 Sep 09 08:17:23 AM UTC 24 12401035483 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.463194262 Sep 09 08:15:17 AM UTC 24 Sep 09 08:17:31 AM UTC 24 14297394106 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.2208569828 Sep 09 08:12:33 AM UTC 24 Sep 09 08:17:33 AM UTC 24 5035867553 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.482197179 Sep 09 08:17:35 AM UTC 24 Sep 09 08:17:40 AM UTC 24 5599749646 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.793127706 Sep 09 08:16:50 AM UTC 24 Sep 09 08:17:41 AM UTC 24 4280268829 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1373059552 Sep 09 08:11:36 AM UTC 24 Sep 09 08:17:42 AM UTC 24 14678903516 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.436386961 Sep 09 08:04:00 AM UTC 24 Sep 09 08:17:55 AM UTC 24 10978890577 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1566547411 Sep 09 08:17:56 AM UTC 24 Sep 09 08:17:58 AM UTC 24 24046825 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2268246566 Sep 09 08:10:28 AM UTC 24 Sep 09 08:18:01 AM UTC 24 7068824524 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3466821170 Sep 09 08:17:18 AM UTC 24 Sep 09 08:18:13 AM UTC 24 764157294 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2589247472 Sep 09 08:13:20 AM UTC 24 Sep 09 08:18:22 AM UTC 24 4476379687 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.775160611 Sep 09 08:17:21 AM UTC 24 Sep 09 08:18:31 AM UTC 24 9943124545 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1784737969 Sep 09 08:04:50 AM UTC 24 Sep 09 08:18:38 AM UTC 24 50257418536 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2133902633 Sep 09 08:12:34 AM UTC 24 Sep 09 08:18:50 AM UTC 24 29105077414 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3602964608 Sep 09 08:17:59 AM UTC 24 Sep 09 08:18:50 AM UTC 24 750940174 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3733023290 Sep 09 08:17:07 AM UTC 24 Sep 09 08:18:52 AM UTC 24 2667502702 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1285553090 Sep 09 08:11:23 AM UTC 24 Sep 09 08:19:09 AM UTC 24 14458130971 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3675364201 Sep 09 08:15:33 AM UTC 24 Sep 09 08:19:18 AM UTC 24 6929459538 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2303266365 Sep 09 08:17:42 AM UTC 24 Sep 09 08:19:18 AM UTC 24 12270592548 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2278368496 Sep 09 08:03:32 AM UTC 24 Sep 09 08:19:21 AM UTC 24 11288475350 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1381719672 Sep 09 08:18:51 AM UTC 24 Sep 09 08:19:24 AM UTC 24 769062033 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1468116826 Sep 09 08:18:51 AM UTC 24 Sep 09 08:19:26 AM UTC 24 731920341 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3493414352 Sep 09 08:19:22 AM UTC 24 Sep 09 08:19:28 AM UTC 24 1470211917 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2163423527 Sep 09 08:18:33 AM UTC 24 Sep 09 08:19:52 AM UTC 24 6465950854 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.932196942 Sep 09 08:19:29 AM UTC 24 Sep 09 08:20:01 AM UTC 24 2295442147 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1548971805 Sep 09 08:20:02 AM UTC 24 Sep 09 08:20:04 AM UTC 24 20610029 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2105075487 Sep 09 08:17:43 AM UTC 24 Sep 09 08:20:07 AM UTC 24 4324884899 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1663137938 Sep 09 08:16:42 AM UTC 24 Sep 09 08:20:12 AM UTC 24 12175669699 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.374263767 Sep 09 08:20:05 AM UTC 24 Sep 09 08:20:38 AM UTC 24 6326833872 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.592085933 Sep 09 08:15:27 AM UTC 24 Sep 09 08:20:42 AM UTC 24 1925980466 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3177440272 Sep 09 08:13:08 AM UTC 24 Sep 09 08:20:46 AM UTC 24 10809805827 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.336370058 Sep 09 08:06:59 AM UTC 24 Sep 09 08:20:46 AM UTC 24 27267809963 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4054331882 Sep 09 08:11:35 AM UTC 24 Sep 09 08:20:50 AM UTC 24 10333149404 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.453284975 Sep 09 08:20:47 AM UTC 24 Sep 09 08:20:57 AM UTC 24 3338156359 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2054580750 Sep 09 08:20:47 AM UTC 24 Sep 09 08:21:00 AM UTC 24 2813178465 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3779059369 Sep 09 08:15:00 AM UTC 24 Sep 09 08:21:01 AM UTC 24 26583581648 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2255419620 Sep 09 08:19:27 AM UTC 24 Sep 09 08:21:07 AM UTC 24 5485742115 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1094856094 Sep 09 08:03:51 AM UTC 24 Sep 09 08:21:07 AM UTC 24 99619431533 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1106211710 Sep 09 08:16:55 AM UTC 24 Sep 09 08:21:11 AM UTC 24 5275756217 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2682597683 Sep 09 08:15:20 AM UTC 24 Sep 09 08:21:14 AM UTC 24 8647997363 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.428255524 Sep 09 08:18:53 AM UTC 24 Sep 09 08:21:14 AM UTC 24 46568759558 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2325654633 Sep 09 08:21:07 AM UTC 24 Sep 09 08:21:14 AM UTC 24 353942027 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2175482575 Sep 09 08:21:15 AM UTC 24 Sep 09 08:21:17 AM UTC 24 32635961 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1409148013 Sep 09 08:20:39 AM UTC 24 Sep 09 08:21:23 AM UTC 24 1054335148 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1036442335 Sep 09 08:10:08 AM UTC 24 Sep 09 08:21:24 AM UTC 24 22847082621 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2797206904 Sep 09 08:21:18 AM UTC 24 Sep 09 08:21:29 AM UTC 24 413258483 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3481780082 Sep 09 08:15:24 AM UTC 24 Sep 09 08:21:42 AM UTC 24 5360648361 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3902436750 Sep 09 08:03:51 AM UTC 24 Sep 09 08:22:02 AM UTC 24 69841389664 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.791701498 Sep 09 08:21:15 AM UTC 24 Sep 09 08:22:04 AM UTC 24 1002520256 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3868478981 Sep 09 08:20:51 AM UTC 24 Sep 09 08:22:13 AM UTC 24 26933891544 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3381608035 Sep 09 08:07:18 AM UTC 24 Sep 09 08:22:13 AM UTC 24 13467962763 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1675432691 Sep 09 08:11:35 AM UTC 24 Sep 09 08:22:18 AM UTC 24 25649296331 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.361201658 Sep 09 08:21:43 AM UTC 24 Sep 09 08:22:23 AM UTC 24 1937907815 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2138982123 Sep 09 08:22:14 AM UTC 24 Sep 09 08:22:35 AM UTC 24 5795409642 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2319289488 Sep 09 08:04:51 AM UTC 24 Sep 09 08:22:40 AM UTC 24 43854340322 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.238110757 Sep 09 08:08:36 AM UTC 24 Sep 09 08:22:42 AM UTC 24 30997839112 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2444204723 Sep 09 08:08:00 AM UTC 24 Sep 09 08:22:43 AM UTC 24 129894153171 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.600466378 Sep 09 08:22:40 AM UTC 24 Sep 09 08:22:48 AM UTC 24 5578366653 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2674670455 Sep 09 08:17:41 AM UTC 24 Sep 09 08:22:52 AM UTC 24 21003079044 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.997358908 Sep 09 08:05:42 AM UTC 24 Sep 09 08:22:52 AM UTC 24 17498207888 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1812444271 Sep 09 08:22:53 AM UTC 24 Sep 09 08:22:55 AM UTC 24 15437628 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2221023664 Sep 09 08:07:47 AM UTC 24 Sep 09 08:23:04 AM UTC 24 44917625635 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3455854331 Sep 09 08:22:05 AM UTC 24 Sep 09 08:23:28 AM UTC 24 1638301531 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1142826303 Sep 09 08:17:21 AM UTC 24 Sep 09 08:23:46 AM UTC 24 7466303065 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2280842956 Sep 09 08:18:22 AM UTC 24 Sep 09 08:23:50 AM UTC 24 4347181990 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2255725563 Sep 09 08:21:07 AM UTC 24 Sep 09 08:23:59 AM UTC 24 8221412721 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3178913853 Sep 09 08:21:12 AM UTC 24 Sep 09 08:24:00 AM UTC 24 5105375309 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.251621600 Sep 09 08:22:49 AM UTC 24 Sep 09 08:24:07 AM UTC 24 3933759596 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2390432760 Sep 09 08:10:13 AM UTC 24 Sep 09 08:24:08 AM UTC 24 50564895013 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2062379302 Sep 09 08:18:40 AM UTC 24 Sep 09 08:24:11 AM UTC 24 44159251560 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2127068643 Sep 09 08:22:56 AM UTC 24 Sep 09 08:24:12 AM UTC 24 937904653 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2609355914 Sep 09 08:23:51 AM UTC 24 Sep 09 08:24:13 AM UTC 24 813583484 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1691496631 Sep 09 08:10:46 AM UTC 24 Sep 09 08:24:17 AM UTC 24 17350572117 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.75953749 Sep 09 08:19:25 AM UTC 24 Sep 09 08:24:18 AM UTC 24 21877737839 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1058411391 Sep 09 08:24:05 AM UTC 24 Sep 09 08:24:19 AM UTC 24 721254916 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.102934987 Sep 09 08:24:13 AM UTC 24 Sep 09 08:24:19 AM UTC 24 394249608 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1692350893 Sep 09 08:22:19 AM UTC 24 Sep 09 08:24:37 AM UTC 24 8780238039 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2975614805 Sep 09 08:24:38 AM UTC 24 Sep 09 08:24:40 AM UTC 24 33318344 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3752803913 Sep 09 08:24:01 AM UTC 24 Sep 09 08:24:42 AM UTC 24 754914071 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1505040727 Sep 09 08:22:14 AM UTC 24 Sep 09 08:24:48 AM UTC 24 60361025437 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2874736750 Sep 09 08:24:20 AM UTC 24 Sep 09 08:24:56 AM UTC 24 4060967277 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4189920954 Sep 09 08:24:41 AM UTC 24 Sep 09 08:25:08 AM UTC 24 3548820025 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%