Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1034
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.39 68.39 92.23 92.23 70.38 70.38 83.68 83.68 33.33 33.33 82.70 82.70 93.57 93.57 22.85 22.85 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2477497330
87.18 18.79 97.79 5.56 84.12 13.74 92.77 9.09 90.48 57.14 90.76 8.06 96.20 2.63 58.14 35.28 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2360895490
90.80 3.62 98.12 0.33 86.14 2.01 95.70 2.93 90.48 0.00 92.18 1.42 96.78 0.58 76.23 18.10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2950486138
92.50 1.69 98.61 0.49 86.14 0.00 95.70 0.00 100.00 9.52 93.13 0.95 97.66 0.88 76.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1984847046
93.94 1.45 98.86 0.25 89.10 2.96 96.52 0.83 100.00 0.00 95.02 1.90 97.66 0.00 80.44 4.20 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.843331399
94.72 0.78 98.86 0.00 89.81 0.71 98.76 2.24 100.00 0.00 95.50 0.47 97.66 0.00 82.45 2.01 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1360666597
95.48 0.76 98.86 0.00 90.17 0.36 98.76 0.00 100.00 0.00 95.50 0.00 97.66 0.00 87.39 4.94 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1343340875
96.03 0.56 99.10 0.25 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.24 97.81 0.15 90.68 3.29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2654665920
96.32 0.29 99.10 0.00 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.00 97.81 0.00 92.69 2.01 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2278368496
96.48 0.16 99.18 0.08 90.17 0.00 99.59 0.83 100.00 0.00 95.73 0.00 97.81 0.00 92.87 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2522949501
96.61 0.14 99.18 0.00 90.17 0.00 99.66 0.07 100.00 0.00 95.73 0.00 98.68 0.88 92.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3268890178
96.74 0.13 99.18 0.00 90.17 0.00 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 93.78 0.91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3335543092
96.86 0.11 99.18 0.00 90.40 0.24 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 94.33 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3398847282
96.96 0.10 99.18 0.00 90.40 0.00 99.66 0.00 100.00 0.00 95.73 0.00 98.68 0.00 95.06 0.73 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1839283014
97.05 0.09 99.18 0.00 90.76 0.36 99.72 0.07 100.00 0.00 95.73 0.00 98.68 0.00 95.25 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1729250817
97.13 0.08 99.18 0.00 90.88 0.12 99.72 0.00 100.00 0.00 96.21 0.47 98.68 0.00 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3768478288
97.21 0.08 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.68 0.00 95.80 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3595310330
97.28 0.07 99.18 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.21 0.00 98.68 0.00 96.16 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.323181055
97.34 0.06 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.44 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3753620047
97.39 0.05 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4136666043
97.42 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.71 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3065585998
97.45 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1014568472
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3481780082
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1159154091

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779782087
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2306030330
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1278456786
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223699099
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.326656827
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2153090999
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.450527380
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.796959038
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4205872414
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4158012526
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2766551116
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.816664740
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61107819
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1298845910
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.962079567
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2257344710
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2064118992
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2168635177
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.152054983
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1937168217
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3741624309
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3517336145
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2393116725
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1583069599
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.714746564
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3316091639
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3192778756
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1696871599
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1634216345
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.928710998
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2165211593
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.343888688
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4113846924
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.452299235
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2308227210
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.920155578
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3176042476
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.781047248
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1387852168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1847548202
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2154646461
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2514694958
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2803788174
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2326938022
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2115888729
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3669046291
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3741474874
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.948965705
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730244314
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.414602708
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2008458932
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3887949007
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1130249595
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.408350002
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2110102541
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.114630325
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2944493440
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2848766194
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.147888327
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2100792613
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2207535632
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1026607163
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3449193498
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670932546
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3784477556
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1882678657
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3042070500
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.673749070
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.220746348
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.943839782
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2328550734
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3306959132
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3739927501
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.748282670
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2549364997
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2553478592
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3379709561
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1265302495
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3920737204
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3820336260
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.622369848
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.567221264
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3999353506
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3687578577
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/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.336370058
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3058816451
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/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3381608035
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1929488193
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2570086935
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1097636433
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.305421519
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3105012642
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3763562323
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.465037694
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2444204723
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2836076021
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.621301168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2571984786
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3370100282
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2458606356
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2221023664
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1611453286
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2745452535
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3885509926
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.238110757
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.48786001
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3455558572
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2855524537
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3071396588
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.208185615
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3504498624
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.792184380
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2390432760
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1691496631
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1442836208
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4256720594
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1921548294
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3584488949
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1036442335
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.20154864
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2268246566
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3973091417
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.514248988
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/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3153919316
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2988901475
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1855889985
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4054331882
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.364709168
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.371619619
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1675432691
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3871004697
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.174936637
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2959549791
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1555866013
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1948296575
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.876575732
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1285553090
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3112610800
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1373059552
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.987878021
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.789801506
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3606557733
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4280926761
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2097558287



Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3389530582 Sep 09 08:02:43 AM UTC 24 Sep 09 08:02:57 AM UTC 24 740556555 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1014568472 Sep 09 08:02:58 AM UTC 24 Sep 09 08:03:13 AM UTC 24 3894018177 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1828843793 Sep 09 08:03:02 AM UTC 24 Sep 09 08:03:15 AM UTC 24 2562511511 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1729250817 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:46 AM UTC 24 16499453 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3574540870 Sep 09 08:03:43 AM UTC 24 Sep 09 08:03:48 AM UTC 24 361114044 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2950486138 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:49 AM UTC 24 538811499 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2477497330 Sep 09 08:03:15 AM UTC 24 Sep 09 08:03:50 AM UTC 24 7929445292 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.4152120281 Sep 09 08:03:49 AM UTC 24 Sep 09 08:03:51 AM UTC 24 25340910 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2522949501 Sep 09 08:03:48 AM UTC 24 Sep 09 08:03:53 AM UTC 24 2387570671 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2463732049 Sep 09 08:03:44 AM UTC 24 Sep 09 08:03:54 AM UTC 24 1001721717 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.44858776 Sep 09 08:03:49 AM UTC 24 Sep 09 08:03:54 AM UTC 24 392290646 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1181491619 Sep 09 08:03:53 AM UTC 24 Sep 09 08:03:55 AM UTC 24 19563763 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2830307980 Sep 09 08:03:53 AM UTC 24 Sep 09 08:03:57 AM UTC 24 494697764 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1370613547 Sep 09 08:03:51 AM UTC 24 Sep 09 08:03:58 AM UTC 24 354492836 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1360666597 Sep 09 08:03:45 AM UTC 24 Sep 09 08:04:02 AM UTC 24 7323795046 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3406798706 Sep 09 08:03:47 AM UTC 24 Sep 09 08:04:03 AM UTC 24 2930268467 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2628677004 Sep 09 08:04:01 AM UTC 24 Sep 09 08:04:08 AM UTC 24 1399153583 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2462828288 Sep 09 08:04:09 AM UTC 24 Sep 09 08:04:11 AM UTC 24 77690293 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3617126759 Sep 09 08:03:52 AM UTC 24 Sep 09 08:04:14 AM UTC 24 6474219323 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.252503001 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:15 AM UTC 24 1537014846 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3282509353 Sep 09 08:04:09 AM UTC 24 Sep 09 08:04:16 AM UTC 24 838559041 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3528349720 Sep 09 08:03:51 AM UTC 24 Sep 09 08:04:17 AM UTC 24 2969245123 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1299199677 Sep 09 08:03:14 AM UTC 24 Sep 09 08:04:17 AM UTC 24 1566456394 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1288708408 Sep 09 08:04:12 AM UTC 24 Sep 09 08:04:20 AM UTC 24 412547077 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1935446486 Sep 09 08:03:53 AM UTC 24 Sep 09 08:04:21 AM UTC 24 1337057387 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2018987034 Sep 09 08:03:46 AM UTC 24 Sep 09 08:04:27 AM UTC 24 2130320617 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1639734063 Sep 09 08:04:20 AM UTC 24 Sep 09 08:04:31 AM UTC 24 677569534 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3347682005 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:33 AM UTC 24 13912268389 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1587564728 Sep 09 08:03:57 AM UTC 24 Sep 09 08:04:38 AM UTC 24 736818417 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1160193093 Sep 09 08:04:18 AM UTC 24 Sep 09 08:04:39 AM UTC 24 4485287898 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1561653755 Sep 09 08:04:22 AM UTC 24 Sep 09 08:04:39 AM UTC 24 4896563317 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2360895490 Sep 09 08:04:04 AM UTC 24 Sep 09 08:04:40 AM UTC 24 1898331432 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2095776742 Sep 09 08:03:47 AM UTC 24 Sep 09 08:04:41 AM UTC 24 2715769056 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2283954331 Sep 09 08:03:49 AM UTC 24 Sep 09 08:04:46 AM UTC 24 1335152009 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.493043182 Sep 09 08:04:40 AM UTC 24 Sep 09 08:04:46 AM UTC 24 1399164132 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1739859713 Sep 09 08:03:57 AM UTC 24 Sep 09 08:04:47 AM UTC 24 760327565 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2970881932 Sep 09 08:04:47 AM UTC 24 Sep 09 08:04:49 AM UTC 24 14610061 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1747698358 Sep 09 08:04:47 AM UTC 24 Sep 09 08:04:52 AM UTC 24 369304889 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1418619687 Sep 09 08:03:58 AM UTC 24 Sep 09 08:04:55 AM UTC 24 93466507434 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4270326613 Sep 09 08:04:41 AM UTC 24 Sep 09 08:04:59 AM UTC 24 393004042 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3019136157 Sep 09 08:04:28 AM UTC 24 Sep 09 08:05:04 AM UTC 24 12471860921 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3078074156 Sep 09 08:03:51 AM UTC 24 Sep 09 08:05:10 AM UTC 24 3433357760 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4275591732 Sep 09 08:03:51 AM UTC 24 Sep 09 08:05:10 AM UTC 24 34849462587 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.28286458 Sep 09 08:04:48 AM UTC 24 Sep 09 08:05:11 AM UTC 24 850207824 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1291961487 Sep 09 08:04:56 AM UTC 24 Sep 09 08:05:14 AM UTC 24 1067843074 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.250755236 Sep 09 08:03:56 AM UTC 24 Sep 09 08:05:17 AM UTC 24 4027052325 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3507314864 Sep 09 08:03:47 AM UTC 24 Sep 09 08:05:19 AM UTC 24 48129296682 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.166357571 Sep 09 08:05:06 AM UTC 24 Sep 09 08:05:21 AM UTC 24 4858756848 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2334085440 Sep 09 08:05:05 AM UTC 24 Sep 09 08:05:21 AM UTC 24 2838708947 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1984847046 Sep 09 08:03:49 AM UTC 24 Sep 09 08:05:22 AM UTC 24 11139537997 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.729601205 Sep 09 08:05:18 AM UTC 24 Sep 09 08:05:24 AM UTC 24 680066266 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1769877684 Sep 09 08:05:25 AM UTC 24 Sep 09 08:05:27 AM UTC 24 44954369 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1657126137 Sep 09 08:05:22 AM UTC 24 Sep 09 08:05:41 AM UTC 24 376854608 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1929488193 Sep 09 08:05:29 AM UTC 24 Sep 09 08:05:46 AM UTC 24 2280098127 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.19731096 Sep 09 08:05:10 AM UTC 24 Sep 09 08:06:02 AM UTC 24 9707079025 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3135237491 Sep 09 08:06:03 AM UTC 24 Sep 09 08:06:22 AM UTC 24 861708607 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3471559393 Sep 09 08:03:44 AM UTC 24 Sep 09 08:06:25 AM UTC 24 8435276562 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.625558885 Sep 09 08:06:26 AM UTC 24 Sep 09 08:06:36 AM UTC 24 1388133209 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3908435718 Sep 09 08:03:43 AM UTC 24 Sep 09 08:06:42 AM UTC 24 13276649799 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.843331399 Sep 09 08:03:48 AM UTC 24 Sep 09 08:06:59 AM UTC 24 24065023351 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3626089826 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:07 AM UTC 24 24344423233 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3335543092 Sep 09 08:03:42 AM UTC 24 Sep 09 08:07:17 AM UTC 24 1199498890 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3105012642 Sep 09 08:06:36 AM UTC 24 Sep 09 08:07:19 AM UTC 24 3047833965 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1055065689 Sep 09 08:07:20 AM UTC 24 Sep 09 08:07:26 AM UTC 24 1399287552 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.259432941 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:27 AM UTC 24 19134591040 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.43711425 Sep 09 08:03:56 AM UTC 24 Sep 09 08:07:30 AM UTC 24 6573933688 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2450750050 Sep 09 08:05:22 AM UTC 24 Sep 09 08:07:36 AM UTC 24 3291571945 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1666350431 Sep 09 08:04:04 AM UTC 24 Sep 09 08:07:42 AM UTC 24 5018562823 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3058816451 Sep 09 08:07:43 AM UTC 24 Sep 09 08:07:45 AM UTC 24 23203143 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1230942985 Sep 09 08:04:41 AM UTC 24 Sep 09 08:07:46 AM UTC 24 18263191541 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2654665920 Sep 09 08:03:51 AM UTC 24 Sep 09 08:07:59 AM UTC 24 36396042668 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1097636433 Sep 09 08:07:31 AM UTC 24 Sep 09 08:08:02 AM UTC 24 2990351343 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.48786001 Sep 09 08:07:46 AM UTC 24 Sep 09 08:08:07 AM UTC 24 528737498 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2202582467 Sep 09 08:06:42 AM UTC 24 Sep 09 08:08:16 AM UTC 24 13662741248 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2787071700 Sep 09 08:04:32 AM UTC 24 Sep 09 08:08:20 AM UTC 24 8828543570 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3856756271 Sep 09 08:03:56 AM UTC 24 Sep 09 08:08:25 AM UTC 24 5845036483 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1026676301 Sep 09 08:10:06 AM UTC 24 Sep 09 08:10:36 AM UTC 24 8200634036 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1786054221 Sep 09 08:04:01 AM UTC 24 Sep 09 08:08:31 AM UTC 24 3945714695 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1308526782 Sep 09 08:05:20 AM UTC 24 Sep 09 08:08:32 AM UTC 24 115427411566 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1611453286 Sep 09 08:08:09 AM UTC 24 Sep 09 08:08:32 AM UTC 24 595967897 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3770843462 Sep 09 08:04:15 AM UTC 24 Sep 09 08:08:36 AM UTC 24 6376715405 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.208185615 Sep 09 08:08:26 AM UTC 24 Sep 09 08:08:37 AM UTC 24 670271206 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3885509926 Sep 09 08:08:38 AM UTC 24 Sep 09 08:08:47 AM UTC 24 3047523011 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.636564896 Sep 09 08:03:49 AM UTC 24 Sep 09 08:08:49 AM UTC 24 10870121085 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.110634896 Sep 09 08:03:48 AM UTC 24 Sep 09 08:09:01 AM UTC 24 1934822523 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.621301168 Sep 09 08:08:32 AM UTC 24 Sep 09 08:10:01 AM UTC 24 9310821124 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.306013334 Sep 09 08:02:57 AM UTC 24 Sep 09 08:10:04 AM UTC 24 20028093445 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3370100282 Sep 09 08:08:49 AM UTC 24 Sep 09 08:10:05 AM UTC 24 11853402242 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.465037694 Sep 09 08:10:05 AM UTC 24 Sep 09 08:10:07 AM UTC 24 49060908 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2836076021 Sep 09 08:08:33 AM UTC 24 Sep 09 08:10:12 AM UTC 24 11429429748 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2571984786 Sep 09 08:08:22 AM UTC 24 Sep 09 08:10:12 AM UTC 24 12662093449 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1048341854 Sep 09 08:04:53 AM UTC 24 Sep 09 08:10:18 AM UTC 24 54220401385 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4136666043 Sep 09 08:03:47 AM UTC 24 Sep 09 08:10:27 AM UTC 24 26112462122 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.20154864 Sep 09 08:10:18 AM UTC 24 Sep 09 08:10:31 AM UTC 24 769444534 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2182251324 Sep 09 08:05:12 AM UTC 24 Sep 09 08:10:31 AM UTC 24 20750812877 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2855524537 Sep 09 08:09:01 AM UTC 24 Sep 09 08:10:43 AM UTC 24 5039039209 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2092026275 Sep 09 08:04:17 AM UTC 24 Sep 09 08:10:45 AM UTC 24 24241619105 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3826448577 Sep 09 08:07:28 AM UTC 24 Sep 09 08:10:46 AM UTC 24 4385589627 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2827324604 Sep 09 08:03:58 AM UTC 24 Sep 09 08:10:47 AM UTC 24 25990709668 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3854333106 Sep 09 08:04:39 AM UTC 24 Sep 09 08:10:49 AM UTC 24 7722445337 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3973091417 Sep 09 08:10:48 AM UTC 24 Sep 09 08:10:55 AM UTC 24 2092246514 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1386717389 Sep 09 08:04:00 AM UTC 24 Sep 09 08:10:59 AM UTC 24 4806441404 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.305421519 Sep 09 08:05:47 AM UTC 24 Sep 09 08:10:59 AM UTC 24 41300389994 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4256720594 Sep 09 08:10:31 AM UTC 24 Sep 09 08:11:01 AM UTC 24 718677919 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4094749027 Sep 09 08:03:46 AM UTC 24 Sep 09 08:11:04 AM UTC 24 5785142986 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.792184380 Sep 09 08:11:02 AM UTC 24 Sep 09 08:11:04 AM UTC 24 40312512 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1033225595 Sep 09 08:03:48 AM UTC 24 Sep 09 08:11:19 AM UTC 24 86150882576 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1948296575 Sep 09 08:11:05 AM UTC 24 Sep 09 08:11:20 AM UTC 24 8552650221 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3153919316 Sep 09 08:11:00 AM UTC 24 Sep 09 08:11:21 AM UTC 24 624533217 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.414517861 Sep 09 08:04:40 AM UTC 24 Sep 09 08:11:22 AM UTC 24 22017222502 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.193633049 Sep 09 08:07:28 AM UTC 24 Sep 09 08:11:29 AM UTC 24 39415883044 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3825688448 Sep 09 08:05:42 AM UTC 24 Sep 09 08:11:33 AM UTC 24 19863417862 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1855889985 Sep 09 08:10:33 AM UTC 24 Sep 09 08:11:34 AM UTC 24 1092560858 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3049079768 Sep 09 08:05:00 AM UTC 24 Sep 09 08:11:34 AM UTC 24 19353397870 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.987878021 Sep 09 08:11:04 AM UTC 24 Sep 09 08:11:34 AM UTC 24 750537393 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.876575732 Sep 09 08:11:22 AM UTC 24 Sep 09 08:11:35 AM UTC 24 1418354102 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2097558287 Sep 09 08:11:34 AM UTC 24 Sep 09 08:11:52 AM UTC 24 2769669702 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1442836208 Sep 09 08:10:37 AM UTC 24 Sep 09 08:11:55 AM UTC 24 9831799617 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3112610800 Sep 09 08:11:52 AM UTC 24 Sep 09 08:11:59 AM UTC 24 352228012 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2707733415 Sep 09 08:04:18 AM UTC 24 Sep 09 08:12:05 AM UTC 24 72724170325 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1921548294 Sep 09 08:10:55 AM UTC 24 Sep 09 08:12:16 AM UTC 24 4163056586 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2745452535 Sep 09 08:08:17 AM UTC 24 Sep 09 08:12:20 AM UTC 24 87092410947 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.364709168 Sep 09 08:12:21 AM UTC 24 Sep 09 08:12:23 AM UTC 24 14428589 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3606557733 Sep 09 08:12:06 AM UTC 24 Sep 09 08:12:24 AM UTC 24 420317777 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.323181055 Sep 09 08:05:23 AM UTC 24 Sep 09 08:12:26 AM UTC 24 79390436687 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3344526823 Sep 09 08:03:00 AM UTC 24 Sep 09 08:12:32 AM UTC 24 24813990156 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3190544597 Sep 09 08:12:24 AM UTC 24 Sep 09 08:12:33 AM UTC 24 1481199404 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.174936637 Sep 09 08:11:30 AM UTC 24 Sep 09 08:12:34 AM UTC 24 4253704346 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3871004697 Sep 09 08:11:34 AM UTC 24 Sep 09 08:12:46 AM UTC 24 15092179429 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1162756851 Sep 09 08:12:33 AM UTC 24 Sep 09 08:13:01 AM UTC 24 2149973545 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.514248988 Sep 09 08:10:47 AM UTC 24 Sep 09 08:13:06 AM UTC 24 5561034522 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3758140137 Sep 09 08:03:47 AM UTC 24 Sep 09 08:13:07 AM UTC 24 10846547294 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1769118820 Sep 09 08:03:45 AM UTC 24 Sep 09 08:13:18 AM UTC 24 10276310240 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1193304196 Sep 09 08:03:16 AM UTC 24 Sep 09 08:13:21 AM UTC 24 13193284715 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2793162932 Sep 09 08:04:33 AM UTC 24 Sep 09 08:13:31 AM UTC 24 26222124542 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1159426286 Sep 09 08:13:32 AM UTC 24 Sep 09 08:13:39 AM UTC 24 697122836 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3065377947 Sep 09 08:13:01 AM UTC 24 Sep 09 08:13:41 AM UTC 24 1463463833 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3584488949 Sep 09 08:10:50 AM UTC 24 Sep 09 08:13:44 AM UTC 24 49898798415 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3071396588 Sep 09 08:08:02 AM UTC 24 Sep 09 08:13:45 AM UTC 24 4557516710 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2751229789 Sep 09 08:12:47 AM UTC 24 Sep 09 08:13:53 AM UTC 24 828135283 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1732622809 Sep 09 08:13:53 AM UTC 24 Sep 09 08:13:55 AM UTC 24 29788752 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1150746653 Sep 09 08:13:45 AM UTC 24 Sep 09 08:14:01 AM UTC 24 610376113 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3180145993 Sep 09 08:02:45 AM UTC 24 Sep 09 08:14:13 AM UTC 24 22092896706 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.97996287 Sep 09 08:07:08 AM UTC 24 Sep 09 08:14:50 AM UTC 24 36486201286 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1405778992 Sep 09 08:06:23 AM UTC 24 Sep 09 08:14:50 AM UTC 24 36497418670 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2594746971 Sep 09 08:13:07 AM UTC 24 Sep 09 08:14:59 AM UTC 24 84137240044 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2481448933 Sep 09 08:05:15 AM UTC 24 Sep 09 08:15:03 AM UTC 24 3141385950 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1555866013 Sep 09 08:11:55 AM UTC 24 Sep 09 08:15:14 AM UTC 24 57415247315 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2959549791 Sep 09 08:12:00 AM UTC 24 Sep 09 08:15:16 AM UTC 24 4993181448 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2699909711 Sep 09 08:14:51 AM UTC 24 Sep 09 08:15:19 AM UTC 24 15897418772 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.3792960676 Sep 09 08:13:56 AM UTC 24 Sep 09 08:15:23 AM UTC 24 444245124 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.4153424089 Sep 09 08:15:03 AM UTC 24 Sep 09 08:15:26 AM UTC 24 743146291 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1652196189 Sep 09 08:15:14 AM UTC 24 Sep 09 08:15:27 AM UTC 24 2667761340 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3986742944 Sep 09 08:15:28 AM UTC 24 Sep 09 08:15:33 AM UTC 24 3372059085 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2458606356 Sep 09 08:08:47 AM UTC 24 Sep 09 08:15:59 AM UTC 24 86229824383 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2707502035 Sep 09 08:02:43 AM UTC 24 Sep 09 08:16:00 AM UTC 24 59638820500 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2988901475 Sep 09 08:10:13 AM UTC 24 Sep 09 08:16:01 AM UTC 24 23239794022 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4056664939 Sep 09 08:16:01 AM UTC 24 Sep 09 08:16:19 AM UTC 24 402595977 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1067317893 Sep 09 08:16:20 AM UTC 24 Sep 09 08:16:23 AM UTC 24 19511519 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2699922161 Sep 09 08:16:24 AM UTC 24 Sep 09 08:16:36 AM UTC 24 930972903 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3504498624 Sep 09 08:10:44 AM UTC 24 Sep 09 08:16:37 AM UTC 24 8285268805 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.83593616 Sep 09 08:13:41 AM UTC 24 Sep 09 08:16:41 AM UTC 24 5799135574 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.779268850 Sep 09 08:14:51 AM UTC 24 Sep 09 08:16:49 AM UTC 24 2258414150 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2067822116 Sep 09 08:05:11 AM UTC 24 Sep 09 08:16:54 AM UTC 24 9849408157 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4280926761 Sep 09 08:11:21 AM UTC 24 Sep 09 08:17:06 AM UTC 24 10504538371 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3267960598 Sep 09 08:16:00 AM UTC 24 Sep 09 08:17:17 AM UTC 24 2895174498 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3465473786 Sep 09 08:13:39 AM UTC 24 Sep 09 08:17:20 AM UTC 24 27724227252 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1839283014 Sep 09 08:03:51 AM UTC 24 Sep 09 08:17:21 AM UTC 24 65959401149 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2386539427 Sep 09 08:03:54 AM UTC 24 Sep 09 08:17:23 AM UTC 24 12401035483 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.463194262 Sep 09 08:15:17 AM UTC 24 Sep 09 08:17:31 AM UTC 24 14297394106 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.2208569828 Sep 09 08:12:33 AM UTC 24 Sep 09 08:17:33 AM UTC 24 5035867553 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.482197179 Sep 09 08:17:35 AM UTC 24 Sep 09 08:17:40 AM UTC 24 5599749646 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.793127706 Sep 09 08:16:50 AM UTC 24 Sep 09 08:17:41 AM UTC 24 4280268829 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1373059552 Sep 09 08:11:36 AM UTC 24 Sep 09 08:17:42 AM UTC 24 14678903516 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.436386961 Sep 09 08:04:00 AM UTC 24 Sep 09 08:17:55 AM UTC 24 10978890577 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1566547411 Sep 09 08:17:56 AM UTC 24 Sep 09 08:17:58 AM UTC 24 24046825 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2268246566 Sep 09 08:10:28 AM UTC 24 Sep 09 08:18:01 AM UTC 24 7068824524 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3466821170 Sep 09 08:17:18 AM UTC 24 Sep 09 08:18:13 AM UTC 24 764157294 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2589247472 Sep 09 08:13:20 AM UTC 24 Sep 09 08:18:22 AM UTC 24 4476379687 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.775160611 Sep 09 08:17:21 AM UTC 24 Sep 09 08:18:31 AM UTC 24 9943124545 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1784737969 Sep 09 08:04:50 AM UTC 24 Sep 09 08:18:38 AM UTC 24 50257418536 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2133902633 Sep 09 08:12:34 AM UTC 24 Sep 09 08:18:50 AM UTC 24 29105077414 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3602964608 Sep 09 08:17:59 AM UTC 24 Sep 09 08:18:50 AM UTC 24 750940174 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3733023290 Sep 09 08:17:07 AM UTC 24 Sep 09 08:18:52 AM UTC 24 2667502702 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1285553090 Sep 09 08:11:23 AM UTC 24 Sep 09 08:19:09 AM UTC 24 14458130971 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3675364201 Sep 09 08:15:33 AM UTC 24 Sep 09 08:19:18 AM UTC 24 6929459538 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2303266365 Sep 09 08:17:42 AM UTC 24 Sep 09 08:19:18 AM UTC 24 12270592548 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2278368496 Sep 09 08:03:32 AM UTC 24 Sep 09 08:19:21 AM UTC 24 11288475350 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1381719672 Sep 09 08:18:51 AM UTC 24 Sep 09 08:19:24 AM UTC 24 769062033 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1468116826 Sep 09 08:18:51 AM UTC 24 Sep 09 08:19:26 AM UTC 24 731920341 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3493414352 Sep 09 08:19:22 AM UTC 24 Sep 09 08:19:28 AM UTC 24 1470211917 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2163423527 Sep 09 08:18:33 AM UTC 24 Sep 09 08:19:52 AM UTC 24 6465950854 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.932196942 Sep 09 08:19:29 AM UTC 24 Sep 09 08:20:01 AM UTC 24 2295442147 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1548971805 Sep 09 08:20:02 AM UTC 24 Sep 09 08:20:04 AM UTC 24 20610029 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2105075487 Sep 09 08:17:43 AM UTC 24 Sep 09 08:20:07 AM UTC 24 4324884899 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1663137938 Sep 09 08:16:42 AM UTC 24 Sep 09 08:20:12 AM UTC 24 12175669699 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.374263767 Sep 09 08:20:05 AM UTC 24 Sep 09 08:20:38 AM UTC 24 6326833872 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.592085933 Sep 09 08:15:27 AM UTC 24 Sep 09 08:20:42 AM UTC 24 1925980466 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3177440272 Sep 09 08:13:08 AM UTC 24 Sep 09 08:20:46 AM UTC 24 10809805827 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.336370058 Sep 09 08:06:59 AM UTC 24 Sep 09 08:20:46 AM UTC 24 27267809963 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4054331882 Sep 09 08:11:35 AM UTC 24 Sep 09 08:20:50 AM UTC 24 10333149404 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.453284975 Sep 09 08:20:47 AM UTC 24 Sep 09 08:20:57 AM UTC 24 3338156359 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2054580750 Sep 09 08:20:47 AM UTC 24 Sep 09 08:21:00 AM UTC 24 2813178465 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3779059369 Sep 09 08:15:00 AM UTC 24 Sep 09 08:21:01 AM UTC 24 26583581648 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2255419620 Sep 09 08:19:27 AM UTC 24 Sep 09 08:21:07 AM UTC 24 5485742115 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1094856094 Sep 09 08:03:51 AM UTC 24 Sep 09 08:21:07 AM UTC 24 99619431533 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1106211710 Sep 09 08:16:55 AM UTC 24 Sep 09 08:21:11 AM UTC 24 5275756217 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2682597683 Sep 09 08:15:20 AM UTC 24 Sep 09 08:21:14 AM UTC 24 8647997363 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.428255524 Sep 09 08:18:53 AM UTC 24 Sep 09 08:21:14 AM UTC 24 46568759558 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2325654633 Sep 09 08:21:07 AM UTC 24 Sep 09 08:21:14 AM UTC 24 353942027 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2175482575 Sep 09 08:21:15 AM UTC 24 Sep 09 08:21:17 AM UTC 24 32635961 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1409148013 Sep 09 08:20:39 AM UTC 24 Sep 09 08:21:23 AM UTC 24 1054335148 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1036442335 Sep 09 08:10:08 AM UTC 24 Sep 09 08:21:24 AM UTC 24 22847082621 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2797206904 Sep 09 08:21:18 AM UTC 24 Sep 09 08:21:29 AM UTC 24 413258483 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3481780082 Sep 09 08:15:24 AM UTC 24 Sep 09 08:21:42 AM UTC 24 5360648361 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3902436750 Sep 09 08:03:51 AM UTC 24 Sep 09 08:22:02 AM UTC 24 69841389664 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.791701498 Sep 09 08:21:15 AM UTC 24 Sep 09 08:22:04 AM UTC 24 1002520256 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3868478981 Sep 09 08:20:51 AM UTC 24 Sep 09 08:22:13 AM UTC 24 26933891544 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3381608035 Sep 09 08:07:18 AM UTC 24 Sep 09 08:22:13 AM UTC 24 13467962763 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1675432691 Sep 09 08:11:35 AM UTC 24 Sep 09 08:22:18 AM UTC 24 25649296331 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.361201658 Sep 09 08:21:43 AM UTC 24 Sep 09 08:22:23 AM UTC 24 1937907815 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2138982123 Sep 09 08:22:14 AM UTC 24 Sep 09 08:22:35 AM UTC 24 5795409642 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2319289488 Sep 09 08:04:51 AM UTC 24 Sep 09 08:22:40 AM UTC 24 43854340322 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.238110757 Sep 09 08:08:36 AM UTC 24 Sep 09 08:22:42 AM UTC 24 30997839112 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2444204723 Sep 09 08:08:00 AM UTC 24 Sep 09 08:22:43 AM UTC 24 129894153171 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.600466378 Sep 09 08:22:40 AM UTC 24 Sep 09 08:22:48 AM UTC 24 5578366653 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2674670455 Sep 09 08:17:41 AM UTC 24 Sep 09 08:22:52 AM UTC 24 21003079044 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.997358908 Sep 09 08:05:42 AM UTC 24 Sep 09 08:22:52 AM UTC 24 17498207888 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1812444271 Sep 09 08:22:53 AM UTC 24 Sep 09 08:22:55 AM UTC 24 15437628 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2221023664 Sep 09 08:07:47 AM UTC 24 Sep 09 08:23:04 AM UTC 24 44917625635 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3455854331 Sep 09 08:22:05 AM UTC 24 Sep 09 08:23:28 AM UTC 24 1638301531 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1142826303 Sep 09 08:17:21 AM UTC 24 Sep 09 08:23:46 AM UTC 24 7466303065 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2280842956 Sep 09 08:18:22 AM UTC 24 Sep 09 08:23:50 AM UTC 24 4347181990 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2255725563 Sep 09 08:21:07 AM UTC 24 Sep 09 08:23:59 AM UTC 24 8221412721 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3178913853 Sep 09 08:21:12 AM UTC 24 Sep 09 08:24:00 AM UTC 24 5105375309 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.251621600 Sep 09 08:22:49 AM UTC 24 Sep 09 08:24:07 AM UTC 24 3933759596 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2390432760 Sep 09 08:10:13 AM UTC 24 Sep 09 08:24:08 AM UTC 24 50564895013 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2062379302 Sep 09 08:18:40 AM UTC 24 Sep 09 08:24:11 AM UTC 24 44159251560 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2127068643 Sep 09 08:22:56 AM UTC 24 Sep 09 08:24:12 AM UTC 24 937904653 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2609355914 Sep 09 08:23:51 AM UTC 24 Sep 09 08:24:13 AM UTC 24 813583484 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1691496631 Sep 09 08:10:46 AM UTC 24 Sep 09 08:24:17 AM UTC 24 17350572117 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.75953749 Sep 09 08:19:25 AM UTC 24 Sep 09 08:24:18 AM UTC 24 21877737839 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1058411391 Sep 09 08:24:05 AM UTC 24 Sep 09 08:24:19 AM UTC 24 721254916 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.102934987 Sep 09 08:24:13 AM UTC 24 Sep 09 08:24:19 AM UTC 24 394249608 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1692350893 Sep 09 08:22:19 AM UTC 24 Sep 09 08:24:37 AM UTC 24 8780238039 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2975614805 Sep 09 08:24:38 AM UTC 24 Sep 09 08:24:40 AM UTC 24 33318344 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3752803913 Sep 09 08:24:01 AM UTC 24 Sep 09 08:24:42 AM UTC 24 754914071 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1505040727 Sep 09 08:22:14 AM UTC 24 Sep 09 08:24:48 AM UTC 24 60361025437 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2874736750 Sep 09 08:24:20 AM UTC 24 Sep 09 08:24:56 AM UTC 24 4060967277 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4189920954 Sep 09 08:24:41 AM UTC 24 Sep 09 08:25:08 AM UTC 24 3548820025 ps