Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	322491278	1			T1	348		T2	522		T3	208
instr_valid_dis	283375565	1			T1	348		T2	522		T3	208
instr_en	26500663	1			T26	63264		T18	46038		T40	74078

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13936700	1			T17	83186		T26	45050		T18	18328
sram_ifetch_valid_disable	276818570	1			T1	348		T2	522		T3	208
sram_ifetch_enable	31736008	1			T17	141324		T26	48228		T18	27188

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	322491278	1			T1	348		T2	522		T3	208
hw_debug_en_valid_off	277113770	1			T1	348		T2	522		T3	208
hw_debug_en_on	35007074	1			T10	9486		T17	179836		T26	48314

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	276818570	1			T1	348		T2	522		T3	208
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	264056785	1			T1	348		T2	522		T3	208
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9103147	1			T26	52074		T18	26460		T40	74078
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5226158	1			T17	96		T26	7926		T41	8170
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1737940	1			T17	96		T26	7926		T128	56456
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2755264	1			T19	6284		T132	12010		T139	32738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6932634	1			T17	13082		T26	37124		T18	18328
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2455334	1			T17	13082		T26	5734		T60	7612
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3928502	1			T18	6892		T41	38474		T133	34698
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9015046	1			T10	9486		T17	67870		T40	24634
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3691820	1			T10	9486		T17	67870		T128	7384
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4077478	1			T40	24634		T140	74018		T133	10748

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10227996	1			T26	11190		T18	12686		T140	36344
lc_exec_en	19059394	1			T17	98884		T26	11190		T40	36740
valid_exec_dis	276780548	1			T1	348		T2	522		T3	208
invalid_exec_dis	45672708	1			T17	224510		T26	93278		T18	45516