Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1035
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.55 84.55 96.16 96.16 80.92 80.92 92.91 92.91 66.67 66.67 87.20 87.20 95.03 95.03 72.94 72.94 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.791378981
89.20 4.66 97.38 1.23 85.66 4.74 94.70 1.79 80.95 14.29 91.47 4.27 96.20 1.17 78.06 5.12 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2360305389
92.44 3.24 98.36 0.98 85.66 0.00 94.90 0.21 100.00 19.05 92.89 1.42 97.22 1.02 78.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.297993681
93.71 1.27 98.53 0.16 87.44 1.78 95.59 0.69 100.00 0.00 93.84 0.95 97.22 0.00 83.36 5.30 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1199965851
94.83 1.12 98.86 0.33 89.45 2.01 98.14 2.55 100.00 0.00 95.26 1.42 97.81 0.58 84.28 0.91 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1839981248
95.72 0.89 98.86 0.00 90.05 0.59 98.14 0.00 100.00 0.00 95.26 0.00 97.81 0.00 89.95 5.67 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.112371463
96.26 0.54 99.10 0.25 90.05 0.00 98.14 0.00 100.00 0.00 95.50 0.24 97.81 0.00 93.24 3.29 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.957809481
96.60 0.34 99.10 0.00 90.40 0.36 98.28 0.14 100.00 0.00 95.73 0.24 97.81 0.00 94.88 1.65 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2581430715
96.77 0.17 99.10 0.00 90.40 0.00 98.28 0.00 100.00 0.00 95.73 0.00 98.98 1.17 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2973924265
96.90 0.13 99.18 0.08 90.40 0.00 99.10 0.83 100.00 0.00 95.73 0.00 98.98 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1753479983
97.01 0.11 99.18 0.00 90.40 0.00 99.17 0.07 100.00 0.00 95.73 0.00 98.98 0.00 95.61 0.73 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1374922401
97.10 0.09 99.18 0.00 90.76 0.36 99.24 0.07 100.00 0.00 95.73 0.00 98.98 0.00 95.80 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2978247097
97.18 0.08 99.18 0.00 90.88 0.12 99.24 0.00 100.00 0.00 96.21 0.47 98.98 0.00 95.80 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3973108162
97.27 0.08 99.18 0.00 91.00 0.12 99.52 0.28 100.00 0.00 96.21 0.00 98.98 0.00 95.98 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.723687760
97.34 0.08 99.18 0.00 91.00 0.00 99.52 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.53 0.55 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4199874182
97.40 0.05 99.18 0.00 91.00 0.00 99.52 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1333065613
97.43 0.04 99.18 0.00 91.00 0.00 99.59 0.07 100.00 0.00 96.21 0.00 98.98 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1434897217
97.47 0.04 99.18 0.00 91.00 0.00 99.66 0.07 100.00 0.00 96.21 0.00 98.98 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3818101255
97.49 0.03 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3916989338
97.52 0.02 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1187072776
97.52 0.01 99.18 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.45318184

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3546245974
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1104220166
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3552621533
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3427067534
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.734568005
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1969639589
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3638669625
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1029088014
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3759217582
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1393708469
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3176968667
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3023878578
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2300509128
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1530785504
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3915749885
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2050788436
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.285517116
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3357445971
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2641249500
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2311694634
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.659029954
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.302206668
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3203870861
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2962379986
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.549957685
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3444852125
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.276204437
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2460054002
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1184221928
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2479180615
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2018577829
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3614043336
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1732628350
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2757149525
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1528458117
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2461041962
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3435308755
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1142939361
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.363811042
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2121058441
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4132506112
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1401458852
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2940319127
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3643279753
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1869520251
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1374997214
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.360370986
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2825970161
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.500437563
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4135415593
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2245682273
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1481567773
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1161620275
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.984542741
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4139106818
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1495854042
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3343573476
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2865333239
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1522697969
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2633284277
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1914247123
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3324520759
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3909939375
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.29979122
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.551304246
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3506177177
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.523206001
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.911039677
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.852711818
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1799790225
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4292583016
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3860324316
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3800868055
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.140683243
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2602531375
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3023562546
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1040007516
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.284016730
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3251315692
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4031269484
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3121604860
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.875485950
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.64416983
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2147154900
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2118125357
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3525793643
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3545281843
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2203413361
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2413563238
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/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3905764963
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.11579377
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.4159350167
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1264809071
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/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3256291544
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3577587186
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.199514567
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1094207564
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.817837357
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4215394144
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1532261752
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2902497582
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.730515288
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4143720471
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1246194896
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.846530367
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2887957742
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1720129462
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.581406245
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3504972377
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1793841029
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3247954211
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2994145640
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.681507065
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1949075734
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2378703656
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3520837720
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1466414304
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1482041191
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4273016969
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2735896793
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2871009336
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3540288248
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3982217644
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2233875325
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3472613709
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1904178976
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3554189874
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1230444116
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1697570324
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3064641100
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3858874001
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1208046529
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2162159018
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.484666664
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2326869502
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1656147824
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2635745055
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.721579056
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.785380394
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1255218591
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1599584949
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.501246636
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1934035037
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3104113116
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3779228472
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.4007210231
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1504731927
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2534667693
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2048413304
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3594517319
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2902075236
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4117198820
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2734470361



Total test records in report: 1035
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3796312403 Sep 11 06:11:02 AM UTC 24 Sep 11 06:11:09 AM UTC 24 3833243544 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3011209103 Sep 11 06:11:04 AM UTC 24 Sep 11 06:11:13 AM UTC 24 3341702666 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3387791821 Sep 11 06:11:05 AM UTC 24 Sep 11 06:11:14 AM UTC 24 709721782 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.555706496 Sep 11 06:11:04 AM UTC 24 Sep 11 06:11:21 AM UTC 24 1755314669 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1753479983 Sep 11 06:11:22 AM UTC 24 Sep 11 06:11:27 AM UTC 24 745164237 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2360305389 Sep 11 06:11:05 AM UTC 24 Sep 11 06:12:06 AM UTC 24 23171379339 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.791378981 Sep 11 06:12:38 AM UTC 24 Sep 11 06:13:34 AM UTC 24 7496686547 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3402666904 Sep 11 06:14:30 AM UTC 24 Sep 11 06:14:35 AM UTC 24 1400437049 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2616568806 Sep 11 06:14:36 AM UTC 24 Sep 11 06:14:38 AM UTC 24 14210793 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1472996920 Sep 11 06:14:39 AM UTC 24 Sep 11 06:15:06 AM UTC 24 3363430494 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2064662972 Sep 11 06:11:02 AM UTC 24 Sep 11 06:15:17 AM UTC 24 5579206077 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.297993681 Sep 11 06:12:07 AM UTC 24 Sep 11 06:15:17 AM UTC 24 11032242880 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3504481832 Sep 11 06:15:18 AM UTC 24 Sep 11 06:15:26 AM UTC 24 430463372 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.403800930 Sep 11 06:11:09 AM UTC 24 Sep 11 06:15:51 AM UTC 24 7902343612 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4028737552 Sep 11 06:15:52 AM UTC 24 Sep 11 06:16:51 AM UTC 24 6245013143 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1362291955 Sep 11 06:11:29 AM UTC 24 Sep 11 06:16:55 AM UTC 24 5841583844 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2694535637 Sep 11 06:16:52 AM UTC 24 Sep 11 06:17:08 AM UTC 24 3303286523 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3899285841 Sep 11 06:16:56 AM UTC 24 Sep 11 06:17:23 AM UTC 24 2958949674 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1199965851 Sep 11 06:11:16 AM UTC 24 Sep 11 06:17:41 AM UTC 24 16179842192 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.957809481 Sep 11 06:11:04 AM UTC 24 Sep 11 06:19:22 AM UTC 24 40328597316 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3527001463 Sep 11 06:19:23 AM UTC 24 Sep 11 06:19:29 AM UTC 24 348609378 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1839981248 Sep 11 06:20:03 AM UTC 24 Sep 11 06:20:06 AM UTC 24 113188676 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2978247097 Sep 11 06:20:05 AM UTC 24 Sep 11 06:20:07 AM UTC 24 23783483 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2493341341 Sep 11 06:19:59 AM UTC 24 Sep 11 06:20:08 AM UTC 24 405194044 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3915125732 Sep 11 06:15:07 AM UTC 24 Sep 11 06:20:22 AM UTC 24 17047479854 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1085988400 Sep 11 06:20:16 AM UTC 24 Sep 11 06:20:22 AM UTC 24 362177855 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2477243706 Sep 11 06:20:21 AM UTC 24 Sep 11 06:20:23 AM UTC 24 12499977 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3134006906 Sep 11 06:20:20 AM UTC 24 Sep 11 06:20:24 AM UTC 24 572124128 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.3268562826 Sep 11 06:20:05 AM UTC 24 Sep 11 06:20:30 AM UTC 24 3421863884 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3220309946 Sep 11 06:20:31 AM UTC 24 Sep 11 06:20:33 AM UTC 24 23088715 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2498864019 Sep 11 06:20:24 AM UTC 24 Sep 11 06:20:34 AM UTC 24 2790899384 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.731261067 Sep 11 06:20:27 AM UTC 24 Sep 11 06:20:34 AM UTC 24 1411432999 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3503125777 Sep 11 06:20:31 AM UTC 24 Sep 11 06:20:35 AM UTC 24 425366215 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.209058308 Sep 11 06:15:17 AM UTC 24 Sep 11 06:20:36 AM UTC 24 4011214794 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.331449734 Sep 11 06:20:29 AM UTC 24 Sep 11 06:20:42 AM UTC 24 314527693 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.130883632 Sep 11 06:20:07 AM UTC 24 Sep 11 06:20:44 AM UTC 24 796673077 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2306088112 Sep 11 06:20:34 AM UTC 24 Sep 11 06:20:47 AM UTC 24 2163707579 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.4294639962 Sep 11 06:20:42 AM UTC 24 Sep 11 06:20:49 AM UTC 24 1211090878 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2765871429 Sep 11 06:20:21 AM UTC 24 Sep 11 06:20:50 AM UTC 24 3550871376 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3383096472 Sep 11 06:20:49 AM UTC 24 Sep 11 06:20:51 AM UTC 24 27394991 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1386539746 Sep 11 06:20:32 AM UTC 24 Sep 11 06:20:52 AM UTC 24 852265210 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1781158608 Sep 11 06:20:48 AM UTC 24 Sep 11 06:20:54 AM UTC 24 437365145 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1838376035 Sep 11 06:20:37 AM UTC 24 Sep 11 06:21:01 AM UTC 24 2830722056 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3526766652 Sep 11 06:20:35 AM UTC 24 Sep 11 06:21:03 AM UTC 24 1404059026 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.460191076 Sep 11 06:20:50 AM UTC 24 Sep 11 06:21:04 AM UTC 24 770084608 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2487617498 Sep 11 06:20:23 AM UTC 24 Sep 11 06:21:11 AM UTC 24 2817974622 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2154185548 Sep 11 06:20:54 AM UTC 24 Sep 11 06:21:14 AM UTC 24 585789168 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3030823839 Sep 11 06:20:23 AM UTC 24 Sep 11 06:21:18 AM UTC 24 809838040 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2366663144 Sep 11 06:21:19 AM UTC 24 Sep 11 06:21:24 AM UTC 24 359019257 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3403515087 Sep 11 06:21:02 AM UTC 24 Sep 11 06:21:25 AM UTC 24 2934166345 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3307398022 Sep 11 06:20:55 AM UTC 24 Sep 11 06:21:28 AM UTC 24 11655101215 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2034159993 Sep 11 06:20:09 AM UTC 24 Sep 11 06:21:29 AM UTC 24 1584223222 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.328335324 Sep 11 06:21:30 AM UTC 24 Sep 11 06:21:32 AM UTC 24 39750431 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3016244337 Sep 11 06:20:10 AM UTC 24 Sep 11 06:21:36 AM UTC 24 818415122 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1763679090 Sep 11 06:20:45 AM UTC 24 Sep 11 06:21:37 AM UTC 24 1397167090 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1583335674 Sep 11 06:21:27 AM UTC 24 Sep 11 06:21:38 AM UTC 24 605281955 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1094207564 Sep 11 06:21:33 AM UTC 24 Sep 11 06:21:48 AM UTC 24 876117760 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3249194640 Sep 11 06:15:28 AM UTC 24 Sep 11 06:21:59 AM UTC 24 51861501929 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3167237977 Sep 11 06:20:24 AM UTC 24 Sep 11 06:22:01 AM UTC 24 38098198695 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.4117478231 Sep 11 06:21:36 AM UTC 24 Sep 11 06:22:02 AM UTC 24 735554389 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3181993519 Sep 11 06:20:37 AM UTC 24 Sep 11 06:22:02 AM UTC 24 34885419013 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1239964399 Sep 11 06:20:13 AM UTC 24 Sep 11 06:22:05 AM UTC 24 37694531875 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2902497582 Sep 11 06:22:03 AM UTC 24 Sep 11 06:22:15 AM UTC 24 1366531944 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2249463736 Sep 11 06:19:56 AM UTC 24 Sep 11 06:22:41 AM UTC 24 14293760018 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3577587186 Sep 11 06:22:41 AM UTC 24 Sep 11 06:22:48 AM UTC 24 1343098082 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3954944184 Sep 11 06:20:18 AM UTC 24 Sep 11 06:22:56 AM UTC 24 11011468244 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1051332725 Sep 11 06:22:03 AM UTC 24 Sep 11 06:22:56 AM UTC 24 5572525323 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3348196011 Sep 11 06:20:17 AM UTC 24 Sep 11 06:22:57 AM UTC 24 6361142604 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.11579377 Sep 11 06:22:59 AM UTC 24 Sep 11 06:23:01 AM UTC 24 32367671 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2396735911 Sep 11 06:19:30 AM UTC 24 Sep 11 06:23:13 AM UTC 24 43040144512 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.681507065 Sep 11 06:23:02 AM UTC 24 Sep 11 06:23:24 AM UTC 24 882701403 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1224705278 Sep 11 06:20:29 AM UTC 24 Sep 11 06:23:39 AM UTC 24 5189507605 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1392711874 Sep 11 06:21:03 AM UTC 24 Sep 11 06:24:06 AM UTC 24 86410515866 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2656980369 Sep 11 06:21:48 AM UTC 24 Sep 11 06:24:07 AM UTC 24 6299884772 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.265216027 Sep 11 06:22:01 AM UTC 24 Sep 11 06:24:08 AM UTC 24 794345813 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.510044872 Sep 11 06:17:24 AM UTC 24 Sep 11 06:24:12 AM UTC 24 19600410375 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3619143516 Sep 11 06:20:16 AM UTC 24 Sep 11 06:24:29 AM UTC 24 40737350750 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3474365468 Sep 11 06:22:57 AM UTC 24 Sep 11 06:24:25 AM UTC 24 10087511970 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1311643951 Sep 11 06:20:45 AM UTC 24 Sep 11 06:24:27 AM UTC 24 5264949051 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2367433612 Sep 11 06:20:33 AM UTC 24 Sep 11 06:24:33 AM UTC 24 2654556226 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1552368453 Sep 11 06:21:25 AM UTC 24 Sep 11 06:24:33 AM UTC 24 13588569966 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1793841029 Sep 11 06:24:07 AM UTC 24 Sep 11 06:24:33 AM UTC 24 1201667765 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4215394144 Sep 11 06:22:57 AM UTC 24 Sep 11 06:24:39 AM UTC 24 7810718206 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2994145640 Sep 11 06:24:34 AM UTC 24 Sep 11 06:24:40 AM UTC 24 367203725 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1675987590 Sep 11 06:21:26 AM UTC 24 Sep 11 06:24:47 AM UTC 24 22044622971 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1434897217 Sep 11 06:20:40 AM UTC 24 Sep 11 06:24:54 AM UTC 24 81026754039 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4143720471 Sep 11 06:24:54 AM UTC 24 Sep 11 06:24:56 AM UTC 24 11713338 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3858874001 Sep 11 06:24:57 AM UTC 24 Sep 11 06:25:09 AM UTC 24 721610657 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1466414304 Sep 11 06:24:12 AM UTC 24 Sep 11 06:25:13 AM UTC 24 778441664 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.723687760 Sep 11 06:24:25 AM UTC 24 Sep 11 06:25:23 AM UTC 24 11294641579 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2887957742 Sep 11 06:24:08 AM UTC 24 Sep 11 06:25:40 AM UTC 24 758138024 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2080146763 Sep 11 06:20:07 AM UTC 24 Sep 11 06:25:41 AM UTC 24 4723790075 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.853979067 Sep 11 06:21:05 AM UTC 24 Sep 11 06:26:36 AM UTC 24 23035033254 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3281667185 Sep 11 06:20:07 AM UTC 24 Sep 11 06:26:36 AM UTC 24 19755677220 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1557811862 Sep 11 06:20:22 AM UTC 24 Sep 11 06:26:37 AM UTC 24 3958071695 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.481549567 Sep 11 06:22:49 AM UTC 24 Sep 11 06:27:05 AM UTC 24 35949642726 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2785713587 Sep 11 06:20:28 AM UTC 24 Sep 11 06:27:05 AM UTC 24 47665509003 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1904178976 Sep 11 06:25:10 AM UTC 24 Sep 11 06:27:06 AM UTC 24 2677775139 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2378703656 Sep 11 06:24:41 AM UTC 24 Sep 11 06:27:07 AM UTC 24 11861103773 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3982217644 Sep 11 06:26:36 AM UTC 24 Sep 11 06:27:13 AM UTC 24 2844932438 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1697570324 Sep 11 06:27:08 AM UTC 24 Sep 11 06:27:15 AM UTC 24 832282322 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3520837720 Sep 11 06:23:40 AM UTC 24 Sep 11 06:27:18 AM UTC 24 26335276839 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.581406245 Sep 11 06:24:34 AM UTC 24 Sep 11 06:27:21 AM UTC 24 13548588800 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.543471482 Sep 11 06:20:43 AM UTC 24 Sep 11 06:27:39 AM UTC 24 57704044566 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4273016969 Sep 11 06:27:40 AM UTC 24 Sep 11 06:27:42 AM UTC 24 33222303 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3554189874 Sep 11 06:25:41 AM UTC 24 Sep 11 06:27:44 AM UTC 24 3746342691 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1532261752 Sep 11 06:21:38 AM UTC 24 Sep 11 06:27:45 AM UTC 24 6648265625 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.924793025 Sep 11 06:20:53 AM UTC 24 Sep 11 06:27:52 AM UTC 24 10461849009 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2326869502 Sep 11 06:26:37 AM UTC 24 Sep 11 06:28:03 AM UTC 24 3196792530 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2048413304 Sep 11 06:27:43 AM UTC 24 Sep 11 06:28:07 AM UTC 24 1568172785 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2581430715 Sep 11 06:11:14 AM UTC 24 Sep 11 06:28:11 AM UTC 24 61533863885 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3779228472 Sep 11 06:28:04 AM UTC 24 Sep 11 06:28:14 AM UTC 24 3690548261 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2742702837 Sep 11 06:11:02 AM UTC 24 Sep 11 06:28:17 AM UTC 24 71053019110 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1720129462 Sep 11 06:24:40 AM UTC 24 Sep 11 06:28:18 AM UTC 24 5239452119 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2162159018 Sep 11 06:27:20 AM UTC 24 Sep 11 06:28:23 AM UTC 24 5678589845 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.846530367 Sep 11 06:24:30 AM UTC 24 Sep 11 06:28:38 AM UTC 24 3427131024 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1230444116 Sep 11 06:25:42 AM UTC 24 Sep 11 06:28:49 AM UTC 24 12470475623 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3540288248 Sep 11 06:26:38 AM UTC 24 Sep 11 06:28:54 AM UTC 24 30082204189 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.484666664 Sep 11 06:25:24 AM UTC 24 Sep 11 06:28:55 AM UTC 24 2683282474 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1504731927 Sep 11 06:28:51 AM UTC 24 Sep 11 06:28:56 AM UTC 24 367674542 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3899951054 Sep 11 06:20:32 AM UTC 24 Sep 11 06:29:11 AM UTC 24 53722534326 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2635745055 Sep 11 06:29:11 AM UTC 24 Sep 11 06:29:13 AM UTC 24 14427043 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2734470361 Sep 11 06:28:14 AM UTC 24 Sep 11 06:29:23 AM UTC 24 3027605611 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1599584949 Sep 11 06:28:12 AM UTC 24 Sep 11 06:29:23 AM UTC 24 780556255 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2710506644 Sep 11 06:29:14 AM UTC 24 Sep 11 06:29:26 AM UTC 24 864933357 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1255218591 Sep 11 06:28:18 AM UTC 24 Sep 11 06:29:35 AM UTC 24 52482282689 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3897974340 Sep 11 06:20:34 AM UTC 24 Sep 11 06:29:44 AM UTC 24 8850088897 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3494124406 Sep 11 06:13:34 AM UTC 24 Sep 11 06:30:07 AM UTC 24 123411419207 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2902075236 Sep 11 06:28:57 AM UTC 24 Sep 11 06:30:16 AM UTC 24 1209764351 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3279822383 Sep 11 06:29:36 AM UTC 24 Sep 11 06:30:21 AM UTC 24 2022421261 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3472613709 Sep 11 06:27:13 AM UTC 24 Sep 11 06:30:24 AM UTC 24 14141674165 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1551161817 Sep 11 06:30:17 AM UTC 24 Sep 11 06:30:31 AM UTC 24 709338246 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3247954211 Sep 11 06:24:08 AM UTC 24 Sep 11 06:30:35 AM UTC 24 10260645984 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2871009336 Sep 11 06:27:05 AM UTC 24 Sep 11 06:30:36 AM UTC 24 39552505559 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.501246636 Sep 11 06:28:57 AM UTC 24 Sep 11 06:30:36 AM UTC 24 12320732217 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2386202318 Sep 11 06:30:36 AM UTC 24 Sep 11 06:30:42 AM UTC 24 1409835726 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1373839069 Sep 11 06:20:39 AM UTC 24 Sep 11 06:30:43 AM UTC 24 20048264219 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.565934992 Sep 11 06:20:54 AM UTC 24 Sep 11 06:30:46 AM UTC 24 19326248836 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3961913270 Sep 11 06:30:44 AM UTC 24 Sep 11 06:30:51 AM UTC 24 112563498 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.494613841 Sep 11 06:30:52 AM UTC 24 Sep 11 06:30:54 AM UTC 24 41252863 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1864063468 Sep 11 06:20:23 AM UTC 24 Sep 11 06:30:56 AM UTC 24 22876771263 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2233875325 Sep 11 06:27:16 AM UTC 24 Sep 11 06:30:58 AM UTC 24 104912455536 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4117198820 Sep 11 06:27:53 AM UTC 24 Sep 11 06:31:22 AM UTC 24 3771214164 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.885699078 Sep 11 06:20:22 AM UTC 24 Sep 11 06:31:23 AM UTC 24 35987355609 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.905037855 Sep 11 06:30:55 AM UTC 24 Sep 11 06:31:25 AM UTC 24 889675420 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3818211364 Sep 11 06:17:09 AM UTC 24 Sep 11 06:31:37 AM UTC 24 18835160191 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1934035037 Sep 11 06:28:55 AM UTC 24 Sep 11 06:31:43 AM UTC 24 17533232979 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3094789967 Sep 11 06:20:06 AM UTC 24 Sep 11 06:31:46 AM UTC 24 9331639611 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2750001279 Sep 11 06:30:22 AM UTC 24 Sep 11 06:31:47 AM UTC 24 14733135979 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3654943205 Sep 11 06:30:57 AM UTC 24 Sep 11 06:31:48 AM UTC 24 2144618591 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1592927317 Sep 11 06:30:08 AM UTC 24 Sep 11 06:31:50 AM UTC 24 3177952352 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1518840351 Sep 11 06:31:24 AM UTC 24 Sep 11 06:32:03 AM UTC 24 1989251069 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2438676156 Sep 11 06:32:04 AM UTC 24 Sep 11 06:32:10 AM UTC 24 709553075 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.730515288 Sep 11 06:24:29 AM UTC 24 Sep 11 06:32:20 AM UTC 24 7406124145 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2504131343 Sep 11 06:30:44 AM UTC 24 Sep 11 06:32:34 AM UTC 24 11447080280 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3927494378 Sep 11 06:31:47 AM UTC 24 Sep 11 06:32:41 AM UTC 24 12213654393 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.416658226 Sep 11 06:31:44 AM UTC 24 Sep 11 06:32:52 AM UTC 24 3189878921 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1643252195 Sep 11 06:32:53 AM UTC 24 Sep 11 06:32:55 AM UTC 24 49606574 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.3003619053 Sep 11 06:20:53 AM UTC 24 Sep 11 06:32:56 AM UTC 24 9718276621 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1213879727 Sep 11 06:32:34 AM UTC 24 Sep 11 06:33:05 AM UTC 24 2592649484 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2071570436 Sep 11 06:31:38 AM UTC 24 Sep 11 06:33:18 AM UTC 24 2935762811 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3256291544 Sep 11 06:21:53 AM UTC 24 Sep 11 06:33:23 AM UTC 24 7830823720 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3905764963 Sep 11 06:22:03 AM UTC 24 Sep 11 06:33:26 AM UTC 24 46759239122 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3210883343 Sep 11 06:29:27 AM UTC 24 Sep 11 06:33:29 AM UTC 24 7753980042 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.4159350167 Sep 11 06:21:37 AM UTC 24 Sep 11 06:33:32 AM UTC 24 158022414447 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3655738364 Sep 11 06:32:57 AM UTC 24 Sep 11 06:33:44 AM UTC 24 774866681 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.666641821 Sep 11 06:33:33 AM UTC 24 Sep 11 06:33:45 AM UTC 24 1383871729 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3921375253 Sep 11 06:20:37 AM UTC 24 Sep 11 06:33:49 AM UTC 24 34350037847 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.4007210231 Sep 11 06:28:08 AM UTC 24 Sep 11 06:34:15 AM UTC 24 14230573293 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.957734047 Sep 11 06:34:15 AM UTC 24 Sep 11 06:34:22 AM UTC 24 417684482 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.4097364035 Sep 11 06:31:23 AM UTC 24 Sep 11 06:34:38 AM UTC 24 2771530937 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.160522965 Sep 11 06:30:32 AM UTC 24 Sep 11 06:34:43 AM UTC 24 20569149216 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3296428542 Sep 11 06:33:31 AM UTC 24 Sep 11 06:34:45 AM UTC 24 3035751515 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1889296623 Sep 11 06:33:34 AM UTC 24 Sep 11 06:34:52 AM UTC 24 7556240121 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.258312186 Sep 11 06:32:10 AM UTC 24 Sep 11 06:34:52 AM UTC 24 2059293802 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.575658320 Sep 11 06:34:53 AM UTC 24 Sep 11 06:34:55 AM UTC 24 188579121 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.752556933 Sep 11 06:17:41 AM UTC 24 Sep 11 06:34:55 AM UTC 24 11741981956 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3722441784 Sep 11 06:34:44 AM UTC 24 Sep 11 06:34:57 AM UTC 24 527597032 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1590266577 Sep 11 06:33:24 AM UTC 24 Sep 11 06:35:04 AM UTC 24 1641916724 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3975503569 Sep 11 06:30:37 AM UTC 24 Sep 11 06:35:07 AM UTC 24 7725573590 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3445547961 Sep 11 06:30:36 AM UTC 24 Sep 11 06:35:12 AM UTC 24 8105821388 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1621838039 Sep 11 06:34:53 AM UTC 24 Sep 11 06:35:18 AM UTC 24 1697775988 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.732119280 Sep 11 06:35:19 AM UTC 24 Sep 11 06:35:27 AM UTC 24 2813309874 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1341370976 Sep 11 06:32:21 AM UTC 24 Sep 11 06:35:28 AM UTC 24 21654869742 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1993833595 Sep 11 06:35:13 AM UTC 24 Sep 11 06:35:37 AM UTC 24 709355201 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.633366589 Sep 11 06:35:05 AM UTC 24 Sep 11 06:35:38 AM UTC 24 3609990009 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1374922401 Sep 11 06:20:15 AM UTC 24 Sep 11 06:35:41 AM UTC 24 10117997126 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2534667693 Sep 11 06:28:41 AM UTC 24 Sep 11 06:35:44 AM UTC 24 46986903179 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.1567240567 Sep 11 06:31:51 AM UTC 24 Sep 11 06:35:46 AM UTC 24 2471450097 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3618876193 Sep 11 06:35:42 AM UTC 24 Sep 11 06:35:48 AM UTC 24 361042367 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2076412809 Sep 11 06:21:15 AM UTC 24 Sep 11 06:36:01 AM UTC 24 14245403973 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3818101255 Sep 11 06:24:34 AM UTC 24 Sep 11 06:36:09 AM UTC 24 29245417812 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3277700216 Sep 11 06:35:29 AM UTC 24 Sep 11 06:36:09 AM UTC 24 11965915235 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3869660579 Sep 11 06:36:10 AM UTC 24 Sep 11 06:36:13 AM UTC 24 16198748 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1778684979 Sep 11 06:34:40 AM UTC 24 Sep 11 06:36:19 AM UTC 24 10901939198 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1326222977 Sep 11 06:35:48 AM UTC 24 Sep 11 06:36:28 AM UTC 24 1415680712 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.3528388631 Sep 11 06:36:10 AM UTC 24 Sep 11 06:36:39 AM UTC 24 1894912572 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4010675699 Sep 11 06:36:40 AM UTC 24 Sep 11 06:36:53 AM UTC 24 1715601642 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3955230868 Sep 11 06:20:13 AM UTC 24 Sep 11 06:38:14 AM UTC 24 15017259320 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2835841327 Sep 11 06:21:12 AM UTC 24 Sep 11 06:38:14 AM UTC 24 95042150588 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.143271284 Sep 11 06:20:24 AM UTC 24 Sep 11 06:38:31 AM UTC 24 105129709601 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.785380394 Sep 11 06:28:24 AM UTC 24 Sep 11 06:38:46 AM UTC 24 31878370786 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.245317923 Sep 11 06:38:16 AM UTC 24 Sep 11 06:38:46 AM UTC 24 1429031694 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1482041191 Sep 11 06:27:05 AM UTC 24 Sep 11 06:38:48 AM UTC 24 14224502493 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1839642867 Sep 11 06:35:47 AM UTC 24 Sep 11 06:39:01 AM UTC 24 11842049349 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3504972377 Sep 11 06:23:14 AM UTC 24 Sep 11 06:39:06 AM UTC 24 16399410421 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.333824484 Sep 11 06:39:02 AM UTC 24 Sep 11 06:39:09 AM UTC 24 349287940 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.2437696647 Sep 11 06:11:02 AM UTC 24 Sep 11 06:39:39 AM UTC 24 126662429273 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.199514567 Sep 11 06:22:16 AM UTC 24 Sep 11 06:39:40 AM UTC 24 73301672051 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2195015557 Sep 11 06:34:58 AM UTC 24 Sep 11 06:39:40 AM UTC 24 4058434330 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.4223324884 Sep 11 06:20:52 AM UTC 24 Sep 11 06:39:42 AM UTC 24 15279311065 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4285487011 Sep 11 06:39:41 AM UTC 24 Sep 11 06:39:43 AM UTC 24 32151805 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.523719814 Sep 11 06:34:56 AM UTC 24 Sep 11 06:39:54 AM UTC 24 18158092023 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2316939028 Sep 11 06:39:43 AM UTC 24 Sep 11 06:40:03 AM UTC 24 1167855607 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1815227826 Sep 11 06:38:16 AM UTC 24 Sep 11 06:40:22 AM UTC 24 10864288711 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.961909910 Sep 11 06:36:29 AM UTC 24 Sep 11 06:40:25 AM UTC 24 28389506219 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.3072515483 Sep 11 06:20:25 AM UTC 24 Sep 11 06:40:27 AM UTC 24 7837134907 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1333065613 Sep 11 06:29:45 AM UTC 24 Sep 11 06:40:34 AM UTC 24 54122797698 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1304304388 Sep 11 06:33:19 AM UTC 24 Sep 11 06:40:37 AM UTC 24 9855367219 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3456601443 Sep 11 06:40:23 AM UTC 24 Sep 11 06:40:39 AM UTC 24 1427637680 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3584847503 Sep 11 06:31:25 AM UTC 24 Sep 11 06:40:48 AM UTC 24 20086692315 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2565483387 Sep 11 06:40:28 AM UTC 24 Sep 11 06:40:49 AM UTC 24 744369341 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3724270750 Sep 11 06:40:36 AM UTC 24 Sep 11 06:40:58 AM UTC 24 3583505466 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2072968250 Sep 11 06:39:10 AM UTC 24 Sep 11 06:40:59 AM UTC 24 5809041963 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2526235381 Sep 11 06:40:59 AM UTC 24 Sep 11 06:41:04 AM UTC 24 374571949 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4164920099 Sep 11 06:35:07 AM UTC 24 Sep 11 06:41:13 AM UTC 24 71252576599 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3800523848 Sep 11 06:39:06 AM UTC 24 Sep 11 06:41:15 AM UTC 24 4030122692 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1592579476 Sep 11 06:33:28 AM UTC 24 Sep 11 06:41:20 AM UTC 24 15366396435 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.458859655 Sep 11 06:40:38 AM UTC 24 Sep 11 06:41:21 AM UTC 24 5498720430 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2339702498 Sep 11 06:41:21 AM UTC 24 Sep 11 06:41:23 AM UTC 24 33636357 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.955104391 Sep 11 06:38:32 AM UTC 24 Sep 11 06:41:31 AM UTC 24 53696754065 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3714545008 Sep 11 06:35:45 AM UTC 24 Sep 11 06:41:38 AM UTC 24 20912163915 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3672652979 Sep 11 06:41:14 AM UTC 24 Sep 11 06:41:41 AM UTC 24 1918769762 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4050697619 Sep 11 06:20:25 AM UTC 24 Sep 11 06:41:45 AM UTC 24 8289626963 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3064641100 Sep 11 06:27:07 AM UTC 24 Sep 11 06:41:51 AM UTC 24 18748854490 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.3903977079 Sep 11 06:41:23 AM UTC 24 Sep 11 06:42:09 AM UTC 24 5828236130 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3591582581 Sep 11 06:41:41 AM UTC 24 Sep 11 06:42:21 AM UTC 24 2121110652 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3908829080 Sep 11 06:42:10 AM UTC 24 Sep 11 06:42:28 AM UTC 24 5793653491 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2556427497 Sep 11 06:34:22 AM UTC 24 Sep 11 06:42:28 AM UTC 24 20712207105 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1866343406 Sep 11 06:35:38 AM UTC 24 Sep 11 06:42:51 AM UTC 24 13860796716 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2464577873 Sep 11 06:41:52 AM UTC 24 Sep 11 06:42:58 AM UTC 24 7542483213 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4171651116 Sep 11 06:39:39 AM UTC 24 Sep 11 06:43:03 AM UTC 24 8099251461 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1264809071 Sep 11 06:22:06 AM UTC 24 Sep 11 06:43:04 AM UTC 24 42622567579 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3872821156 Sep 11 06:42:58 AM UTC 24 Sep 11 06:43:05 AM UTC 24 3067243827 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.851124447 Sep 11 06:41:05 AM UTC 24 Sep 11 06:43:19 AM UTC 24 1617424363 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1346338328 Sep 11 06:43:06 AM UTC 24 Sep 11 06:43:20 AM UTC 24 503481093 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1589126616 Sep 11 06:43:21 AM UTC 24 Sep 11 06:43:24 AM UTC 24 32682816 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.947083783 Sep 11 06:42:22 AM UTC 24 Sep 11 06:43:30 AM UTC 24 9354930565 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.1926317805 Sep 11 06:33:05 AM UTC 24 Sep 11 06:43:33 AM UTC 24 18664639033 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.942110732 Sep 11 06:43:25 AM UTC 24 Sep 11 06:43:39 AM UTC 24 3346905108 ps