Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	354009672	1			T2	1038		T4	1412		T5	4930
instr_valid_dis	313279905	1			T2	1038		T4	1412		T5	4930
instr_en	28203545	1			T26	82756		T27	160424		T146	47896

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12733614	1			T26	19606		T27	86000		T146	110672
sram_ifetch_valid_disable	315787412	1			T2	1038		T4	1412		T5	4930
sram_ifetch_enable	25488646	1			T28	3352		T26	52846		T27	44912

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	354009672	1			T2	1038		T4	1412		T5	4930
hw_debug_en_valid_off	310352398	1			T2	1038		T4	1412		T5	4930
hw_debug_en_on	28569722	1			T28	48936		T26	58570		T27	45372

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	315787412	1			T2	1038		T4	1412		T5	4930
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	296915263	1			T2	1038		T4	1412		T5	4930
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12165563	1			T26	82756		T27	30158		T146	3926
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4913330	1			T27	52154		T146	39902		T113	15260
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1752356	1			T146	39902		T152	72832		T153	82476
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2094322	1			T27	52154		T113	15260		T142	89856
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5410776	1			T26	19606		T27	33846		T146	26800
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1902944	1			T27	604		T146	26800		T142	96
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2909958	1			T27	33242		T113	80746		T142	67636
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	15232046	1			T28	48936		T26	18964		T27	11484
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4705824	1			T26	17058		T27	11484		T147	26700
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6421204	1			T26	1906		T146	76		T113	63860

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9922350	1			T27	44870		T113	79400		T147	6610
lc_exec_en	7926900	1			T26	20000		T27	42		T113	43536
valid_exec_dis	307238644	1			T2	1038		T4	1412		T5	4930
invalid_exec_dis	38222260	1			T28	3352		T26	72452		T27	130912