Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.30 99.25 95.11 99.72 100.00 96.38 99.13 98.54


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.75 61.75 90.61 90.61 61.14 61.14 51.27 51.27 23.81 23.81 77.45 77.45 92.89 92.89 35.10 35.10 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3378520034
87.76 26.01 96.81 6.20 81.40 20.26 89.05 37.78 90.48 66.67 88.73 11.27 95.65 2.76 72.21 37.11 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.178081057
92.00 4.24 97.99 1.17 84.95 3.55 95.11 6.06 100.00 9.52 91.67 2.94 96.23 0.58 78.06 5.85 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.267186562
93.74 1.74 98.32 0.34 88.27 3.32 95.39 0.28 100.00 0.00 93.87 2.21 96.23 0.00 84.10 6.03 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.1705138285
94.96 1.22 98.91 0.59 90.52 2.25 97.66 2.27 100.00 0.00 95.83 1.96 96.81 0.58 85.01 0.91 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1881311892
95.74 0.78 98.91 0.00 90.88 0.36 97.66 0.00 100.00 0.00 95.83 0.00 96.81 0.00 90.13 5.12 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2952021163
96.42 0.67 99.16 0.25 90.88 0.00 98.07 0.41 100.00 0.00 96.08 0.25 96.95 0.15 93.78 3.66 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.940859925
96.68 0.26 99.16 0.00 90.88 0.00 98.07 0.00 100.00 0.00 96.08 0.00 96.95 0.00 95.61 1.83 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1933314515
96.93 0.25 99.16 0.00 91.11 0.24 98.07 0.00 100.00 0.00 96.08 0.00 98.26 1.31 95.80 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.415237881
97.10 0.18 99.16 0.00 91.11 0.00 98.07 0.00 100.00 0.00 96.08 0.00 99.13 0.87 96.16 0.37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1669789606
97.28 0.18 99.16 0.00 91.23 0.12 98.69 0.62 100.00 0.00 96.57 0.49 99.13 0.00 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3814565538
97.42 0.14 99.25 0.08 91.23 0.00 99.59 0.90 100.00 0.00 96.57 0.00 99.13 0.00 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.652225473
97.52 0.10 99.25 0.00 91.23 0.00 99.59 0.00 100.00 0.00 96.57 0.00 99.13 0.00 96.89 0.73 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2429762597
97.59 0.07 99.25 0.00 91.35 0.12 99.59 0.00 100.00 0.00 96.57 0.00 99.13 0.00 97.26 0.37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3748007060
97.65 0.06 99.25 0.00 91.71 0.36 99.66 0.07 100.00 0.00 96.57 0.00 99.13 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.20576730
97.70 0.05 99.25 0.00 91.71 0.00 99.66 0.00 100.00 0.00 96.57 0.00 99.13 0.00 97.62 0.37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.536732109
97.76 0.05 99.25 0.00 91.71 0.00 99.66 0.00 100.00 0.00 96.57 0.00 99.13 0.00 97.99 0.37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1109952288
97.80 0.04 99.25 0.00 91.82 0.12 99.66 0.00 100.00 0.00 96.57 0.00 99.13 0.00 98.17 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.459027745
97.83 0.03 99.25 0.00 91.82 0.00 99.66 0.00 100.00 0.00 96.57 0.00 99.13 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2683230254
97.85 0.03 99.25 0.00 91.82 0.00 99.66 0.00 100.00 0.00 96.57 0.00 99.13 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2290911205
97.86 0.01 99.25 0.00 91.82 0.00 99.72 0.07 100.00 0.00 96.57 0.00 99.13 0.00 98.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3574427612

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3244358318
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2294335312
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2818040016
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1426883311
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.185977465
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.982537560
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3904548516
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1094989429
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.27433529
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1803127501
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.607660888
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2732894835
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1977893813
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2274012978
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.894830187
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.632131392
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3674474503
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3865496414
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2920568121
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3794308077
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2883380710
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2386095651
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2228640279
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3841596199
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1915489391
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.63336428
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2893926127
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1252740945
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3609211845
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1743092265
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3423374507
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3847581523
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3523609556
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.269512966
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1872783798
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2702202058
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1048528532
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2826305086
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3900231550
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2034440369
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3823712091
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2449815772
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3306533684
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.664824488
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.103138695
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1116062530
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1896727387
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.870120077
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2891566675
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2194230779
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1514538010
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3793596301
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2420762178
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3981648189
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3706119220
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1153314646
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2096281169
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.861291316
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2621613430
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.551122936
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1381119226
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2957382524
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1537336645
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3332099765
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2346920796
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2617717386
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1382507544
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.522068345
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.390171027
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4142237405
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3659904984
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1000608084
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2275075414
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1313609589
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3794801685
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.59242349
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3765465118
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.548122360
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2892919551
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4177722466
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.6381717
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1316950106
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.397541652
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.545412582
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2997934642
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3020721596
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3505605229
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3284468130
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3730675596
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.4079549454
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.432714595
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2275240895
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.747275976
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1936357085
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3088026047
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3783578192
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3517072538
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3864026853
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4033560812
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.726301071
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1730094426
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2400944273
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1116507879
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1124355696
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.75480758
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3627525386
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1750083601
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2421009010
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3393719497
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1948748145
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4264788754
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.352050749
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.919886503
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4102615146
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4167204117
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2856239821
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2718803569
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1436599140
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1882180676
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1977246674
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2155874739
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4208907126
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.3160293106
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1474196335
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2051974542
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4237284243
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.897928176
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3773879019
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.4120384340
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2598677375
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3576163171
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1792517887
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.291025789
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.720667393
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.12002077
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.24558827
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993877009
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.718385332
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2224863135
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3594493935



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.20576730 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:10 AM UTC 24 15591825 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2177028155 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:11 AM UTC 24 217509304 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.652225473 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:13 AM UTC 24 1019289141 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.2560032071 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:14 AM UTC 24 5042830030 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3378520034 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:19 AM UTC 24 788820219 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1462524040 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:34 AM UTC 24 6970635759 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.504164457 Sep 24 09:49:40 AM UTC 24 Sep 24 09:49:42 AM UTC 24 38832394 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1881311892 Sep 24 09:49:40 AM UTC 24 Sep 24 09:49:43 AM UTC 24 115018909 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.208403677 Sep 24 09:49:39 AM UTC 24 Sep 24 09:49:44 AM UTC 24 1348915735 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1345480380 Sep 24 09:49:39 AM UTC 24 Sep 24 09:49:47 AM UTC 24 1389595186 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3931025955 Sep 24 09:49:45 AM UTC 24 Sep 24 09:49:52 AM UTC 24 376090934 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1355583146 Sep 24 09:49:08 AM UTC 24 Sep 24 09:49:54 AM UTC 24 796188904 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1062355938 Sep 24 09:49:39 AM UTC 24 Sep 24 09:49:56 AM UTC 24 3119570623 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3336847562 Sep 24 09:49:40 AM UTC 24 Sep 24 09:49:59 AM UTC 24 707727585 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2509087476 Sep 24 09:49:38 AM UTC 24 Sep 24 09:50:03 AM UTC 24 1269974212 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2008501732 Sep 24 09:50:04 AM UTC 24 Sep 24 09:50:06 AM UTC 24 35261366 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.106981528 Sep 24 09:50:02 AM UTC 24 Sep 24 09:50:06 AM UTC 24 541543231 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.885118329 Sep 24 09:49:40 AM UTC 24 Sep 24 09:50:12 AM UTC 24 5388407663 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.267186562 Sep 24 09:49:08 AM UTC 24 Sep 24 09:50:14 AM UTC 24 58349588908 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3551512300 Sep 24 09:49:07 AM UTC 24 Sep 24 09:50:15 AM UTC 24 3996976306 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1738936513 Sep 24 09:49:40 AM UTC 24 Sep 24 09:50:22 AM UTC 24 1876488171 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.4253705174 Sep 24 09:50:16 AM UTC 24 Sep 24 09:50:31 AM UTC 24 2683487456 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2611785831 Sep 24 09:49:56 AM UTC 24 Sep 24 09:50:44 AM UTC 24 5139694491 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.3768596383 Sep 24 09:50:08 AM UTC 24 Sep 24 09:50:47 AM UTC 24 1219137373 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2938286315 Sep 24 09:49:08 AM UTC 24 Sep 24 09:50:50 AM UTC 24 3133609629 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3819048539 Sep 24 09:49:39 AM UTC 24 Sep 24 09:50:57 AM UTC 24 4160263918 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.178081057 Sep 24 09:49:40 AM UTC 24 Sep 24 09:50:59 AM UTC 24 8257703574 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2925316703 Sep 24 09:49:40 AM UTC 24 Sep 24 09:50:59 AM UTC 24 796579540 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1540322086 Sep 24 09:51:00 AM UTC 24 Sep 24 09:51:05 AM UTC 24 684888551 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2243271174 Sep 24 09:49:40 AM UTC 24 Sep 24 09:51:08 AM UTC 24 3921071701 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1870810978 Sep 24 09:49:39 AM UTC 24 Sep 24 09:51:08 AM UTC 24 12856418697 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3729220215 Sep 24 09:50:45 AM UTC 24 Sep 24 09:51:24 AM UTC 24 5231991881 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3531721400 Sep 24 09:49:08 AM UTC 24 Sep 24 09:51:28 AM UTC 24 12572245758 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1659517642 Sep 24 09:51:29 AM UTC 24 Sep 24 09:51:31 AM UTC 24 46969175 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3919253189 Sep 24 09:51:24 AM UTC 24 Sep 24 09:51:31 AM UTC 24 854901361 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.979061593 Sep 24 09:50:32 AM UTC 24 Sep 24 09:51:31 AM UTC 24 1228792832 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4226047866 Sep 24 09:49:40 AM UTC 24 Sep 24 09:51:32 AM UTC 24 63954920870 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.3233040982 Sep 24 09:51:32 AM UTC 24 Sep 24 09:51:39 AM UTC 24 773783948 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1827811917 Sep 24 09:49:08 AM UTC 24 Sep 24 09:51:42 AM UTC 24 27037149955 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3814565538 Sep 24 09:51:10 AM UTC 24 Sep 24 09:51:59 AM UTC 24 1415102221 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3765686691 Sep 24 09:49:53 AM UTC 24 Sep 24 09:52:02 AM UTC 24 6293289326 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3391502549 Sep 24 09:51:40 AM UTC 24 Sep 24 09:52:13 AM UTC 24 641742082 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.691796253 Sep 24 09:50:49 AM UTC 24 Sep 24 09:52:15 AM UTC 24 10653695532 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3087605075 Sep 24 09:51:59 AM UTC 24 Sep 24 09:52:24 AM UTC 24 2778541047 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1669789606 Sep 24 09:49:39 AM UTC 24 Sep 24 09:52:58 AM UTC 24 4571248769 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.940859925 Sep 24 09:49:39 AM UTC 24 Sep 24 09:53:10 AM UTC 24 8701916868 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1724317190 Sep 24 09:53:11 AM UTC 24 Sep 24 09:53:19 AM UTC 24 4804251255 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2689923526 Sep 24 09:52:14 AM UTC 24 Sep 24 09:53:28 AM UTC 24 15297174807 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.54353179 Sep 24 09:52:03 AM UTC 24 Sep 24 09:53:47 AM UTC 24 1635582366 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1507752521 Sep 24 09:50:16 AM UTC 24 Sep 24 09:53:52 AM UTC 24 6950983867 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.4030144336 Sep 24 09:49:49 AM UTC 24 Sep 24 09:53:59 AM UTC 24 8210474525 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1286434570 Sep 24 09:53:47 AM UTC 24 Sep 24 09:54:04 AM UTC 24 2012956264 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3325311036 Sep 24 09:54:00 AM UTC 24 Sep 24 09:54:04 AM UTC 24 135669544 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.145160865 Sep 24 09:54:05 AM UTC 24 Sep 24 09:54:07 AM UTC 24 54243726 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.976545929 Sep 24 09:51:10 AM UTC 24 Sep 24 09:54:11 AM UTC 24 20879144224 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3642073997 Sep 24 09:49:08 AM UTC 24 Sep 24 09:54:26 AM UTC 24 20757527499 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1379277634 Sep 24 09:54:05 AM UTC 24 Sep 24 09:54:39 AM UTC 24 1333459585 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.111019369 Sep 24 09:49:08 AM UTC 24 Sep 24 09:54:39 AM UTC 24 28220146497 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2918498620 Sep 24 09:49:40 AM UTC 24 Sep 24 09:54:40 AM UTC 24 16760122032 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1532043658 Sep 24 09:49:39 AM UTC 24 Sep 24 09:54:54 AM UTC 24 21004018113 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3356481265 Sep 24 09:49:08 AM UTC 24 Sep 24 09:55:03 AM UTC 24 9954264968 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3155955009 Sep 24 09:51:06 AM UTC 24 Sep 24 09:55:31 AM UTC 24 26265145786 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2097097066 Sep 24 09:49:08 AM UTC 24 Sep 24 09:55:34 AM UTC 24 8633014049 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4280809051 Sep 24 09:52:16 AM UTC 24 Sep 24 09:55:35 AM UTC 24 2780130110 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.283146558 Sep 24 09:54:40 AM UTC 24 Sep 24 09:55:44 AM UTC 24 4838319651 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.194298344 Sep 24 09:54:55 AM UTC 24 Sep 24 09:55:45 AM UTC 24 1516441449 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3234956709 Sep 24 09:49:38 AM UTC 24 Sep 24 09:55:48 AM UTC 24 4877951558 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.665119758 Sep 24 09:55:45 AM UTC 24 Sep 24 09:55:51 AM UTC 24 346332365 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3282428852 Sep 24 09:55:52 AM UTC 24 Sep 24 09:56:03 AM UTC 24 501718900 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.106273729 Sep 24 09:50:24 AM UTC 24 Sep 24 09:56:29 AM UTC 24 13673421235 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.954505884 Sep 24 09:54:41 AM UTC 24 Sep 24 09:56:29 AM UTC 24 780048793 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3830631735 Sep 24 09:56:30 AM UTC 24 Sep 24 09:56:32 AM UTC 24 15249135 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.4288298818 Sep 24 09:56:30 AM UTC 24 Sep 24 09:56:44 AM UTC 24 2793629381 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3214049840 Sep 24 09:53:29 AM UTC 24 Sep 24 09:57:13 AM UTC 24 38377540391 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1066704462 Sep 24 09:55:04 AM UTC 24 Sep 24 09:57:35 AM UTC 24 52335001170 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.884517082 Sep 24 09:57:36 AM UTC 24 Sep 24 09:58:00 AM UTC 24 3548744404 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2442081310 Sep 24 09:55:49 AM UTC 24 Sep 24 09:58:23 AM UTC 24 2525037285 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1719760250 Sep 24 09:49:40 AM UTC 24 Sep 24 09:58:27 AM UTC 24 17629321761 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1609550956 Sep 24 09:50:08 AM UTC 24 Sep 24 09:58:38 AM UTC 24 18652616832 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3823701076 Sep 24 09:49:40 AM UTC 24 Sep 24 09:58:50 AM UTC 24 17825159399 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.869010301 Sep 24 09:54:27 AM UTC 24 Sep 24 09:59:05 AM UTC 24 14248535326 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2317049588 Sep 24 09:58:24 AM UTC 24 Sep 24 09:59:18 AM UTC 24 1998776962 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2645950929 Sep 24 09:51:43 AM UTC 24 Sep 24 09:59:23 AM UTC 24 32248347343 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3232884345 Sep 24 09:58:39 AM UTC 24 Sep 24 09:59:23 AM UTC 24 4643413776 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.854989693 Sep 24 09:59:25 AM UTC 24 Sep 24 09:59:32 AM UTC 24 3354386481 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2495130475 Sep 24 09:51:33 AM UTC 24 Sep 24 09:59:44 AM UTC 24 4865539199 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3218131835 Sep 24 09:49:39 AM UTC 24 Sep 24 09:59:50 AM UTC 24 35821029941 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3289264517 Sep 24 09:59:45 AM UTC 24 Sep 24 10:00:00 AM UTC 24 797361401 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3924134922 Sep 24 10:00:00 AM UTC 24 Sep 24 10:00:02 AM UTC 24 14935635 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.747275976 Sep 24 09:58:28 AM UTC 24 Sep 24 10:00:07 AM UTC 24 3224438600 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.75480758 Sep 24 10:00:06 AM UTC 24 Sep 24 10:00:28 AM UTC 24 3616669708 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.266065858 Sep 24 09:49:43 AM UTC 24 Sep 24 10:00:53 AM UTC 24 9385980231 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.4243481895 Sep 24 09:55:34 AM UTC 24 Sep 24 10:00:58 AM UTC 24 23903153436 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2400944273 Sep 24 10:00:59 AM UTC 24 Sep 24 10:01:07 AM UTC 24 426290575 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.1705138285 Sep 24 09:51:00 AM UTC 24 Sep 24 10:01:24 AM UTC 24 36869893347 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2856776957 Sep 24 09:56:33 AM UTC 24 Sep 24 10:01:38 AM UTC 24 6002976729 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4033560812 Sep 24 10:01:25 AM UTC 24 Sep 24 10:01:41 AM UTC 24 2853446220 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3113161443 Sep 24 09:53:20 AM UTC 24 Sep 24 10:01:41 AM UTC 24 21305183718 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1599689436 Sep 24 09:54:40 AM UTC 24 Sep 24 10:01:43 AM UTC 24 14098637858 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2086534722 Sep 24 09:55:46 AM UTC 24 Sep 24 10:01:44 AM UTC 24 21539135914 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3295000254 Sep 24 09:50:51 AM UTC 24 Sep 24 10:01:51 AM UTC 24 130936441246 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1323829515 Sep 24 10:01:52 AM UTC 24 Sep 24 10:01:59 AM UTC 24 348459090 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3393719497 Sep 24 10:01:39 AM UTC 24 Sep 24 10:02:13 AM UTC 24 729357928 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3849122760 Sep 24 09:59:25 AM UTC 24 Sep 24 10:02:24 AM UTC 24 27728358155 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.128140285 Sep 24 09:52:24 AM UTC 24 Sep 24 10:02:28 AM UTC 24 14138968705 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2275240895 Sep 24 09:57:14 AM UTC 24 Sep 24 10:02:35 AM UTC 24 17931019747 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3088026047 Sep 24 10:02:36 AM UTC 24 Sep 24 10:02:38 AM UTC 24 16785638 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1750083601 Sep 24 10:02:25 AM UTC 24 Sep 24 10:02:40 AM UTC 24 279387674 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1246099102 Sep 24 09:59:33 AM UTC 24 Sep 24 10:02:44 AM UTC 24 4387724617 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.240416201 Sep 24 10:02:39 AM UTC 24 Sep 24 10:03:11 AM UTC 24 1271696136 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2040035233 Sep 24 09:54:09 AM UTC 24 Sep 24 10:03:55 AM UTC 24 10524276967 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.4079549454 Sep 24 09:58:50 AM UTC 24 Sep 24 10:03:56 AM UTC 24 6381915082 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3864026853 Sep 24 10:01:41 AM UTC 24 Sep 24 10:04:02 AM UTC 24 49505776341 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.604440582 Sep 24 09:49:45 AM UTC 24 Sep 24 10:04:04 AM UTC 24 55468619472 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1617639470 Sep 24 09:52:59 AM UTC 24 Sep 24 10:04:14 AM UTC 24 4782076721 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2239321749 Sep 24 09:49:08 AM UTC 24 Sep 24 10:04:17 AM UTC 24 108935553557 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2718803569 Sep 24 10:03:56 AM UTC 24 Sep 24 10:04:20 AM UTC 24 1795966946 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2421009010 Sep 24 10:00:53 AM UTC 24 Sep 24 10:04:25 AM UTC 24 12635152353 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2558113885 Sep 24 09:58:01 AM UTC 24 Sep 24 10:04:29 AM UTC 24 23238120783 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1882180676 Sep 24 10:04:30 AM UTC 24 Sep 24 10:04:38 AM UTC 24 678749350 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4167204117 Sep 24 10:04:03 AM UTC 24 Sep 24 10:04:45 AM UTC 24 1436459520 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.726301071 Sep 24 10:02:15 AM UTC 24 Sep 24 10:05:01 AM UTC 24 6574708032 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4208907126 Sep 24 10:04:04 AM UTC 24 Sep 24 10:05:03 AM UTC 24 2953022008 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2643440331 Sep 24 10:05:02 AM UTC 24 Sep 24 10:05:35 AM UTC 24 2333199026 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4264788754 Sep 24 10:05:36 AM UTC 24 Sep 24 10:05:38 AM UTC 24 14609240 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.24558827 Sep 24 10:05:39 AM UTC 24 Sep 24 10:05:53 AM UTC 24 1630090643 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.2234254256 Sep 24 09:50:59 AM UTC 24 Sep 24 10:06:06 AM UTC 24 7182370147 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2856239821 Sep 24 10:04:46 AM UTC 24 Sep 24 10:06:32 AM UTC 24 13354577161 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4102615146 Sep 24 10:04:15 AM UTC 24 Sep 24 10:06:48 AM UTC 24 24945394673 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1436599140 Sep 24 10:03:58 AM UTC 24 Sep 24 10:06:52 AM UTC 24 5485622297 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1792517887 Sep 24 10:06:48 AM UTC 24 Sep 24 10:06:55 AM UTC 24 372455812 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1116507879 Sep 24 10:01:09 AM UTC 24 Sep 24 10:06:56 AM UTC 24 21784396306 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3773879019 Sep 24 10:06:57 AM UTC 24 Sep 24 10:07:19 AM UTC 24 2937123834 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3074679814 Sep 24 09:49:39 AM UTC 24 Sep 24 10:07:37 AM UTC 24 102874920942 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2956283182 Sep 24 10:01:59 AM UTC 24 Sep 24 10:07:40 AM UTC 24 28261055239 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3594493935 Sep 24 10:06:57 AM UTC 24 Sep 24 10:07:44 AM UTC 24 3833779907 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2155874739 Sep 24 10:03:12 AM UTC 24 Sep 24 10:07:53 AM UTC 24 13669400525 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1559846573 Sep 24 10:04:38 AM UTC 24 Sep 24 10:07:57 AM UTC 24 5058761385 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.720667393 Sep 24 10:07:54 AM UTC 24 Sep 24 10:08:00 AM UTC 24 1342071052 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2429762597 Sep 24 09:49:08 AM UTC 24 Sep 24 10:08:19 AM UTC 24 81971510632 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.718385332 Sep 24 10:08:19 AM UTC 24 Sep 24 10:08:27 AM UTC 24 736095043 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.4120384340 Sep 24 10:08:00 AM UTC 24 Sep 24 10:09:31 AM UTC 24 9850478717 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1474196335 Sep 24 10:09:32 AM UTC 24 Sep 24 10:09:34 AM UTC 24 18381137 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.897928176 Sep 24 10:07:20 AM UTC 24 Sep 24 10:09:46 AM UTC 24 13240354605 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.630646702 Sep 24 10:09:35 AM UTC 24 Sep 24 10:10:05 AM UTC 24 2988704432 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.692811627 Sep 24 10:02:41 AM UTC 24 Sep 24 10:10:11 AM UTC 24 16646267485 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.2028877032 Sep 24 09:59:18 AM UTC 24 Sep 24 10:10:41 AM UTC 24 3331032745 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.3160293106 Sep 24 10:07:38 AM UTC 24 Sep 24 10:10:52 AM UTC 24 4739569942 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2568551628 Sep 24 10:10:42 AM UTC 24 Sep 24 10:10:57 AM UTC 24 825132510 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3228324545 Sep 24 10:10:58 AM UTC 24 Sep 24 10:11:06 AM UTC 24 675407310 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2126128532 Sep 24 10:11:07 AM UTC 24 Sep 24 10:11:14 AM UTC 24 1393261058 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2598677375 Sep 24 10:07:57 AM UTC 24 Sep 24 10:11:32 AM UTC 24 6916830447 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1948748145 Sep 24 10:04:18 AM UTC 24 Sep 24 10:11:34 AM UTC 24 17572464668 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.942161037 Sep 24 09:49:07 AM UTC 24 Sep 24 10:11:55 AM UTC 24 20545333377 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1730094426 Sep 24 10:00:07 AM UTC 24 Sep 24 10:11:58 AM UTC 24 51741130544 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1621470327 Sep 24 10:11:58 AM UTC 24 Sep 24 10:12:03 AM UTC 24 344902365 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3453423895 Sep 24 09:59:06 AM UTC 24 Sep 24 10:12:03 AM UTC 24 14393928211 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2055188763 Sep 24 10:11:33 AM UTC 24 Sep 24 10:12:47 AM UTC 24 3376370981 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3748007060 Sep 24 10:11:16 AM UTC 24 Sep 24 10:13:03 AM UTC 24 19495939033 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.291025789 Sep 24 10:06:54 AM UTC 24 Sep 24 10:13:43 AM UTC 24 13388754496 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2056925300 Sep 24 10:13:44 AM UTC 24 Sep 24 10:13:46 AM UTC 24 30218729 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2318720997 Sep 24 10:13:47 AM UTC 24 Sep 24 10:14:20 AM UTC 24 746542394 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1124355696 Sep 24 10:01:45 AM UTC 24 Sep 24 10:14:27 AM UTC 24 16055671562 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2764610916 Sep 24 10:12:48 AM UTC 24 Sep 24 10:14:29 AM UTC 24 1012951784 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1977246674 Sep 24 10:04:26 AM UTC 24 Sep 24 10:15:06 AM UTC 24 49810482253 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.354295688 Sep 24 10:10:12 AM UTC 24 Sep 24 10:15:14 AM UTC 24 4380509024 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3576163171 Sep 24 10:05:53 AM UTC 24 Sep 24 10:15:26 AM UTC 24 70551980809 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.543631537 Sep 24 10:12:04 AM UTC 24 Sep 24 10:15:34 AM UTC 24 8059942156 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2909185917 Sep 24 10:15:06 AM UTC 24 Sep 24 10:15:44 AM UTC 24 3358492955 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2224863135 Sep 24 10:06:32 AM UTC 24 Sep 24 10:15:53 AM UTC 24 6732504132 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3789116344 Sep 24 10:10:52 AM UTC 24 Sep 24 10:16:20 AM UTC 24 45873401461 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4009564866 Sep 24 09:55:31 AM UTC 24 Sep 24 10:16:30 AM UTC 24 30722364413 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2095850546 Sep 24 10:15:28 AM UTC 24 Sep 24 10:16:51 AM UTC 24 1523177172 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3117772629 Sep 24 10:15:35 AM UTC 24 Sep 24 10:16:54 AM UTC 24 827339817 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3959950094 Sep 24 10:15:45 AM UTC 24 Sep 24 10:16:57 AM UTC 24 19910510660 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2859530200 Sep 24 10:16:52 AM UTC 24 Sep 24 10:17:00 AM UTC 24 728436852 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.919886503 Sep 24 10:04:20 AM UTC 24 Sep 24 10:17:35 AM UTC 24 21641813961 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.72693618 Sep 24 10:17:01 AM UTC 24 Sep 24 10:17:47 AM UTC 24 4755360582 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2020746155 Sep 24 10:17:48 AM UTC 24 Sep 24 10:17:50 AM UTC 24 115836541 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.12002077 Sep 24 10:07:45 AM UTC 24 Sep 24 10:17:58 AM UTC 24 3628449187 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1534891839 Sep 24 10:12:03 AM UTC 24 Sep 24 10:18:07 AM UTC 24 28789386016 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3517072538 Sep 24 10:01:44 AM UTC 24 Sep 24 10:18:12 AM UTC 24 19990373581 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1928658838 Sep 24 10:17:51 AM UTC 24 Sep 24 10:18:17 AM UTC 24 1358979232 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.101283445 Sep 24 10:16:57 AM UTC 24 Sep 24 10:18:32 AM UTC 24 5306261868 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1358862355 Sep 24 09:49:08 AM UTC 24 Sep 24 10:18:43 AM UTC 24 268932950667 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1640577965 Sep 24 10:18:18 AM UTC 24 Sep 24 10:18:56 AM UTC 24 1463814741 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4237284243 Sep 24 10:07:40 AM UTC 24 Sep 24 10:19:16 AM UTC 24 6059856990 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2769730965 Sep 24 10:19:17 AM UTC 24 Sep 24 10:19:45 AM UTC 24 14517347147 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2122231972 Sep 24 10:18:45 AM UTC 24 Sep 24 10:20:12 AM UTC 24 1542715056 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1275606555 Sep 24 10:18:57 AM UTC 24 Sep 24 10:20:30 AM UTC 24 3122910482 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3783578192 Sep 24 10:00:29 AM UTC 24 Sep 24 10:20:32 AM UTC 24 171200917055 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.4058178552 Sep 24 10:20:32 AM UTC 24 Sep 24 10:20:39 AM UTC 24 1525078856 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3828776404 Sep 24 10:14:29 AM UTC 24 Sep 24 10:20:40 AM UTC 24 19890076231 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1933314515 Sep 24 09:55:36 AM UTC 24 Sep 24 10:20:58 AM UTC 24 16117969119 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3298641593 Sep 24 10:21:00 AM UTC 24 Sep 24 10:21:20 AM UTC 24 355398408 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1936357085 Sep 24 10:01:42 AM UTC 24 Sep 24 10:22:03 AM UTC 24 78371421488 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2187768330 Sep 24 09:49:08 AM UTC 24 Sep 24 10:22:03 AM UTC 24 187277212559 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2004516059 Sep 24 10:22:04 AM UTC 24 Sep 24 10:22:06 AM UTC 24 14080561 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2356482604 Sep 24 10:20:40 AM UTC 24 Sep 24 10:22:26 AM UTC 24 23881614236 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1066947229 Sep 24 10:22:04 AM UTC 24 Sep 24 10:22:33 AM UTC 24 881386267 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.958195145 Sep 24 10:16:30 AM UTC 24 Sep 24 10:23:57 AM UTC 24 117581632036 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.3702736513 Sep 24 09:51:32 AM UTC 24 Sep 24 10:24:01 AM UTC 24 25278456414 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3247465198 Sep 24 10:18:13 AM UTC 24 Sep 24 10:24:14 AM UTC 24 6848681824 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1385617007 Sep 24 10:23:58 AM UTC 24 Sep 24 10:24:28 AM UTC 24 600949381 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.499517853 Sep 24 09:51:32 AM UTC 24 Sep 24 10:24:55 AM UTC 24 119422169847 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3232266475 Sep 24 10:22:34 AM UTC 24 Sep 24 10:25:24 AM UTC 24 3099786502 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2840252626 Sep 24 10:24:57 AM UTC 24 Sep 24 10:25:26 AM UTC 24 6794123520 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.4209740643 Sep 24 10:16:55 AM UTC 24 Sep 24 10:25:26 AM UTC 24 21128501619 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.204170871 Sep 24 09:56:45 AM UTC 24 Sep 24 10:25:30 AM UTC 24 45405056030 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2265719590 Sep 24 10:24:15 AM UTC 24 Sep 24 10:25:30 AM UTC 24 751555482 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1944497289 Sep 24 09:49:40 AM UTC 24 Sep 24 10:25:35 AM UTC 24 39119497456 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2226762819 Sep 24 10:25:30 AM UTC 24 Sep 24 10:25:38 AM UTC 24 350933420 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1488829352 Sep 24 10:20:39 AM UTC 24 Sep 24 10:25:45 AM UTC 24 93947145328 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.898753711 Sep 24 10:24:28 AM UTC 24 Sep 24 10:25:47 AM UTC 24 827960437 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1558248024 Sep 24 10:15:15 AM UTC 24 Sep 24 10:25:49 AM UTC 24 90906742811 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1252254140 Sep 24 10:25:48 AM UTC 24 Sep 24 10:25:50 AM UTC 24 13376076 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1397431487 Sep 24 10:11:35 AM UTC 24 Sep 24 10:25:59 AM UTC 24 16559134605 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.966051293 Sep 24 10:15:54 AM UTC 24 Sep 24 10:26:16 AM UTC 24 10069623640 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.4170039977 Sep 24 09:50:14 AM UTC 24 Sep 24 10:26:33 AM UTC 24 31856928072 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2667164942 Sep 24 10:25:38 AM UTC 24 Sep 24 10:26:35 AM UTC 24 700976613 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4240819301 Sep 24 10:26:34 AM UTC 24 Sep 24 10:27:16 AM UTC 24 3048179396 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.2693464618 Sep 24 10:20:12 AM UTC 24 Sep 24 10:27:43 AM UTC 24 13251502101 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1445743388 Sep 24 10:25:49 AM UTC 24 Sep 24 10:27:59 AM UTC 24 1585343443 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1945166172 Sep 24 10:27:44 AM UTC 24 Sep 24 10:28:00 AM UTC 24 2801960270 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3476156837 Sep 24 10:17:59 AM UTC 24 Sep 24 10:28:02 AM UTC 24 13701787059 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4032718703 Sep 24 10:24:01 AM UTC 24 Sep 24 10:28:05 AM UTC 24 7229843445 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3332989126 Sep 24 10:18:32 AM UTC 24 Sep 24 10:28:26 AM UTC 24 80685446346 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2114679504 Sep 24 10:28:27 AM UTC 24 Sep 24 10:28:34 AM UTC 24 1411834201 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.152832022 Sep 24 10:27:17 AM UTC 24 Sep 24 10:28:54 AM UTC 24 778194768 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.295790413 Sep 24 10:25:25 AM UTC 24 Sep 24 10:29:12 AM UTC 24 13173787485 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3945419066 Sep 24 10:29:13 AM UTC 24 Sep 24 10:29:23 AM UTC 24 688220109 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.892598206 Sep 24 10:25:36 AM UTC 24 Sep 24 10:29:26 AM UTC 24 69565768368 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4242794302 Sep 24 10:29:26 AM UTC 24 Sep 24 10:29:28 AM UTC 24 38730251 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3832600519 Sep 24 10:28:01 AM UTC 24 Sep 24 10:29:53 AM UTC 24 9755418568 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.583289819 Sep 24 10:29:30 AM UTC 24 Sep 24 10:30:01 AM UTC 24 2619750258 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1419528788 Sep 24 10:26:17 AM UTC 24 Sep 24 10:30:28 AM UTC 24 32317240198 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.1995962191 Sep 24 10:10:06 AM UTC 24 Sep 24 10:31:19 AM UTC 24 180083815758 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.4238483121 Sep 24 10:28:55 AM UTC 24 Sep 24 10:31:33 AM UTC 24 5068084961 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2493463853 Sep 24 10:20:30 AM UTC 24 Sep 24 10:31:40 AM UTC 24 25630922748 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3910874133 Sep 24 10:14:20 AM UTC 24 Sep 24 10:31:53 AM UTC 24 44392078197 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2185257373 Sep 24 10:13:05 AM UTC 24 Sep 24 10:32:55 AM UTC 24 55488200464 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3745565896 Sep 24 10:31:54 AM UTC 24 Sep 24 10:32:58 AM UTC 24 1572414355 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.715057238 Sep 24 09:49:40 AM UTC 24 Sep 24 10:33:10 AM UTC 24 247010986515 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3381373440 Sep 24 10:31:19 AM UTC 24 Sep 24 10:33:12 AM UTC 24 5035109963 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.757224251 Sep 24 10:18:08 AM UTC 24 Sep 24 10:33:14 AM UTC 24 93327214617 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1454742554 Sep 24 10:33:14 AM UTC 24 Sep 24 10:33:19 AM UTC 24 678995452 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.124679419 Sep 24 10:32:56 AM UTC 24 Sep 24 10:33:28 AM UTC 24 13885127370 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.68566876 Sep 24 10:31:42 AM UTC 24 Sep 24 10:33:29 AM UTC 24 1410202985 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2340377323 Sep 24 10:26:36 AM UTC 24 Sep 24 10:33:33 AM UTC 24 44399062434 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4134839696 Sep 24 10:28:35 AM UTC 24 Sep 24 10:33:54 AM UTC 24 15151078531 ps