Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	146824080	1			T4	649		T5	2011		T8	1761
triple_byte_access	2850966	1			T4	7		T5	95		T8	1589
halfword_access	4376251	1			T4	21		T5	148		T8	2417
byte_access	6118639	1			T4	24		T5	171		T8	3188
zero_access	1856848	1			T4	5		T5	40		T8	749

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80678632

1

T4

332

T5

1278

T8

4850

auto[1]

81348152

1

T4

374

T5

1187

T8

4854

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72935707	1			T4	310		T5	1047		T8	859
auto[0]	triple_byte_access	1360256	1			T4	3		T5	51		T8	793
auto[0]	halfword_access	2138008	1			T4	9		T5	64		T8	1201
auto[0]	byte_access	3133724	1			T4	9		T5	91		T8	1594
auto[0]	zero_access	1110937	1			T4	1		T5	25		T8	403
auto[1]	word_access	73888373	1			T4	339		T5	964		T8	902
auto[1]	triple_byte_access	1490710	1			T4	4		T5	44		T8	796
auto[1]	halfword_access	2238243	1			T4	12		T5	84		T8	1216
auto[1]	byte_access	2984915	1			T4	15		T5	80		T8	1594
auto[1]	zero_access	745911	1			T4	4		T5	15		T8	346