Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	322359156	1			T2	32		T3	358		T4	1866
instr_valid_dis	286489177	1			T2	32		T3	358		T4	1866
instr_en	23253067	1			T28	7756		T20	7742		T27	39412

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17071822	1			T28	12500		T19	49050		T27	20778
sram_ifetch_valid_disable	279708674	1			T2	32		T3	358		T4	1866
sram_ifetch_enable	25578660	1			T19	20500		T20	52		T27	18634

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	322359156	1			T2	32		T3	358		T4	1866
hw_debug_en_valid_off	280648386	1			T2	32		T3	358		T4	1866
hw_debug_en_on	28321362	1			T19	71576		T20	30578		T116	17542

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	279708674	1			T2	32		T3	358		T4	1866
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	265843737	1			T2	32		T3	358		T4	1866
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8724603	1			T28	64		T20	7690		T116	70
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7001812	1			T28	7692		T27	20778		T116	23290
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3974026	1			T117	32846		T156	106618		T155	25100
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2243794	1			T28	7692		T27	20778		T116	23290
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5169270	1			T19	49050		T116	17472		T117	82756
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2066034	1			T117	82756		T131	6538		T153	11876
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2056168	1			T116	17472		T148	20096		T156	14768
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11827328	1			T19	2070		T20	30526		T116	70
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6213070	1			T20	30526		T117	16254		T21	12060
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3605292	1			T116	70		T21	17544		T149	66512

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9658238	1			T20	52		T27	18634		T116	12794
lc_exec_en	11324764	1			T19	20456		T20	52		T117	19194
valid_exec_dis	274310442	1			T2	32		T3	358		T4	1866
invalid_exec_dis	42650482	1			T28	12500		T19	69550		T20	52