Name |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.444408866 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342138767 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.66505225 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3490424267 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.185598413 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1444967382 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2945805891 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1436522902 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1725555156 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.633697829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2795727419 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.346917829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522519105 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2612045579 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4142240092 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1664045756 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2593753278 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1762106153 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.542465941 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3714788462 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3177054894 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.975959635 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.786648023 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4290190131 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1020272231 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1403899382 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.172364888 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.698272590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2988684294 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.663380637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2776185276 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1501573595 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.332501784 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3535731994 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3166130129 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3423210803 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3014407543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.801490166 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3023043768 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.711406482 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1827521790 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3086479478 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1934130237 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2670516995 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.201060318 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3435324028 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1157331322 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.493414515 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930512184 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4273413318 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2526903326 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2680605891 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.472497417 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3515221320 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1303043395 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.548855785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2136877368 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1045016175 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2759402331 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1463450069 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.778259131 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2665283611 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3834701720 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2903193145 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1857461230 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.551507700 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2591074668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.961219410 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1145480147 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.274070381 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.262814051 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2387003505 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3856646672 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967025671 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506167649 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.485777188 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1207405401 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.936308777 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.794717033 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4012557481 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1876484718 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1966248864 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3405468819 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3799817957 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2364689593 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3323368548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.98120302 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.33748730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.653830701 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1528791809 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3454854929 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.799292030 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3560467562 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3900259730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.662068324 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4140165279 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2818885844 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3127319775 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3177565683 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4077131044 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3689666415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.9365998 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3013479674 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1342321632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2350843688 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031886717 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2222352368 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1960157127 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4214918514 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3487167937 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1656703668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2539730377 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1849677083 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3829518795 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2150492146 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3617171327 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3279829348 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.641867704 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1473998776 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.100702783 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4214343831 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.996520004 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1776798575 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2807990673 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.258615662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1844218162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1742890441 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4276213026 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1626289764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3530834705 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2282395184 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2229183779 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.72831962 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1194272685 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1182091038 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.509798039 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4226918557 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2215319090 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2271090737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.429093585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1485622681 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1460314068 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2735680643 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3547276451 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1480811772 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3874894012 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.425686627 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2887613022 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.908273339 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3728139455 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.287419000 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4244781600 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3808193801 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1310989693 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1843202599 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1326716023 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.300456195 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2907349371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2130510162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2521226017 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3721437915 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.360119199 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1763505270 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3453964077 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.7243817 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3941846072 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1783370739 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2483527736 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.214999265 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1367871855 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.800772115 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.215601656 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.389958660 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1333881911 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.216907803 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3339522565 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3999807848 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.59803490 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3952240373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1554831239 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.995908162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2289936234 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1558211726 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1316681245 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1320975146 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.578240824 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1833143634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4202054845 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1242670508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3898127958 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.2886136997 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3011745003 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.586327430 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1416675056 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3463892041 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3976511537 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1579133551 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.411849161 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.684842096 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.362467284 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.4102975167 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2129784000 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1335192402 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2543470674 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2398749048 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2253745935 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2995378392 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2526888090 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2030149913 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.4079991298 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2798199769 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2831418845 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.20415957 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.468359913 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3531276263 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1001821560 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2924352275 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2393726410 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.117732389 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.842678599 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2779796125 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1160191942 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1649442416 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2913826520 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.440465668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1124366861 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.85794617 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.532888122 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3385612647 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1778370040 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2005508148 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2721987334 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2340624646 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4086072939 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.4242735391 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2083880543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.877500881 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3083576266 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.313672549 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1719803694 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2717859132 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2649008347 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2950748727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3262266412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1378842234 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.3615066568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.957155290 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.975568144 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3305077396 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1539261755 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1506643624 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1658361054 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.580191563 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2668434341 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2423267363 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.133891580 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1335826320 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.4085129634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1763937315 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3606569395 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3035264724 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3338152190 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2574504958 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.855530677 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1713912020 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.482396729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3897380148 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.723440151 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.844535966 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1156649936 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2216316117 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2588490324 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1674369479 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.632026948 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3424623039 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.2493175647 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.1939743350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.699748128 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.248464205 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3754327568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4235117709 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.880770559 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3700291158 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3434899781 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.636099460 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3819679222 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3760646217 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2220081032 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1919714224 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.38771028 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1168837789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1510502078 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1444777990 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1147331785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1211367215 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2309966342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2028511621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4205249403 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3648630840 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.928331534 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2984351512 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3217654851 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.846022014 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2883655923 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.2413425435 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.956717682 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3997742629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4248014912 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.968311077 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.759891078 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3787762848 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3569946963 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.2711303968 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2438450101 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1158813598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2120839005 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2782252316 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.441279415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.409265706 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1705211472 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.639291973 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.590645392 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2579481883 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.2906621060 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3405265143 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3312934865 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3203865979 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2049986303 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3323164731 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.481774887 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.773652763 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1132590672 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2637899157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3663871360 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2417804192 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.129534516 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.796134371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4222881967 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4159460942 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4283046853 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3135281578 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.2123330939 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4056931932 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.132199132 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4234508975 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1054484584 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.401057634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1998260157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.130295527 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2511671178 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.570724847 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3562119719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2690699980 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.642706699 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2546872207 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3631977955 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2394780541 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3460181885 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.639400113 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2926178196 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.837600444 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1459144460 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2855518390 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2951790352 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4269405207 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3489415227 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.318925373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3398764863 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2870036264 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.22868925 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.579188301 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.388759586 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.893076762 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.4152416493 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.229873568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.56441068 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1273295806 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.498604025 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.848570896 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3488889629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.4246513808 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3656125894 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1529461621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3902300523 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1603865637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1064801051 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3526848623 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.512146617 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1446347906 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1231782179 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3675266050 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1766860441 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.434158181 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.3470870361 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2600152609 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2881893982 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.926147183 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1250213904 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1080803819 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.189808237 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.536802619 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3419369423 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1564200039 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3637964955 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.689851467 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.151511993 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.1200654183 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3904633110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1789573997 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2795297381 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2566670984 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.437982412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.400811841 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2394716610 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.387007306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.3897832021 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.598173548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1663360457 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1468538528 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4252304314 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1240849072 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1931837852 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.635198170 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2403116789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1683703536 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2776395206 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2281926948 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2699859185 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3276562162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2741305137 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.4100829727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2135820783 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3984671951 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3753301572 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3584536669 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3330673475 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1795804757 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.67228823 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1404946210 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2313430676 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2233747004 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1058082911 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.184435478 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3622667754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2110402530 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1779018471 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2162925352 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1878511778 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2042497970 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2530433192 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1412570910 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3327045574 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1113482470 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3662995881 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.116183509 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1595192989 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4009889708 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3350173032 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2341905134 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3575016472 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.417228273 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.363915246 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.342284185 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4193998893 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4002278828 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1941018362 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1474279386 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.286707692 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2309232482 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3026747374 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1914971839 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2755881007 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2009411146 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1381179945 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1202577977 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3353551966 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.307761452 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.678849540 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1182688524 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.136279172 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2058770356 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2001003542 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2710515330 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3728233675 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3090925697 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1087361415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3912743858 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3354794623 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.94487761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.306778451 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.3346899986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2902922737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1797324538 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2710724899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.924317494 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1173991535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1618835901 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.578677668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1943173546 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.2188205498 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2311530262 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3205409251 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4120791181 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1800698412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3560623231 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.632432560 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3283685727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3652306790 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3646098517 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.298845608 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.1823971521 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.4182851450 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.688772852 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2232216359 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1073183259 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.4285149667 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.897334263 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1198405241 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3955913221 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2154933570 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1054289384 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2129235477 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3848007094 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2021533337 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3848550342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3403550498 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3283154644 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.3171474523 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.536458107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2104333118 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3403217157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.692877332 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.733572929 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1836795659 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2565815203 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.250880083 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3188903474 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1112682861 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3463013974 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2727192136 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.198687817 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2278033193 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3195779877 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1373814127 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.278106351 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1936897087 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.770043066 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2954513013 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1251042025 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1585971131 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1037886974 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.64999906 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1737640175 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3823727275 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1804783657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.380368191 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2678393214 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2464959211 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2569249349 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2967075645 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1092956437 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1436006205 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.611921754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1278970316 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3149180485 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.164226603 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1895000569 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2664586508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3200845729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.923991621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.119361730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1032689004 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3459763772 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.4138488657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1874963991 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1576237881 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2760517814 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1356418714 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1727709900 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3787384999 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2183345873 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1649188357 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2855248424 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.1106446431 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.670378953 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2026118412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3171852109 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1124173788 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2787915863 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1159612410 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.996499688 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.4274787024 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1930881219 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.1509046141 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2525803711 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.583512719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.4232723190 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1882858838 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2549350737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.263067461 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3548610435 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.376119197 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.1818886353 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.805423266 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.4109032899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.486533654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2172144632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.6453350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3225016313 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.359204632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1919777407 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2251856187 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2933475448 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.510308700 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1181001247 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2858422872 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2812886522 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3618428493 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3199055031 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2111407354 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.504900350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3294537884 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3064769420 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3219890629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2219267637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.625120993 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2750013143 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1859332764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1758705267 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3634997691 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.2723485550 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3544628169 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.742142991 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3875902305 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1361883399 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1788483537 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1014905098 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2708246254 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2856767759 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2709046033 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3236789041 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.3880790098 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3106156186 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1638348512 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3589922072 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2368947348 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1026609293 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.308144309 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3859936220 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1326306754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1504120192 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.73882741 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.773025760 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4133993904 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3790166592 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1009879690 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3742619662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1966978044 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2863260195 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.2960787907 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.4108546863 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1603591627 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2890629895 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3394907761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2528281024 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3812969516 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1291155896 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2598752270 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1894218583 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3822011691 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2415060193 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1086917488 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3708583123 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.927392654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3093800389 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1270585575 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1980729335 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1340623268 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.2691508680 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2321340737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.513261698 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1997724144 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4279945535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1297238049 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1274088659 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3185902739 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1098620306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.633598598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.279666199 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.244714218 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2048280931 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.26158387 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.18732595 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3271270758 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.858819683 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2072429904 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.836752219 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.1767516129 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.584949212 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1672830535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2234875844 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2106686869 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1031219526 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.812729837 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1769960372 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2758806602 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1171391719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.83461853 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3338659762 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.3167772002 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.293454986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.336822329 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2320106785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2968495385 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1151542224 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1040080940 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.2945019264 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.2046519518 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.611984950 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3177317364 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.471150718 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1520854501 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3366686088 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1847990551 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.931724001 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.1362477968 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1596628130 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3671808121 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1688317337 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1005615098 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3060277097 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1759111815 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2816919215 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1154541549 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.161646897 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3360472894 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1998514653 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2174295342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.4202718038 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1890516616 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.684509306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.997028789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3992426185 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1165699368 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3748306087 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1504180187 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3516673829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1885750491 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.87725233 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3240536195 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4209787047 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2669863107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2269940190 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2968825605 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3407397848 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1207474420 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1477304931 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1038200452 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1917866215 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2544911986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1869132638 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1151346067 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1836251456 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4003745428 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.915665676 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3335863876 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3786254585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3822974199 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.302342508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2837883117 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.157623350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2065114304 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2156061733 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.3948427321 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1014979454 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1284224795 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2988926859 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1205324265 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4175815263 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3951949373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4249650996 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1019039527 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3872193919 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.657883982 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.638113460 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3678679007 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3804896859 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.267676206 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2834261817 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1056358002 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2355323237 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.756910418 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2673528667 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.87684620 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2744287405 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1695233650 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1124685772 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.79520722 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.113878496 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3868898655 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3459856486 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2257307969 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.1665411784 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1599021954 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1450432100 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2138106018 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.22161991 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.842142590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2567050048 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3401807274 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2030048996 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1340456810 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.3405957729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3379375041 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.398905608 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3330091172 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.220430754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2786018045 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4098151837 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1681823671 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1835164265 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2821985376 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.2993506959 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1732126763 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.72736007 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.756726612 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1826301210 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3612598883 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2694724107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3806750539 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3223745577 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.3209782482 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.4291718489 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.1403482362 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.156226079 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4092870082 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2519306418 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1621302430 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1000771346 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.550663054 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2325978776 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1413053780 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.390652218 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.21041106 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.545929615 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3042602366 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1189456745 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.683666181 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3173116738 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1966118642 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.2424740751 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2188381488 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1779714247 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.660291439 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.459642097 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2346447156 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4276216722 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.275633400 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.4104175655 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.807486102 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3303669103 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2152922696 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.668250506 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.720858282 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3603611355 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2456854970 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3006336381 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.563190585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.1230108558 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.921093964 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3701548113 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1859053481 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1772613022 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1101215908 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2018419211 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.931561910 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.674624412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.953387634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.114040590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2999667168 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3221827465 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1993157260 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.523255023 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3821577752 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.45308054 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.22274118 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3294312764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.2312471668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.299831337 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.606668157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.649452088 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1707142398 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.988894940 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.583568654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3980954369 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.131015969 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2348405927 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.991090448 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2283033110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1324476968 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2306944629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2595039977 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1890043045 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.869208474 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3053592033 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4142994899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1269560227 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2947355729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.754871598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1856152264 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2886516511 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.499101992 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1776081459 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.361109548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3428617692 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.70100184 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4183119982 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3723766400 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2734508985 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1234192158 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3543298604 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.654865849 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3841419819 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.995696338 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.4090979619 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.943508996 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2382765651 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3886708632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1030232110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2419862614 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.714589178 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1794036002 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1490105829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3778103061 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1876107218 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2390780657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.4093647971 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1480880893 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2426932930 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3824773961 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1161802502 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1102442136 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.628607210 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.3874056540 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1095189445 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3127873941 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3413685763 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1500634533 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3228700974 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2209247486 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1965953983 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2788024379 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.13875915 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1891860200 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.751329908 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1921043832 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2248060238 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3616892283 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3915451418 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2824511584 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3714813981 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3549328961 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.2959382033 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.526142273 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2240432899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2194267747 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2079361131 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2092355519 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1782967975 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2961102422 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3724837730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.4105989371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3326966853 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.973228267 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.55431582 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1365564677 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1804362828 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.813284771 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2415141703 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1402369150 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2098904662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.1941498384 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2860762191 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3177778456 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.269686024 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231165320 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3184968903 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4214074628 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2866813901 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1004753402 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.938362602 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3831728335 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3209093615 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1422697318 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2109003361 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2525218107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3798247600 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1573591543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2223397544 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.50887118 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.3201485217 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1517123580 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1566626219 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.298665005 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.626491335 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.224349654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1952137761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3004734564 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.718499139 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.203248631 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3603311040 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3876987801 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3578489964 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.248428525 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3199652138 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3798146143 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1582504142 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1263139711 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1159052433 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1149758786 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3415686705 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.638499784 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761903578 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1782205678 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4102738045 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3739291750 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1108290130 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.956624679 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3788334981 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.908649972 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1387045645 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3729148986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3388787233 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4234339299 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3688918730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1161397954 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.595168857 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.4061901889 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857385962 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1291823145 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.644684306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1008002943 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1195559760 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1711588505 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1680074195 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2752637883 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1126153787 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1259410546 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3643126785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3768267969 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1382039825 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1222136330 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3488715569 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2446269650 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4134330935 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3144713485 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.794618529 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.191326471 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3427789958 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.200439499 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:18:11 PM UTC 24 |
1344870878 ps |
T2 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.105053325 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:18:18 PM UTC 24 |
668688209 ps |
T3 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1182091038 |
|
|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:18:18 PM UTC 24 |
4255414477 ps |
T12 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1361126443 |
|
|
Oct 09 12:18:18 PM UTC 24 |
Oct 09 12:18:20 PM UTC 24 |
44029510 ps |
T4 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2215319090 |
|
|
Oct 09 12:18:12 PM UTC 24 |
Oct 09 12:18:23 PM UTC 24 |
1277405717 ps |
T6 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2271090737 |
|
|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:18:30 PM UTC 24 |
1473680137 ps |
T10 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1843202599 |
|
|
Oct 09 12:18:18 PM UTC 24 |
Oct 09 12:18:31 PM UTC 24 |
715479478 ps |
T11 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1485622681 |
|
|
Oct 09 12:18:04 PM UTC 24 |
Oct 09 12:18:36 PM UTC 24 |
1490977026 ps |
T13 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3874894012 |
|
|
Oct 09 12:18:32 PM UTC 24 |
Oct 09 12:18:48 PM UTC 24 |
714923100 ps |
T5 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3225264152 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:18:54 PM UTC 24 |
17395898918 ps |
T23 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.287419000 |
|
|
Oct 09 12:18:54 PM UTC 24 |
Oct 09 12:19:00 PM UTC 24 |
698450352 ps |
T28 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1379979564 |
|
|
Oct 09 12:18:52 PM UTC 24 |
Oct 09 12:19:31 PM UTC 24 |
1155510832 ps |
T32 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3728139455 |
|
|
Oct 09 12:18:24 PM UTC 24 |
Oct 09 12:19:41 PM UTC 24 |
5283020397 ps |
T16 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4244781600 |
|
|
Oct 09 12:19:32 PM UTC 24 |
Oct 09 12:19:44 PM UTC 24 |
1354556664 ps |
T36 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2229183779 |
|
|
Oct 09 12:18:04 PM UTC 24 |
Oct 09 12:20:06 PM UTC 24 |
807529253 ps |
T7 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1284224795 |
|
|
Oct 09 12:27:58 PM UTC 24 |
Oct 09 12:28:05 PM UTC 24 |
2567318362 ps |
T18 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1310989693 |
|
|
Oct 09 12:20:07 PM UTC 24 |
Oct 09 12:20:11 PM UTC 24 |
348299421 ps |
T24 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.300456195 |
|
|
Oct 09 12:19:42 PM UTC 24 |
Oct 09 12:20:12 PM UTC 24 |
627712860 ps |
T14 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2735680643 |
|
|
Oct 09 12:20:11 PM UTC 24 |
Oct 09 12:20:13 PM UTC 24 |
41164389 ps |
T37 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2130510162 |
|
|
Oct 09 12:18:33 PM UTC 24 |
Oct 09 12:20:20 PM UTC 24 |
1615659000 ps |
T38 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1459144460 |
|
|
Oct 09 12:20:11 PM UTC 24 |
Oct 09 12:20:33 PM UTC 24 |
3092661494 ps |
T8 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1480811772 |
|
|
Oct 09 12:18:37 PM UTC 24 |
Oct 09 12:20:38 PM UTC 24 |
51932102234 ps |
T68 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3460181885 |
|
|
Oct 09 12:20:21 PM UTC 24 |
Oct 09 12:20:55 PM UTC 24 |
1504742146 ps |
T19 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3808193801 |
|
|
Oct 09 12:18:53 PM UTC 24 |
Oct 09 12:21:18 PM UTC 24 |
11786924899 ps |
T62 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2907349371 |
|
|
Oct 09 12:18:21 PM UTC 24 |
Oct 09 12:21:27 PM UTC 24 |
3157435444 ps |
T69 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4269405207 |
|
|
Oct 09 12:20:55 PM UTC 24 |
Oct 09 12:21:32 PM UTC 24 |
730661328 ps |
T42 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1724692259 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:21:38 PM UTC 24 |
41724939028 ps |
T29 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2926178196 |
|
|
Oct 09 12:21:40 PM UTC 24 |
Oct 09 12:21:48 PM UTC 24 |
1168807675 ps |
T54 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.425686627 |
|
|
Oct 09 12:19:25 PM UTC 24 |
Oct 09 12:21:58 PM UTC 24 |
4495173377 ps |
T9 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2690699980 |
|
|
Oct 09 12:21:19 PM UTC 24 |
Oct 09 12:22:08 PM UTC 24 |
13291290009 ps |
T17 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.837600444 |
|
|
Oct 09 12:21:58 PM UTC 24 |
Oct 09 12:22:08 PM UTC 24 |
2761677286 ps |
T15 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2511671178 |
|
|
Oct 09 12:22:09 PM UTC 24 |
Oct 09 12:22:11 PM UTC 24 |
44009613 ps |
T55 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.642706699 |
|
|
Oct 09 12:20:39 PM UTC 24 |
Oct 09 12:22:12 PM UTC 24 |
1585600628 ps |
T30 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.7590283 |
|
|
Oct 09 12:22:09 PM UTC 24 |
Oct 09 12:22:13 PM UTC 24 |
1049891357 ps |
T43 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.72831962 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:22:20 PM UTC 24 |
10904464098 ps |
T56 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2664586508 |
|
|
Oct 09 12:22:12 PM UTC 24 |
Oct 09 12:22:25 PM UTC 24 |
723709069 ps |
T165 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1436006205 |
|
|
Oct 09 12:22:25 PM UTC 24 |
Oct 09 12:22:39 PM UTC 24 |
2108722915 ps |
T20 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512464987 |
|
|
Oct 09 12:21:35 PM UTC 24 |
Oct 09 12:22:41 PM UTC 24 |
8294797473 ps |
T164 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2464959211 |
|
|
Oct 09 12:22:42 PM UTC 24 |
Oct 09 12:23:06 PM UTC 24 |
706073771 ps |
T44 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2546872207 |
|
|
Oct 09 12:21:56 PM UTC 24 |
Oct 09 12:23:20 PM UTC 24 |
1391155342 ps |
T25 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3934216209 |
|
|
Oct 09 12:21:59 PM UTC 24 |
Oct 09 12:23:41 PM UTC 24 |
7539121219 ps |
T63 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2675997623 |
|
|
Oct 09 12:18:31 PM UTC 24 |
Oct 09 12:23:42 PM UTC 24 |
23366766525 ps |
T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.119361730 |
|
|
Oct 09 12:23:07 PM UTC 24 |
Oct 09 12:23:54 PM UTC 24 |
1517374517 ps |
T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2951790352 |
|
|
Oct 09 12:20:16 PM UTC 24 |
Oct 09 12:23:57 PM UTC 24 |
3248076497 ps |
T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1278970316 |
|
|
Oct 09 12:23:56 PM UTC 24 |
Oct 09 12:24:03 PM UTC 24 |
354938472 ps |
T51 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2887613022 |
|
|
Oct 09 12:19:01 PM UTC 24 |
Oct 09 12:24:19 PM UTC 24 |
5361645068 ps |
T106 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.509798039 |
|
|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:24:23 PM UTC 24 |
27880864331 ps |
T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3149180485 |
|
|
Oct 09 12:24:20 PM UTC 24 |
Oct 09 12:24:30 PM UTC 24 |
662736941 ps |
T130 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3823727275 |
|
|
Oct 09 12:24:33 PM UTC 24 |
Oct 09 12:24:35 PM UTC 24 |
14574048 ps |
T31 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1895000569 |
|
|
Oct 09 12:24:31 PM UTC 24 |
Oct 09 12:24:36 PM UTC 24 |
439616620 ps |
T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2988926859 |
|
|
Oct 09 12:24:36 PM UTC 24 |
Oct 09 12:24:58 PM UTC 24 |
859939052 ps |
T22 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2678393214 |
|
|
Oct 09 12:23:11 PM UTC 24 |
Oct 09 12:25:15 PM UTC 24 |
29501912290 ps |
T26 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2307627702 |
|
|
Oct 09 12:24:20 PM UTC 24 |
Oct 09 12:25:18 PM UTC 24 |
6833649015 ps |
T47 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2569249349 |
|
|
Oct 09 12:24:04 PM UTC 24 |
Oct 09 12:25:41 PM UTC 24 |
2842468241 ps |
T166 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3786254585 |
|
|
Oct 09 12:26:01 PM UTC 24 |
Oct 09 12:26:15 PM UTC 24 |
1342018805 ps |
T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.157623350 |
|
|
Oct 09 12:25:19 PM UTC 24 |
Oct 09 12:26:18 PM UTC 24 |
3346280135 ps |
T27 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.380368191 |
|
|
Oct 09 12:23:41 PM UTC 24 |
Oct 09 12:26:23 PM UTC 24 |
3612352775 ps |
T107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.639400113 |
|
|
Oct 09 12:20:34 PM UTC 24 |
Oct 09 12:26:33 PM UTC 24 |
13238263363 ps |
T39 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1151346067 |
|
|
Oct 09 12:26:24 PM UTC 24 |
Oct 09 12:26:36 PM UTC 24 |
4791380903 ps |
T147 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3335863876 |
|
|
Oct 09 12:26:19 PM UTC 24 |
Oct 09 12:26:44 PM UTC 24 |
9769813172 ps |
T168 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2156061733 |
|
|
Oct 09 12:26:45 PM UTC 24 |
Oct 09 12:26:50 PM UTC 24 |
347178361 ps |
T169 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4249650996 |
|
|
Oct 09 12:26:17 PM UTC 24 |
Oct 09 12:27:17 PM UTC 24 |
3226439813 ps |
T40 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1737640175 |
|
|
Oct 09 12:23:20 PM UTC 24 |
Oct 09 12:27:20 PM UTC 24 |
5105583896 ps |
T170 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.3948427321 |
|
|
Oct 09 12:27:21 PM UTC 24 |
Oct 09 12:27:34 PM UTC 24 |
676211132 ps |
T52 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3631977955 |
|
|
Oct 09 12:21:48 PM UTC 24 |
Oct 09 12:27:48 PM UTC 24 |
24692066817 ps |
T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.429093585 |
|
|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:27:57 PM UTC 24 |
121517560777 ps |
T171 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1836251456 |
|
|
Oct 09 12:28:06 PM UTC 24 |
Oct 09 12:28:08 PM UTC 24 |
58477386 ps |
T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4175815263 |
|
|
Oct 09 12:27:35 PM UTC 24 |
Oct 09 12:28:10 PM UTC 24 |
3474828473 ps |
T109 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.611921754 |
|
|
Oct 09 12:22:41 PM UTC 24 |
Oct 09 12:29:05 PM UTC 24 |
19799078798 ps |
T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3177778456 |
|
|
Oct 09 12:28:09 PM UTC 24 |
Oct 09 12:29:06 PM UTC 24 |
5684793157 ps |
T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3822974199 |
|
|
Oct 09 12:27:17 PM UTC 24 |
Oct 09 12:29:08 PM UTC 24 |
10156687343 ps |
T173 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2415141703 |
|
|
Oct 09 12:29:08 PM UTC 24 |
Oct 09 12:29:34 PM UTC 24 |
1090463814 ps |
T45 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.302342508 |
|
|
Oct 09 12:26:50 PM UTC 24 |
Oct 09 12:29:46 PM UTC 24 |
10440674728 ps |
T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.55431582 |
|
|
Oct 09 12:29:35 PM UTC 24 |
Oct 09 12:29:50 PM UTC 24 |
695579924 ps |
T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4214074628 |
|
|
Oct 09 12:29:46 PM UTC 24 |
Oct 09 12:30:41 PM UTC 24 |
3223158264 ps |
T46 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2967075645 |
|
|
Oct 09 12:23:58 PM UTC 24 |
Oct 09 12:30:44 PM UTC 24 |
44055972087 ps |
T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2098904662 |
|
|
Oct 09 12:31:13 PM UTC 24 |
Oct 09 12:31:20 PM UTC 24 |
693392501 ps |
T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.923991621 |
|
|
Oct 09 12:22:21 PM UTC 24 |
Oct 09 12:31:00 PM UTC 24 |
6192072089 ps |
T41 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.130295527 |
|
|
Oct 09 12:21:29 PM UTC 24 |
Oct 09 12:31:12 PM UTC 24 |
25501042507 ps |
T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3951949373 |
|
|
Oct 09 12:25:16 PM UTC 24 |
Oct 09 12:31:21 PM UTC 24 |
16560209151 ps |
T85 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1626289764 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:31:41 PM UTC 24 |
76842917087 ps |
T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.973228267 |
|
|
Oct 09 12:29:51 PM UTC 24 |
Oct 09 12:31:44 PM UTC 24 |
11774221752 ps |
T162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.1941498384 |
|
|
Oct 09 12:31:42 PM UTC 24 |
Oct 09 12:31:55 PM UTC 24 |
691842221 ps |
T64 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231165320 |
|
|
Oct 09 12:31:45 PM UTC 24 |
Oct 09 12:32:01 PM UTC 24 |
1092816881 ps |
T177 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3724837730 |
|
|
Oct 09 12:32:03 PM UTC 24 |
Oct 09 12:32:05 PM UTC 24 |
21925754 ps |
T178 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2394780541 |
|
|
Oct 09 12:20:13 PM UTC 24 |
Oct 09 12:32:26 PM UTC 24 |
9602277989 ps |
T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1566626219 |
|
|
Oct 09 12:32:06 PM UTC 24 |
Oct 09 12:32:45 PM UTC 24 |
745103650 ps |
T116 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2860762191 |
|
|
Oct 09 12:31:02 PM UTC 24 |
Oct 09 12:32:52 PM UTC 24 |
757596863 ps |
T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2065114304 |
|
|
Oct 09 12:25:41 PM UTC 24 |
Oct 09 12:33:15 PM UTC 24 |
6763006718 ps |
T117 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4226918557 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:33:20 PM UTC 24 |
2836043401 ps |
T181 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.908273339 |
|
|
Oct 09 12:18:19 PM UTC 24 |
Oct 09 12:33:31 PM UTC 24 |
21495972629 ps |
T21 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1205324265 |
|
|
Oct 09 12:27:49 PM UTC 24 |
Oct 09 12:33:39 PM UTC 24 |
15492939533 ps |
T149 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2282395184 |
|
|
Oct 09 12:18:05 PM UTC 24 |
Oct 09 12:33:40 PM UTC 24 |
16997138524 ps |
T182 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1573591543 |
|
|
Oct 09 12:32:53 PM UTC 24 |
Oct 09 12:33:50 PM UTC 24 |
5030542924 ps |
T183 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3184968903 |
|
|
Oct 09 12:29:06 PM UTC 24 |
Oct 09 12:33:53 PM UTC 24 |
8504304755 ps |
T148 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1014979454 |
|
|
Oct 09 12:26:37 PM UTC 24 |
Oct 09 12:34:00 PM UTC 24 |
2891553308 ps |
T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.50887118 |
|
|
Oct 09 12:33:54 PM UTC 24 |
Oct 09 12:34:02 PM UTC 24 |
354251740 ps |
T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1460314068 |
|
|
Oct 09 12:18:50 PM UTC 24 |
Oct 09 12:34:02 PM UTC 24 |
50357122510 ps |
T185 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.3201485217 |
|
|
Oct 09 12:34:04 PM UTC 24 |
Oct 09 12:34:16 PM UTC 24 |
2554178008 ps |
T95 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1365564677 |
|
|
Oct 09 12:31:22 PM UTC 24 |
Oct 09 12:34:23 PM UTC 24 |
5106590740 ps |
T186 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1804362828 |
|
|
Oct 09 12:31:21 PM UTC 24 |
Oct 09 12:34:36 PM UTC 24 |
7195665555 ps |
T187 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1004753402 |
|
|
Oct 09 12:34:37 PM UTC 24 |
Oct 09 12:34:39 PM UTC 24 |
13544567 ps |
T188 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3209093615 |
|
|
Oct 09 12:33:40 PM UTC 24 |
Oct 09 12:34:55 PM UTC 24 |
38667472823 ps |
T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3415686705 |
|
|
Oct 09 12:34:40 PM UTC 24 |
Oct 09 12:35:06 PM UTC 24 |
1648632022 ps |
T190 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1422697318 |
|
|
Oct 09 12:33:21 PM UTC 24 |
Oct 09 12:35:07 PM UTC 24 |
781749687 ps |
T191 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1952137761 |
|
|
Oct 09 12:33:32 PM UTC 24 |
Oct 09 12:35:08 PM UTC 24 |
828627925 ps |
T192 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2837883117 |
|
|
Oct 09 12:24:37 PM UTC 24 |
Oct 09 12:35:08 PM UTC 24 |
20198579725 ps |
T96 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2109003361 |
|
|
Oct 09 12:34:02 PM UTC 24 |
Oct 09 12:35:22 PM UTC 24 |
4911356263 ps |
T193 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1582504142 |
|
|
Oct 09 12:35:08 PM UTC 24 |
Oct 09 12:35:30 PM UTC 24 |
1246099634 ps |
T194 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4003745428 |
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|
Oct 09 12:24:59 PM UTC 24 |
Oct 09 12:35:43 PM UTC 24 |
48071350197 ps |
T195 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1194272685 |
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|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:35:54 PM UTC 24 |
18458400954 ps |
T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3876987801 |
|
|
Oct 09 12:35:44 PM UTC 24 |
Oct 09 12:35:55 PM UTC 24 |
1461516875 ps |
T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761903578 |
|
|
Oct 09 12:35:31 PM UTC 24 |
Oct 09 12:35:59 PM UTC 24 |
1072743365 ps |
T198 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3578489964 |
|
|
Oct 09 12:35:23 PM UTC 24 |
Oct 09 12:36:05 PM UTC 24 |
2615512342 ps |
T199 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.224349654 |
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|
Oct 09 12:32:46 PM UTC 24 |
Oct 09 12:36:13 PM UTC 24 |
3633023358 ps |
T200 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1159052433 |
|
|
Oct 09 12:36:06 PM UTC 24 |
Oct 09 12:36:14 PM UTC 24 |
1031093526 ps |
T48 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.626491335 |
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|
Oct 09 12:34:17 PM UTC 24 |
Oct 09 12:36:14 PM UTC 24 |
1639622996 ps |
T201 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1149758786 |
|
|
Oct 09 12:36:16 PM UTC 24 |
Oct 09 12:36:30 PM UTC 24 |
8248457369 ps |
T131 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.164226603 |
|
|
Oct 09 12:23:43 PM UTC 24 |
Oct 09 12:36:46 PM UTC 24 |
55947788667 ps |
T150 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3562119719 |
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|
Oct 09 12:21:33 PM UTC 24 |
Oct 09 12:36:50 PM UTC 24 |
65226753369 ps |
T202 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.718499139 |
|
|
Oct 09 12:36:51 PM UTC 24 |
Oct 09 12:36:53 PM UTC 24 |
13214996 ps |
T203 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.4061901889 |
|
|
Oct 09 12:36:54 PM UTC 24 |
Oct 09 12:37:23 PM UTC 24 |
556865316 ps |
T49 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1346919198 |
|
|
Oct 09 12:36:31 PM UTC 24 |
Oct 09 12:37:34 PM UTC 24 |
7924220342 ps |
T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2866813901 |
|
|
Oct 09 12:33:41 PM UTC 24 |
Oct 09 12:37:39 PM UTC 24 |
4566637923 ps |
T57 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.248428525 |
|
|
Oct 09 12:36:16 PM UTC 24 |
Oct 09 12:37:56 PM UTC 24 |
10475458012 ps |
T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3388787233 |
|
|
Oct 09 12:37:45 PM UTC 24 |
Oct 09 12:37:57 PM UTC 24 |
712913801 ps |
T206 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3788334981 |
|
|
Oct 09 12:37:58 PM UTC 24 |
Oct 09 12:38:08 PM UTC 24 |
2241555206 ps |
T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2525218107 |
|
|
Oct 09 12:34:01 PM UTC 24 |
Oct 09 12:38:19 PM UTC 24 |
4109754184 ps |
T158 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1402369150 |
|
|
Oct 09 12:29:10 PM UTC 24 |
Oct 09 12:38:33 PM UTC 24 |
23382315244 ps |
T208 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1008002943 |
|
|
Oct 09 12:38:09 PM UTC 24 |
Oct 09 12:38:34 PM UTC 24 |
733569130 ps |
T161 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.956624679 |
|
|
Oct 09 12:38:20 PM UTC 24 |
Oct 09 12:39:18 PM UTC 24 |
27012017202 ps |
T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2223397544 |
|
|
Oct 09 12:33:15 PM UTC 24 |
Oct 09 12:40:18 PM UTC 24 |
45415611994 ps |
T209 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3688918730 |
|
|
Oct 09 12:40:19 PM UTC 24 |
Oct 09 12:40:26 PM UTC 24 |
360116096 ps |
T210 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1092956437 |
|
|
Oct 09 12:22:13 PM UTC 24 |
Oct 09 12:40:32 PM UTC 24 |
22727089593 ps |
T211 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.638499784 |
|
|
Oct 09 12:35:07 PM UTC 24 |
Oct 09 12:41:06 PM UTC 24 |
16353009212 ps |
T156 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.915665676 |
|
|
Oct 09 12:26:34 PM UTC 24 |
Oct 09 12:41:06 PM UTC 24 |
55109585997 ps |
T212 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1782205678 |
|
|
Oct 09 12:38:33 PM UTC 24 |
Oct 09 12:41:11 PM UTC 24 |
10402785531 ps |
T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1161397954 |
|
|
Oct 09 12:41:07 PM UTC 24 |
Oct 09 12:41:18 PM UTC 24 |
2742388075 ps |
T214 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1804783657 |
|
|
Oct 09 12:22:14 PM UTC 24 |
Oct 09 12:41:18 PM UTC 24 |
16477417891 ps |
T215 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.4105989371 |
|
|
Oct 09 12:28:46 PM UTC 24 |
Oct 09 12:41:18 PM UTC 24 |
12547982765 ps |
T216 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4102738045 |
|
|
Oct 09 12:41:18 PM UTC 24 |
Oct 09 12:41:20 PM UTC 24 |
24074778 ps |
T217 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.813284771 |
|
|
Oct 09 12:28:11 PM UTC 24 |
Oct 09 12:41:41 PM UTC 24 |
125165754826 ps |
T218 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3199652138 |
|
|
Oct 09 12:36:14 PM UTC 24 |
Oct 09 12:41:43 PM UTC 24 |
27671791705 ps |
T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1382039825 |
|
|
Oct 09 12:41:44 PM UTC 24 |
Oct 09 12:41:54 PM UTC 24 |
1479989057 ps |
T65 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1291823145 |
|
|
Oct 09 12:41:07 PM UTC 24 |
Oct 09 12:41:54 PM UTC 24 |
2569312496 ps |
T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4134330935 |
|
|
Oct 09 12:41:19 PM UTC 24 |
Oct 09 12:42:28 PM UTC 24 |
3081615368 ps |
T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3427789958 |
|
|
Oct 09 12:42:29 PM UTC 24 |
Oct 09 12:42:44 PM UTC 24 |
4166448437 ps |
T222 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1126153787 |
|
|
Oct 09 12:41:56 PM UTC 24 |
Oct 09 12:42:58 PM UTC 24 |
5207586384 ps |
T223 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.908649972 |
|
|
Oct 09 12:40:33 PM UTC 24 |
Oct 09 12:43:29 PM UTC 24 |
4994152017 ps |
T132 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.595168857 |
|
|
Oct 09 12:39:20 PM UTC 24 |
Oct 09 12:43:38 PM UTC 24 |
16348207382 ps |
T224 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.644684306 |
|
|
Oct 09 12:37:40 PM UTC 24 |
Oct 09 12:43:38 PM UTC 24 |
4396041688 ps |
T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3488715569 |
|
|
Oct 09 12:43:40 PM UTC 24 |
Oct 09 12:43:45 PM UTC 24 |
5590504463 ps |
T226 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2752637883 |
|
|
Oct 09 12:42:45 PM UTC 24 |
Oct 09 12:43:54 PM UTC 24 |
9689212744 ps |
T227 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4234339299 |
|
|
Oct 09 12:37:57 PM UTC 24 |
Oct 09 12:43:55 PM UTC 24 |
28827608183 ps |
T33 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.3193999044 |
|
|
Oct 09 12:43:56 PM UTC 24 |
Oct 09 12:44:07 PM UTC 24 |
1333398107 ps |
T155 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3831728335 |
|
|
Oct 09 12:33:42 PM UTC 24 |
Oct 09 12:45:05 PM UTC 24 |
17867360936 ps |
T228 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1711588505 |
|
|
Oct 09 12:45:06 PM UTC 24 |
Oct 09 12:45:08 PM UTC 24 |
14474018 ps |
T66 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.794618529 |
|
|
Oct 09 12:44:08 PM UTC 24 |
Oct 09 12:45:08 PM UTC 24 |
7381520160 ps |
T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1263139711 |
|
|
Oct 09 12:35:09 PM UTC 24 |
Oct 09 12:45:34 PM UTC 24 |
19951125201 ps |
T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1333881911 |
|
|
Oct 09 12:45:09 PM UTC 24 |
Oct 09 12:45:37 PM UTC 24 |
1120323957 ps |
T58 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1259410546 |
|
|
Oct 09 12:43:55 PM UTC 24 |
Oct 09 12:45:38 PM UTC 24 |
1451157501 ps |
T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.214999265 |
|
|
Oct 09 12:45:37 PM UTC 24 |
Oct 09 12:46:17 PM UTC 24 |
907221695 ps |
T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1387045645 |
|
|
Oct 09 12:40:27 PM UTC 24 |
Oct 09 12:46:21 PM UTC 24 |
86164391150 ps |
T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.7243817 |
|
|
Oct 09 12:46:18 PM UTC 24 |
Oct 09 12:46:45 PM UTC 24 |
718111203 ps |
T234 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.59803490 |
|
|
Oct 09 12:46:22 PM UTC 24 |
Oct 09 12:46:47 PM UTC 24 |
765057830 ps |
T235 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3643126785 |
|
|
Oct 09 12:43:46 PM UTC 24 |
Oct 09 12:47:44 PM UTC 24 |
28899117704 ps |
T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.191326471 |
|
|
Oct 09 12:41:41 PM UTC 24 |
Oct 09 12:47:48 PM UTC 24 |
4854948990 ps |
T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3453964077 |
|
|
Oct 09 12:46:46 PM UTC 24 |
Oct 09 12:48:25 PM UTC 24 |
33157411135 ps |
T238 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.800772115 |
|
|
Oct 09 12:48:26 PM UTC 24 |
Oct 09 12:48:34 PM UTC 24 |
355194266 ps |
T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3768267969 |
|
|
Oct 09 12:41:19 PM UTC 24 |
Oct 09 12:48:38 PM UTC 24 |
10869846685 ps |
T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4047104403 |
|
|
Oct 09 12:36:47 PM UTC 24 |
Oct 09 12:49:18 PM UTC 24 |
28699753705 ps |
T240 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.215601656 |
|
|
Oct 09 12:49:19 PM UTC 24 |
Oct 09 12:49:26 PM UTC 24 |
2657826706 ps |
T67 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3339522565 |
|
|
Oct 09 12:49:26 PM UTC 24 |
Oct 09 12:50:08 PM UTC 24 |
924290153 ps |
T241 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3798247600 |
|
|
Oct 09 12:32:20 PM UTC 24 |
Oct 09 12:50:09 PM UTC 24 |
78753918005 ps |
T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3721437915 |
|
|
Oct 09 12:50:09 PM UTC 24 |
Oct 09 12:50:12 PM UTC 24 |
23778793 ps |
T243 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3004734564 |
|
|
Oct 09 12:35:55 PM UTC 24 |
Oct 09 12:50:14 PM UTC 24 |
59421643210 ps |
T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1108290130 |
|
|
Oct 09 12:38:35 PM UTC 24 |
Oct 09 12:50:29 PM UTC 24 |
18574662861 ps |
T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1517123580 |
|
|
Oct 09 12:33:50 PM UTC 24 |
Oct 09 12:50:31 PM UTC 24 |
54409297289 ps |
T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.586327430 |
|
|
Oct 09 12:50:10 PM UTC 24 |
Oct 09 12:50:36 PM UTC 24 |
1520145266 ps |
T246 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3530834705 |
|
|
Oct 09 12:18:03 PM UTC 24 |
Oct 09 12:50:37 PM UTC 24 |
26894481128 ps |
T247 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3326966853 |
|
|
Oct 09 12:30:46 PM UTC 24 |
Oct 09 12:50:44 PM UTC 24 |
17905887479 ps |
T248 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4202054845 |
|
|
Oct 09 12:50:32 PM UTC 24 |
Oct 09 12:50:52 PM UTC 24 |
432317383 ps |
T249 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1763505270 |
|
|
Oct 09 12:47:46 PM UTC 24 |
Oct 09 12:51:08 PM UTC 24 |
7851377346 ps |
T250 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1558211726 |
|
|
Oct 09 12:50:54 PM UTC 24 |
Oct 09 12:51:12 PM UTC 24 |
6152980018 ps |
T251 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3941846072 |
|
|
Oct 09 12:48:39 PM UTC 24 |
Oct 09 12:51:13 PM UTC 24 |
18838927948 ps |
T252 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1579133551 |
|
|
Oct 09 12:50:44 PM UTC 24 |
Oct 09 12:51:36 PM UTC 24 |
3103550527 ps |
T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1316681245 |
|
|
Oct 09 12:50:38 PM UTC 24 |
Oct 09 12:51:44 PM UTC 24 |
3401680446 ps |
T254 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3898127958 |
|
|
Oct 09 12:51:37 PM UTC 24 |
Oct 09 12:51:45 PM UTC 24 |
419506792 ps |
T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.2886136997 |
|
|
Oct 09 12:51:46 PM UTC 24 |
Oct 09 12:51:57 PM UTC 24 |
694031848 ps |
T256 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1367871855 |
|
|
Oct 09 12:45:39 PM UTC 24 |
Oct 09 12:52:07 PM UTC 24 |
26818125646 ps |
T257 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3463892041 |
|
|
Oct 09 12:51:58 PM UTC 24 |
Oct 09 12:52:09 PM UTC 24 |
1959561441 ps |
T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1222136330 |
|
|
Oct 09 12:41:56 PM UTC 24 |
Oct 09 12:52:11 PM UTC 24 |
35251631874 ps |
T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1554831239 |
|
|
Oct 09 12:52:10 PM UTC 24 |
Oct 09 12:52:12 PM UTC 24 |
36509108 ps |
T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2831418845 |
|
|
Oct 09 12:52:12 PM UTC 24 |
Oct 09 12:52:34 PM UTC 24 |
502692300 ps |
T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3999807848 |
|
|
Oct 09 12:45:35 PM UTC 24 |
Oct 09 12:53:31 PM UTC 24 |
19274302801 ps |
T262 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2961102422 |
|
|
Oct 09 12:30:42 PM UTC 24 |
Oct 09 12:53:32 PM UTC 24 |
46165765165 ps |
T263 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3952240373 |
|
|
Oct 09 12:51:09 PM UTC 24 |
Oct 09 12:53:38 PM UTC 24 |
3695843559 ps |
T264 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1783370739 |
|
|
Oct 09 12:48:34 PM UTC 24 |
Oct 09 12:53:39 PM UTC 24 |
5417964842 ps |
T265 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2483527736 |
|
|
Oct 09 12:45:09 PM UTC 24 |
Oct 09 12:53:43 PM UTC 24 |
11901187878 ps |
T266 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1195559760 |
|
|
Oct 09 12:42:59 PM UTC 24 |
Oct 09 12:53:47 PM UTC 24 |
17498294944 ps |
T267 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2995378392 |
|
|
Oct 09 12:53:33 PM UTC 24 |
Oct 09 12:53:58 PM UTC 24 |
593838623 ps |
T268 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1680074195 |
|
|
Oct 09 12:41:21 PM UTC 24 |
Oct 09 12:54:11 PM UTC 24 |
164008125593 ps |
T269 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1335192402 |
|
|
Oct 09 12:53:40 PM UTC 24 |
Oct 09 12:54:18 PM UTC 24 |
982868754 ps |
T270 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2030149913 |
|
|
Oct 09 12:54:18 PM UTC 24 |
Oct 09 12:54:25 PM UTC 24 |
350411227 ps |
T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1001821560 |
|
|
Oct 09 12:53:43 PM UTC 24 |
Oct 09 12:55:28 PM UTC 24 |
8620675715 ps |
T59 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1320975146 |
|
|
Oct 09 12:51:46 PM UTC 24 |
Oct 09 12:55:30 PM UTC 24 |
40497903480 ps |
T272 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.4079991298 |
|
|
Oct 09 12:55:31 PM UTC 24 |
Oct 09 12:55:43 PM UTC 24 |
662002419 ps |
T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2446269650 |
|
|
Oct 09 12:43:39 PM UTC 24 |
Oct 09 12:56:01 PM UTC 24 |
2784668883 ps |
T273 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.960063235 |
|
|
Oct 09 12:18:10 PM UTC 24 |
Oct 09 12:56:01 PM UTC 24 |
79762371644 ps |
T133 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2798199769 |
|
|
Oct 09 12:54:12 PM UTC 24 |
Oct 09 12:56:04 PM UTC 24 |
8444472677 ps |
T274 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.684842096 |
|
|
Oct 09 12:56:02 PM UTC 24 |
Oct 09 12:56:04 PM UTC 24 |
25713172 ps |
T275 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.468359913 |
|
|
Oct 09 12:55:44 PM UTC 24 |
Oct 09 12:56:06 PM UTC 24 |
1318553235 ps |
T276 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3976511537 |
|
|
Oct 09 12:50:30 PM UTC 24 |
Oct 09 12:56:09 PM UTC 24 |
10730275925 ps |
T151 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1677372427 |
|
|
Oct 09 12:43:29 PM UTC 24 |
Oct 09 12:56:20 PM UTC 24 |
27249332581 ps |
T277 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.389958660 |
|
|
Oct 09 12:47:49 PM UTC 24 |
Oct 09 12:56:20 PM UTC 24 |
3569820687 ps |
T278 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2005508148 |
|
|
Oct 09 12:56:04 PM UTC 24 |
Oct 09 12:56:43 PM UTC 24 |
5809081782 ps |
T279 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1124366861 |
|
|
Oct 09 12:56:21 PM UTC 24 |
Oct 09 12:56:51 PM UTC 24 |
3500273900 ps |
T280 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1160191942 |
|
|
Oct 09 12:56:43 PM UTC 24 |
Oct 09 12:57:03 PM UTC 24 |
725700003 ps |
T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.4242735391 |
|
|
Oct 09 12:56:51 PM UTC 24 |
Oct 09 12:57:10 PM UTC 24 |
2840635978 ps |
T60 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2543470674 |
|
|
Oct 09 12:55:30 PM UTC 24 |
Oct 09 12:57:19 PM UTC 24 |
2629061071 ps |
T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2129784000 |
|
|
Oct 09 12:53:48 PM UTC 24 |
Oct 09 12:57:26 PM UTC 24 |
18242947216 ps |
T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2779796125 |
|
|
Oct 09 12:57:03 PM UTC 24 |
Oct 09 12:57:26 PM UTC 24 |
5751859255 ps |
T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.532888122 |
|
|
Oct 09 12:57:27 PM UTC 24 |
Oct 09 12:57:34 PM UTC 24 |
431392579 ps |
T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2398749048 |
|
|
Oct 09 12:54:26 PM UTC 24 |
Oct 09 12:57:42 PM UTC 24 |
98846459573 ps |
T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2521226017 |
|
|
Oct 09 12:46:48 PM UTC 24 |
Oct 09 12:57:53 PM UTC 24 |
38568912789 ps |
T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3385612647 |
|
|
Oct 09 12:57:53 PM UTC 24 |
Oct 09 12:58:06 PM UTC 24 |
1376552236 ps |
T288 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.578240824 |
|
|
Oct 09 12:51:44 PM UTC 24 |
Oct 09 12:58:06 PM UTC 24 |
10717505698 ps |
T289 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2393726410 |
|
|
Oct 09 12:58:07 PM UTC 24 |
Oct 09 12:58:09 PM UTC 24 |
34828013 ps |
T290 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3729148986 |
|
|
Oct 09 12:37:24 PM UTC 24 |
Oct 09 12:58:41 PM UTC 24 |
11995786784 ps |
T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2924352275 |
|
|
Oct 09 12:57:11 PM UTC 24 |
Oct 09 12:58:45 PM UTC 24 |
2820915993 ps |
T61 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2340624646 |
|
|
Oct 09 12:58:06 PM UTC 24 |
Oct 09 12:58:48 PM UTC 24 |
8544988926 ps |
T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3603311040 |
|
|
Oct 09 12:35:55 PM UTC 24 |
Oct 09 12:59:27 PM UTC 24 |
20784071047 ps |
T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1378842234 |
|
|
Oct 09 12:58:58 PM UTC 24 |
Oct 09 12:59:30 PM UTC 24 |
5192284190 ps |
T294 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2913826520 |
|
|
Oct 09 12:57:34 PM UTC 24 |
Oct 09 12:59:35 PM UTC 24 |
4118872249 ps |
T295 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.360119199 |
|
|
Oct 09 12:45:34 PM UTC 24 |
Oct 09 12:59:48 PM UTC 24 |
124087355019 ps |
T296 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2668434341 |
|
|
Oct 09 12:59:35 PM UTC 24 |
Oct 09 12:59:52 PM UTC 24 |
737220346 ps |
T297 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1539261755 |
|
|
Oct 09 12:58:10 PM UTC 24 |
Oct 09 12:59:53 PM UTC 24 |
790553552 ps |
T298 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2855518390 |
|
|
Oct 09 12:22:06 PM UTC 24 |
Oct 09 01:00:15 PM UTC 24 |
141992666154 ps |
T299 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2717859132 |
|
|
Oct 09 12:59:31 PM UTC 24 |
Oct 09 01:00:17 PM UTC 24 |
767389586 ps |
T300 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.957155290 |
|
|
Oct 09 01:00:18 PM UTC 24 |
Oct 09 01:00:24 PM UTC 24 |
712916788 ps |
T301 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3531276263 |
|
|
Oct 09 12:53:32 PM UTC 24 |
Oct 09 01:00:37 PM UTC 24 |
11252501168 ps |
T302 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1649442416 |
|
|
Oct 09 12:57:43 PM UTC 24 |
Oct 09 01:00:39 PM UTC 24 |
2457882985 ps |
T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2526888090 |
|
|
Oct 09 12:53:39 PM UTC 24 |
Oct 09 01:00:40 PM UTC 24 |
218396218852 ps |
T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2083880543 |
|
|
Oct 09 12:59:53 PM UTC 24 |
Oct 09 01:00:43 PM UTC 24 |
1635234280 ps |
T305 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1778370040 |
|
|
Oct 09 12:57:27 PM UTC 24 |
Oct 09 01:00:47 PM UTC 24 |
6317680851 ps |
T306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.877500881 |
|
|
Oct 09 01:00:48 PM UTC 24 |
Oct 09 01:00:50 PM UTC 24 |
38242688 ps |
T307 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.975568144 |
|
|
Oct 09 01:00:40 PM UTC 24 |
Oct 09 01:00:54 PM UTC 24 |
2356798428 ps |
T308 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.440465668 |
|
|
Oct 09 12:56:05 PM UTC 24 |
Oct 09 01:00:55 PM UTC 24 |
3456816216 ps |
T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1242670508 |
|
|
Oct 09 12:50:37 PM UTC 24 |
Oct 09 01:01:24 PM UTC 24 |
63297673644 ps |
T310 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.411849161 |
|
|
Oct 09 12:53:59 PM UTC 24 |
Oct 09 01:01:27 PM UTC 24 |
16778958439 ps |