Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.64 99.50 96.05 99.72 100.00 97.34 99.13 98.72


Total tests in report: 1083
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.00 71.00 92.04 92.04 69.60 69.60 85.92 85.92 33.33 33.33 81.37 81.37 93.61 93.61 41.13 41.13 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3225264152
80.80 9.80 94.80 2.77 81.12 11.52 87.19 1.27 47.62 14.29 86.03 4.66 95.36 1.74 73.49 32.36 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2307627702
87.39 6.59 97.07 2.26 82.19 1.07 88.33 1.14 85.71 38.10 89.46 3.43 95.50 0.15 73.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1346919198
90.28 2.88 98.24 1.17 83.73 1.54 88.50 0.17 100.00 14.29 91.42 1.96 96.37 0.87 73.67 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1724692259
93.09 2.81 98.58 0.34 87.89 4.16 96.63 8.13 100.00 0.00 94.12 2.70 96.37 0.00 78.06 4.39 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512464987
94.09 1.00 98.74 0.17 88.72 0.83 96.76 0.14 100.00 0.00 94.85 0.74 96.37 0.00 83.18 5.12 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.890781814
94.90 0.81 98.91 0.17 90.86 2.14 97.66 0.90 100.00 0.00 95.83 0.98 96.95 0.58 84.10 0.91 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.7590283
95.60 0.70 98.91 0.00 91.21 0.36 98.24 0.59 100.00 0.00 96.32 0.49 96.95 0.00 87.57 3.47 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1379979564
96.26 0.66 99.16 0.25 91.21 0.00 98.59 0.34 100.00 0.00 96.57 0.25 97.10 0.15 91.22 3.66 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2675997623
96.67 0.41 99.16 0.00 91.33 0.12 98.59 0.00 100.00 0.00 96.57 0.00 97.10 0.00 93.97 2.74 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.960063235
97.05 0.37 99.16 0.00 91.33 0.00 98.66 0.07 100.00 0.00 96.57 0.00 97.82 0.73 95.80 1.83 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3934216209
97.37 0.32 99.41 0.25 92.16 0.83 98.66 0.00 100.00 0.00 97.55 0.98 97.82 0.00 95.98 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.3193999044
97.52 0.16 99.41 0.00 92.52 0.36 98.66 0.00 100.00 0.00 97.55 0.00 97.82 0.00 96.71 0.73 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4047104403
97.67 0.15 99.41 0.00 92.52 0.00 98.66 0.00 100.00 0.00 97.55 0.00 98.84 1.02 96.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1520453853
97.80 0.13 99.50 0.08 92.52 0.00 99.48 0.83 100.00 0.00 97.55 0.00 98.84 0.00 96.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.200439499
97.90 0.10 99.50 0.00 92.52 0.00 99.48 0.00 100.00 0.00 97.55 0.00 98.84 0.00 97.44 0.73 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3348518951
97.98 0.08 99.50 0.00 92.52 0.00 99.48 0.00 100.00 0.00 97.55 0.00 98.84 0.00 97.99 0.55 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1677372427
98.04 0.06 99.50 0.00 92.87 0.36 99.55 0.07 100.00 0.00 97.55 0.00 98.84 0.00 97.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1361126443
98.10 0.05 99.50 0.00 92.87 0.00 99.55 0.00 100.00 0.00 97.55 0.00 98.84 0.00 98.35 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.301428978
98.13 0.03 99.50 0.00 92.99 0.12 99.66 0.10 100.00 0.00 97.55 0.00 98.84 0.00 98.35 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.105053325
98.16 0.03 99.50 0.00 92.99 0.00 99.72 0.07 100.00 0.00 97.55 0.00 98.98 0.15 98.35 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1378274002
98.18 0.03 99.50 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.55 0.00 98.98 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1386368646
98.21 0.03 99.50 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.55 0.00 98.98 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.125574064
98.23 0.02 99.50 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.15 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2034153356


Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.444408866
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342138767
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.66505225
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3490424267
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.185598413
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1444967382
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2945805891
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1436522902
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1725555156
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.633697829
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2795727419
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.346917829
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522519105
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2612045579
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4142240092
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1664045756
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2593753278
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1762106153
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.542465941
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3714788462
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3177054894
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.975959635
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.786648023
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4290190131
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1020272231
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1403899382
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.172364888
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.698272590
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2988684294
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.663380637
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2776185276
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1501573595
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.332501784
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3535731994
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3166130129
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3423210803
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3014407543
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.801490166
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3023043768
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.711406482
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1827521790
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3086479478
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1934130237
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2670516995
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.201060318
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3435324028
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1157331322
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.493414515
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930512184
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4273413318
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2526903326
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2680605891
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.472497417
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3515221320
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1303043395
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.548855785
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2136877368
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1045016175
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2759402331
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1463450069
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.778259131
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2665283611
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3834701720
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2903193145
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1857461230
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.551507700
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2591074668
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.961219410
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1145480147
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.274070381
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.262814051
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2387003505
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3856646672
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967025671
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506167649
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.485777188
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1207405401
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.936308777
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.794717033
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4012557481
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1876484718
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1966248864
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3405468819
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3799817957
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/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.628607210
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/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3413685763
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1500634533
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3228700974
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/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1402369150
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2098904662
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.1941498384
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2860762191
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3177778456
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.269686024
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231165320
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3184968903
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4214074628
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2866813901
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1004753402
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.938362602
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/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1422697318
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2109003361
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/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3798247600
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1573591543
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2223397544
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.50887118
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.3201485217
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1517123580
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1566626219
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.298665005
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.626491335
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.224349654
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1952137761
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3004734564
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.718499139
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.203248631
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3603311040
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3876987801
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3578489964
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.248428525
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3199652138
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3798146143
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1582504142
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1263139711
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1159052433
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1149758786
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3415686705
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.638499784
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761903578
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1782205678
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4102738045
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3739291750
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1108290130
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.956624679
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3788334981
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.908649972
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1387045645
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3729148986
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3388787233
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4234339299
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3688918730
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1161397954
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.595168857
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.4061901889
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857385962
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1291823145
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.644684306
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1008002943
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1195559760
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1711588505
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1680074195
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2752637883
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1126153787
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1259410546
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3643126785
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3768267969
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1382039825
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1222136330
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3488715569
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2446269650
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4134330935
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3144713485
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.794618529
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.191326471
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3427789958




Total test records in report: 1083
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.200439499 Oct 09 12:18:05 PM UTC 24 Oct 09 12:18:11 PM UTC 24 1344870878 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.105053325 Oct 09 12:18:05 PM UTC 24 Oct 09 12:18:18 PM UTC 24 668688209 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1182091038 Oct 09 12:18:03 PM UTC 24 Oct 09 12:18:18 PM UTC 24 4255414477 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1361126443 Oct 09 12:18:18 PM UTC 24 Oct 09 12:18:20 PM UTC 24 44029510 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2215319090 Oct 09 12:18:12 PM UTC 24 Oct 09 12:18:23 PM UTC 24 1277405717 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2271090737 Oct 09 12:18:03 PM UTC 24 Oct 09 12:18:30 PM UTC 24 1473680137 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1843202599 Oct 09 12:18:18 PM UTC 24 Oct 09 12:18:31 PM UTC 24 715479478 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1485622681 Oct 09 12:18:04 PM UTC 24 Oct 09 12:18:36 PM UTC 24 1490977026 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3874894012 Oct 09 12:18:32 PM UTC 24 Oct 09 12:18:48 PM UTC 24 714923100 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3225264152 Oct 09 12:18:05 PM UTC 24 Oct 09 12:18:54 PM UTC 24 17395898918 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.287419000 Oct 09 12:18:54 PM UTC 24 Oct 09 12:19:00 PM UTC 24 698450352 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1379979564 Oct 09 12:18:52 PM UTC 24 Oct 09 12:19:31 PM UTC 24 1155510832 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3728139455 Oct 09 12:18:24 PM UTC 24 Oct 09 12:19:41 PM UTC 24 5283020397 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4244781600 Oct 09 12:19:32 PM UTC 24 Oct 09 12:19:44 PM UTC 24 1354556664 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2229183779 Oct 09 12:18:04 PM UTC 24 Oct 09 12:20:06 PM UTC 24 807529253 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1284224795 Oct 09 12:27:58 PM UTC 24 Oct 09 12:28:05 PM UTC 24 2567318362 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1310989693 Oct 09 12:20:07 PM UTC 24 Oct 09 12:20:11 PM UTC 24 348299421 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.300456195 Oct 09 12:19:42 PM UTC 24 Oct 09 12:20:12 PM UTC 24 627712860 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2735680643 Oct 09 12:20:11 PM UTC 24 Oct 09 12:20:13 PM UTC 24 41164389 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2130510162 Oct 09 12:18:33 PM UTC 24 Oct 09 12:20:20 PM UTC 24 1615659000 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1459144460 Oct 09 12:20:11 PM UTC 24 Oct 09 12:20:33 PM UTC 24 3092661494 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1480811772 Oct 09 12:18:37 PM UTC 24 Oct 09 12:20:38 PM UTC 24 51932102234 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3460181885 Oct 09 12:20:21 PM UTC 24 Oct 09 12:20:55 PM UTC 24 1504742146 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3808193801 Oct 09 12:18:53 PM UTC 24 Oct 09 12:21:18 PM UTC 24 11786924899 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2907349371 Oct 09 12:18:21 PM UTC 24 Oct 09 12:21:27 PM UTC 24 3157435444 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4269405207 Oct 09 12:20:55 PM UTC 24 Oct 09 12:21:32 PM UTC 24 730661328 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1724692259 Oct 09 12:18:05 PM UTC 24 Oct 09 12:21:38 PM UTC 24 41724939028 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2926178196 Oct 09 12:21:40 PM UTC 24 Oct 09 12:21:48 PM UTC 24 1168807675 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.425686627 Oct 09 12:19:25 PM UTC 24 Oct 09 12:21:58 PM UTC 24 4495173377 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2690699980 Oct 09 12:21:19 PM UTC 24 Oct 09 12:22:08 PM UTC 24 13291290009 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.837600444 Oct 09 12:21:58 PM UTC 24 Oct 09 12:22:08 PM UTC 24 2761677286 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2511671178 Oct 09 12:22:09 PM UTC 24 Oct 09 12:22:11 PM UTC 24 44009613 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.642706699 Oct 09 12:20:39 PM UTC 24 Oct 09 12:22:12 PM UTC 24 1585600628 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.7590283 Oct 09 12:22:09 PM UTC 24 Oct 09 12:22:13 PM UTC 24 1049891357 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.72831962 Oct 09 12:18:05 PM UTC 24 Oct 09 12:22:20 PM UTC 24 10904464098 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2664586508 Oct 09 12:22:12 PM UTC 24 Oct 09 12:22:25 PM UTC 24 723709069 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1436006205 Oct 09 12:22:25 PM UTC 24 Oct 09 12:22:39 PM UTC 24 2108722915 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512464987 Oct 09 12:21:35 PM UTC 24 Oct 09 12:22:41 PM UTC 24 8294797473 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2464959211 Oct 09 12:22:42 PM UTC 24 Oct 09 12:23:06 PM UTC 24 706073771 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2546872207 Oct 09 12:21:56 PM UTC 24 Oct 09 12:23:20 PM UTC 24 1391155342 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3934216209 Oct 09 12:21:59 PM UTC 24 Oct 09 12:23:41 PM UTC 24 7539121219 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2675997623 Oct 09 12:18:31 PM UTC 24 Oct 09 12:23:42 PM UTC 24 23366766525 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.119361730 Oct 09 12:23:07 PM UTC 24 Oct 09 12:23:54 PM UTC 24 1517374517 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2951790352 Oct 09 12:20:16 PM UTC 24 Oct 09 12:23:57 PM UTC 24 3248076497 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1278970316 Oct 09 12:23:56 PM UTC 24 Oct 09 12:24:03 PM UTC 24 354938472 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2887613022 Oct 09 12:19:01 PM UTC 24 Oct 09 12:24:19 PM UTC 24 5361645068 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.509798039 Oct 09 12:18:03 PM UTC 24 Oct 09 12:24:23 PM UTC 24 27880864331 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3149180485 Oct 09 12:24:20 PM UTC 24 Oct 09 12:24:30 PM UTC 24 662736941 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3823727275 Oct 09 12:24:33 PM UTC 24 Oct 09 12:24:35 PM UTC 24 14574048 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1895000569 Oct 09 12:24:31 PM UTC 24 Oct 09 12:24:36 PM UTC 24 439616620 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2988926859 Oct 09 12:24:36 PM UTC 24 Oct 09 12:24:58 PM UTC 24 859939052 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2678393214 Oct 09 12:23:11 PM UTC 24 Oct 09 12:25:15 PM UTC 24 29501912290 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2307627702 Oct 09 12:24:20 PM UTC 24 Oct 09 12:25:18 PM UTC 24 6833649015 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2569249349 Oct 09 12:24:04 PM UTC 24 Oct 09 12:25:41 PM UTC 24 2842468241 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3786254585 Oct 09 12:26:01 PM UTC 24 Oct 09 12:26:15 PM UTC 24 1342018805 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.157623350 Oct 09 12:25:19 PM UTC 24 Oct 09 12:26:18 PM UTC 24 3346280135 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.380368191 Oct 09 12:23:41 PM UTC 24 Oct 09 12:26:23 PM UTC 24 3612352775 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.639400113 Oct 09 12:20:34 PM UTC 24 Oct 09 12:26:33 PM UTC 24 13238263363 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1151346067 Oct 09 12:26:24 PM UTC 24 Oct 09 12:26:36 PM UTC 24 4791380903 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3335863876 Oct 09 12:26:19 PM UTC 24 Oct 09 12:26:44 PM UTC 24 9769813172 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2156061733 Oct 09 12:26:45 PM UTC 24 Oct 09 12:26:50 PM UTC 24 347178361 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4249650996 Oct 09 12:26:17 PM UTC 24 Oct 09 12:27:17 PM UTC 24 3226439813 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1737640175 Oct 09 12:23:20 PM UTC 24 Oct 09 12:27:20 PM UTC 24 5105583896 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.3948427321 Oct 09 12:27:21 PM UTC 24 Oct 09 12:27:34 PM UTC 24 676211132 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3631977955 Oct 09 12:21:48 PM UTC 24 Oct 09 12:27:48 PM UTC 24 24692066817 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.429093585 Oct 09 12:18:03 PM UTC 24 Oct 09 12:27:57 PM UTC 24 121517560777 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1836251456 Oct 09 12:28:06 PM UTC 24 Oct 09 12:28:08 PM UTC 24 58477386 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4175815263 Oct 09 12:27:35 PM UTC 24 Oct 09 12:28:10 PM UTC 24 3474828473 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.611921754 Oct 09 12:22:41 PM UTC 24 Oct 09 12:29:05 PM UTC 24 19799078798 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3177778456 Oct 09 12:28:09 PM UTC 24 Oct 09 12:29:06 PM UTC 24 5684793157 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3822974199 Oct 09 12:27:17 PM UTC 24 Oct 09 12:29:08 PM UTC 24 10156687343 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2415141703 Oct 09 12:29:08 PM UTC 24 Oct 09 12:29:34 PM UTC 24 1090463814 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.302342508 Oct 09 12:26:50 PM UTC 24 Oct 09 12:29:46 PM UTC 24 10440674728 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.55431582 Oct 09 12:29:35 PM UTC 24 Oct 09 12:29:50 PM UTC 24 695579924 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4214074628 Oct 09 12:29:46 PM UTC 24 Oct 09 12:30:41 PM UTC 24 3223158264 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2967075645 Oct 09 12:23:58 PM UTC 24 Oct 09 12:30:44 PM UTC 24 44055972087 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2098904662 Oct 09 12:31:13 PM UTC 24 Oct 09 12:31:20 PM UTC 24 693392501 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.923991621 Oct 09 12:22:21 PM UTC 24 Oct 09 12:31:00 PM UTC 24 6192072089 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.130295527 Oct 09 12:21:29 PM UTC 24 Oct 09 12:31:12 PM UTC 24 25501042507 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3951949373 Oct 09 12:25:16 PM UTC 24 Oct 09 12:31:21 PM UTC 24 16560209151 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1626289764 Oct 09 12:18:05 PM UTC 24 Oct 09 12:31:41 PM UTC 24 76842917087 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.973228267 Oct 09 12:29:51 PM UTC 24 Oct 09 12:31:44 PM UTC 24 11774221752 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.1941498384 Oct 09 12:31:42 PM UTC 24 Oct 09 12:31:55 PM UTC 24 691842221 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231165320 Oct 09 12:31:45 PM UTC 24 Oct 09 12:32:01 PM UTC 24 1092816881 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3724837730 Oct 09 12:32:03 PM UTC 24 Oct 09 12:32:05 PM UTC 24 21925754 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2394780541 Oct 09 12:20:13 PM UTC 24 Oct 09 12:32:26 PM UTC 24 9602277989 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1566626219 Oct 09 12:32:06 PM UTC 24 Oct 09 12:32:45 PM UTC 24 745103650 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2860762191 Oct 09 12:31:02 PM UTC 24 Oct 09 12:32:52 PM UTC 24 757596863 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2065114304 Oct 09 12:25:41 PM UTC 24 Oct 09 12:33:15 PM UTC 24 6763006718 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4226918557 Oct 09 12:18:05 PM UTC 24 Oct 09 12:33:20 PM UTC 24 2836043401 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.908273339 Oct 09 12:18:19 PM UTC 24 Oct 09 12:33:31 PM UTC 24 21495972629 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1205324265 Oct 09 12:27:49 PM UTC 24 Oct 09 12:33:39 PM UTC 24 15492939533 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2282395184 Oct 09 12:18:05 PM UTC 24 Oct 09 12:33:40 PM UTC 24 16997138524 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1573591543 Oct 09 12:32:53 PM UTC 24 Oct 09 12:33:50 PM UTC 24 5030542924 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3184968903 Oct 09 12:29:06 PM UTC 24 Oct 09 12:33:53 PM UTC 24 8504304755 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1014979454 Oct 09 12:26:37 PM UTC 24 Oct 09 12:34:00 PM UTC 24 2891553308 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.50887118 Oct 09 12:33:54 PM UTC 24 Oct 09 12:34:02 PM UTC 24 354251740 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1460314068 Oct 09 12:18:50 PM UTC 24 Oct 09 12:34:02 PM UTC 24 50357122510 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.3201485217 Oct 09 12:34:04 PM UTC 24 Oct 09 12:34:16 PM UTC 24 2554178008 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1365564677 Oct 09 12:31:22 PM UTC 24 Oct 09 12:34:23 PM UTC 24 5106590740 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1804362828 Oct 09 12:31:21 PM UTC 24 Oct 09 12:34:36 PM UTC 24 7195665555 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1004753402 Oct 09 12:34:37 PM UTC 24 Oct 09 12:34:39 PM UTC 24 13544567 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3209093615 Oct 09 12:33:40 PM UTC 24 Oct 09 12:34:55 PM UTC 24 38667472823 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3415686705 Oct 09 12:34:40 PM UTC 24 Oct 09 12:35:06 PM UTC 24 1648632022 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1422697318 Oct 09 12:33:21 PM UTC 24 Oct 09 12:35:07 PM UTC 24 781749687 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1952137761 Oct 09 12:33:32 PM UTC 24 Oct 09 12:35:08 PM UTC 24 828627925 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2837883117 Oct 09 12:24:37 PM UTC 24 Oct 09 12:35:08 PM UTC 24 20198579725 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2109003361 Oct 09 12:34:02 PM UTC 24 Oct 09 12:35:22 PM UTC 24 4911356263 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1582504142 Oct 09 12:35:08 PM UTC 24 Oct 09 12:35:30 PM UTC 24 1246099634 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4003745428 Oct 09 12:24:59 PM UTC 24 Oct 09 12:35:43 PM UTC 24 48071350197 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1194272685 Oct 09 12:18:03 PM UTC 24 Oct 09 12:35:54 PM UTC 24 18458400954 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3876987801 Oct 09 12:35:44 PM UTC 24 Oct 09 12:35:55 PM UTC 24 1461516875 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761903578 Oct 09 12:35:31 PM UTC 24 Oct 09 12:35:59 PM UTC 24 1072743365 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3578489964 Oct 09 12:35:23 PM UTC 24 Oct 09 12:36:05 PM UTC 24 2615512342 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.224349654 Oct 09 12:32:46 PM UTC 24 Oct 09 12:36:13 PM UTC 24 3633023358 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1159052433 Oct 09 12:36:06 PM UTC 24 Oct 09 12:36:14 PM UTC 24 1031093526 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.626491335 Oct 09 12:34:17 PM UTC 24 Oct 09 12:36:14 PM UTC 24 1639622996 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1149758786 Oct 09 12:36:16 PM UTC 24 Oct 09 12:36:30 PM UTC 24 8248457369 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.164226603 Oct 09 12:23:43 PM UTC 24 Oct 09 12:36:46 PM UTC 24 55947788667 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3562119719 Oct 09 12:21:33 PM UTC 24 Oct 09 12:36:50 PM UTC 24 65226753369 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.718499139 Oct 09 12:36:51 PM UTC 24 Oct 09 12:36:53 PM UTC 24 13214996 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.4061901889 Oct 09 12:36:54 PM UTC 24 Oct 09 12:37:23 PM UTC 24 556865316 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1346919198 Oct 09 12:36:31 PM UTC 24 Oct 09 12:37:34 PM UTC 24 7924220342 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2866813901 Oct 09 12:33:41 PM UTC 24 Oct 09 12:37:39 PM UTC 24 4566637923 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.248428525 Oct 09 12:36:16 PM UTC 24 Oct 09 12:37:56 PM UTC 24 10475458012 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3388787233 Oct 09 12:37:45 PM UTC 24 Oct 09 12:37:57 PM UTC 24 712913801 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3788334981 Oct 09 12:37:58 PM UTC 24 Oct 09 12:38:08 PM UTC 24 2241555206 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2525218107 Oct 09 12:34:01 PM UTC 24 Oct 09 12:38:19 PM UTC 24 4109754184 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1402369150 Oct 09 12:29:10 PM UTC 24 Oct 09 12:38:33 PM UTC 24 23382315244 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1008002943 Oct 09 12:38:09 PM UTC 24 Oct 09 12:38:34 PM UTC 24 733569130 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.956624679 Oct 09 12:38:20 PM UTC 24 Oct 09 12:39:18 PM UTC 24 27012017202 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2223397544 Oct 09 12:33:15 PM UTC 24 Oct 09 12:40:18 PM UTC 24 45415611994 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3688918730 Oct 09 12:40:19 PM UTC 24 Oct 09 12:40:26 PM UTC 24 360116096 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1092956437 Oct 09 12:22:13 PM UTC 24 Oct 09 12:40:32 PM UTC 24 22727089593 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.638499784 Oct 09 12:35:07 PM UTC 24 Oct 09 12:41:06 PM UTC 24 16353009212 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.915665676 Oct 09 12:26:34 PM UTC 24 Oct 09 12:41:06 PM UTC 24 55109585997 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1782205678 Oct 09 12:38:33 PM UTC 24 Oct 09 12:41:11 PM UTC 24 10402785531 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1161397954 Oct 09 12:41:07 PM UTC 24 Oct 09 12:41:18 PM UTC 24 2742388075 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1804783657 Oct 09 12:22:14 PM UTC 24 Oct 09 12:41:18 PM UTC 24 16477417891 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.4105989371 Oct 09 12:28:46 PM UTC 24 Oct 09 12:41:18 PM UTC 24 12547982765 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4102738045 Oct 09 12:41:18 PM UTC 24 Oct 09 12:41:20 PM UTC 24 24074778 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.813284771 Oct 09 12:28:11 PM UTC 24 Oct 09 12:41:41 PM UTC 24 125165754826 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3199652138 Oct 09 12:36:14 PM UTC 24 Oct 09 12:41:43 PM UTC 24 27671791705 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1382039825 Oct 09 12:41:44 PM UTC 24 Oct 09 12:41:54 PM UTC 24 1479989057 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1291823145 Oct 09 12:41:07 PM UTC 24 Oct 09 12:41:54 PM UTC 24 2569312496 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4134330935 Oct 09 12:41:19 PM UTC 24 Oct 09 12:42:28 PM UTC 24 3081615368 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3427789958 Oct 09 12:42:29 PM UTC 24 Oct 09 12:42:44 PM UTC 24 4166448437 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1126153787 Oct 09 12:41:56 PM UTC 24 Oct 09 12:42:58 PM UTC 24 5207586384 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.908649972 Oct 09 12:40:33 PM UTC 24 Oct 09 12:43:29 PM UTC 24 4994152017 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.595168857 Oct 09 12:39:20 PM UTC 24 Oct 09 12:43:38 PM UTC 24 16348207382 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.644684306 Oct 09 12:37:40 PM UTC 24 Oct 09 12:43:38 PM UTC 24 4396041688 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3488715569 Oct 09 12:43:40 PM UTC 24 Oct 09 12:43:45 PM UTC 24 5590504463 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2752637883 Oct 09 12:42:45 PM UTC 24 Oct 09 12:43:54 PM UTC 24 9689212744 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4234339299 Oct 09 12:37:57 PM UTC 24 Oct 09 12:43:55 PM UTC 24 28827608183 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.3193999044 Oct 09 12:43:56 PM UTC 24 Oct 09 12:44:07 PM UTC 24 1333398107 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3831728335 Oct 09 12:33:42 PM UTC 24 Oct 09 12:45:05 PM UTC 24 17867360936 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1711588505 Oct 09 12:45:06 PM UTC 24 Oct 09 12:45:08 PM UTC 24 14474018 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.794618529 Oct 09 12:44:08 PM UTC 24 Oct 09 12:45:08 PM UTC 24 7381520160 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1263139711 Oct 09 12:35:09 PM UTC 24 Oct 09 12:45:34 PM UTC 24 19951125201 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1333881911 Oct 09 12:45:09 PM UTC 24 Oct 09 12:45:37 PM UTC 24 1120323957 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1259410546 Oct 09 12:43:55 PM UTC 24 Oct 09 12:45:38 PM UTC 24 1451157501 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.214999265 Oct 09 12:45:37 PM UTC 24 Oct 09 12:46:17 PM UTC 24 907221695 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1387045645 Oct 09 12:40:27 PM UTC 24 Oct 09 12:46:21 PM UTC 24 86164391150 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.7243817 Oct 09 12:46:18 PM UTC 24 Oct 09 12:46:45 PM UTC 24 718111203 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.59803490 Oct 09 12:46:22 PM UTC 24 Oct 09 12:46:47 PM UTC 24 765057830 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3643126785 Oct 09 12:43:46 PM UTC 24 Oct 09 12:47:44 PM UTC 24 28899117704 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.191326471 Oct 09 12:41:41 PM UTC 24 Oct 09 12:47:48 PM UTC 24 4854948990 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3453964077 Oct 09 12:46:46 PM UTC 24 Oct 09 12:48:25 PM UTC 24 33157411135 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.800772115 Oct 09 12:48:26 PM UTC 24 Oct 09 12:48:34 PM UTC 24 355194266 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3768267969 Oct 09 12:41:19 PM UTC 24 Oct 09 12:48:38 PM UTC 24 10869846685 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4047104403 Oct 09 12:36:47 PM UTC 24 Oct 09 12:49:18 PM UTC 24 28699753705 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.215601656 Oct 09 12:49:19 PM UTC 24 Oct 09 12:49:26 PM UTC 24 2657826706 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3339522565 Oct 09 12:49:26 PM UTC 24 Oct 09 12:50:08 PM UTC 24 924290153 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3798247600 Oct 09 12:32:20 PM UTC 24 Oct 09 12:50:09 PM UTC 24 78753918005 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3721437915 Oct 09 12:50:09 PM UTC 24 Oct 09 12:50:12 PM UTC 24 23778793 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3004734564 Oct 09 12:35:55 PM UTC 24 Oct 09 12:50:14 PM UTC 24 59421643210 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1108290130 Oct 09 12:38:35 PM UTC 24 Oct 09 12:50:29 PM UTC 24 18574662861 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1517123580 Oct 09 12:33:50 PM UTC 24 Oct 09 12:50:31 PM UTC 24 54409297289 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.586327430 Oct 09 12:50:10 PM UTC 24 Oct 09 12:50:36 PM UTC 24 1520145266 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3530834705 Oct 09 12:18:03 PM UTC 24 Oct 09 12:50:37 PM UTC 24 26894481128 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3326966853 Oct 09 12:30:46 PM UTC 24 Oct 09 12:50:44 PM UTC 24 17905887479 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4202054845 Oct 09 12:50:32 PM UTC 24 Oct 09 12:50:52 PM UTC 24 432317383 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1763505270 Oct 09 12:47:46 PM UTC 24 Oct 09 12:51:08 PM UTC 24 7851377346 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1558211726 Oct 09 12:50:54 PM UTC 24 Oct 09 12:51:12 PM UTC 24 6152980018 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3941846072 Oct 09 12:48:39 PM UTC 24 Oct 09 12:51:13 PM UTC 24 18838927948 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1579133551 Oct 09 12:50:44 PM UTC 24 Oct 09 12:51:36 PM UTC 24 3103550527 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1316681245 Oct 09 12:50:38 PM UTC 24 Oct 09 12:51:44 PM UTC 24 3401680446 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3898127958 Oct 09 12:51:37 PM UTC 24 Oct 09 12:51:45 PM UTC 24 419506792 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.2886136997 Oct 09 12:51:46 PM UTC 24 Oct 09 12:51:57 PM UTC 24 694031848 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1367871855 Oct 09 12:45:39 PM UTC 24 Oct 09 12:52:07 PM UTC 24 26818125646 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3463892041 Oct 09 12:51:58 PM UTC 24 Oct 09 12:52:09 PM UTC 24 1959561441 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1222136330 Oct 09 12:41:56 PM UTC 24 Oct 09 12:52:11 PM UTC 24 35251631874 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1554831239 Oct 09 12:52:10 PM UTC 24 Oct 09 12:52:12 PM UTC 24 36509108 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2831418845 Oct 09 12:52:12 PM UTC 24 Oct 09 12:52:34 PM UTC 24 502692300 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3999807848 Oct 09 12:45:35 PM UTC 24 Oct 09 12:53:31 PM UTC 24 19274302801 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2961102422 Oct 09 12:30:42 PM UTC 24 Oct 09 12:53:32 PM UTC 24 46165765165 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3952240373 Oct 09 12:51:09 PM UTC 24 Oct 09 12:53:38 PM UTC 24 3695843559 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1783370739 Oct 09 12:48:34 PM UTC 24 Oct 09 12:53:39 PM UTC 24 5417964842 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2483527736 Oct 09 12:45:09 PM UTC 24 Oct 09 12:53:43 PM UTC 24 11901187878 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1195559760 Oct 09 12:42:59 PM UTC 24 Oct 09 12:53:47 PM UTC 24 17498294944 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2995378392 Oct 09 12:53:33 PM UTC 24 Oct 09 12:53:58 PM UTC 24 593838623 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1680074195 Oct 09 12:41:21 PM UTC 24 Oct 09 12:54:11 PM UTC 24 164008125593 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1335192402 Oct 09 12:53:40 PM UTC 24 Oct 09 12:54:18 PM UTC 24 982868754 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2030149913 Oct 09 12:54:18 PM UTC 24 Oct 09 12:54:25 PM UTC 24 350411227 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1001821560 Oct 09 12:53:43 PM UTC 24 Oct 09 12:55:28 PM UTC 24 8620675715 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1320975146 Oct 09 12:51:46 PM UTC 24 Oct 09 12:55:30 PM UTC 24 40497903480 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.4079991298 Oct 09 12:55:31 PM UTC 24 Oct 09 12:55:43 PM UTC 24 662002419 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2446269650 Oct 09 12:43:39 PM UTC 24 Oct 09 12:56:01 PM UTC 24 2784668883 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.960063235 Oct 09 12:18:10 PM UTC 24 Oct 09 12:56:01 PM UTC 24 79762371644 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2798199769 Oct 09 12:54:12 PM UTC 24 Oct 09 12:56:04 PM UTC 24 8444472677 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.684842096 Oct 09 12:56:02 PM UTC 24 Oct 09 12:56:04 PM UTC 24 25713172 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.468359913 Oct 09 12:55:44 PM UTC 24 Oct 09 12:56:06 PM UTC 24 1318553235 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3976511537 Oct 09 12:50:30 PM UTC 24 Oct 09 12:56:09 PM UTC 24 10730275925 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1677372427 Oct 09 12:43:29 PM UTC 24 Oct 09 12:56:20 PM UTC 24 27249332581 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.389958660 Oct 09 12:47:49 PM UTC 24 Oct 09 12:56:20 PM UTC 24 3569820687 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2005508148 Oct 09 12:56:04 PM UTC 24 Oct 09 12:56:43 PM UTC 24 5809081782 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1124366861 Oct 09 12:56:21 PM UTC 24 Oct 09 12:56:51 PM UTC 24 3500273900 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1160191942 Oct 09 12:56:43 PM UTC 24 Oct 09 12:57:03 PM UTC 24 725700003 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.4242735391 Oct 09 12:56:51 PM UTC 24 Oct 09 12:57:10 PM UTC 24 2840635978 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2543470674 Oct 09 12:55:30 PM UTC 24 Oct 09 12:57:19 PM UTC 24 2629061071 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2129784000 Oct 09 12:53:48 PM UTC 24 Oct 09 12:57:26 PM UTC 24 18242947216 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2779796125 Oct 09 12:57:03 PM UTC 24 Oct 09 12:57:26 PM UTC 24 5751859255 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.532888122 Oct 09 12:57:27 PM UTC 24 Oct 09 12:57:34 PM UTC 24 431392579 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2398749048 Oct 09 12:54:26 PM UTC 24 Oct 09 12:57:42 PM UTC 24 98846459573 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2521226017 Oct 09 12:46:48 PM UTC 24 Oct 09 12:57:53 PM UTC 24 38568912789 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3385612647 Oct 09 12:57:53 PM UTC 24 Oct 09 12:58:06 PM UTC 24 1376552236 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.578240824 Oct 09 12:51:44 PM UTC 24 Oct 09 12:58:06 PM UTC 24 10717505698 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2393726410 Oct 09 12:58:07 PM UTC 24 Oct 09 12:58:09 PM UTC 24 34828013 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3729148986 Oct 09 12:37:24 PM UTC 24 Oct 09 12:58:41 PM UTC 24 11995786784 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2924352275 Oct 09 12:57:11 PM UTC 24 Oct 09 12:58:45 PM UTC 24 2820915993 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2340624646 Oct 09 12:58:06 PM UTC 24 Oct 09 12:58:48 PM UTC 24 8544988926 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3603311040 Oct 09 12:35:55 PM UTC 24 Oct 09 12:59:27 PM UTC 24 20784071047 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1378842234 Oct 09 12:58:58 PM UTC 24 Oct 09 12:59:30 PM UTC 24 5192284190 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2913826520 Oct 09 12:57:34 PM UTC 24 Oct 09 12:59:35 PM UTC 24 4118872249 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.360119199 Oct 09 12:45:34 PM UTC 24 Oct 09 12:59:48 PM UTC 24 124087355019 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2668434341 Oct 09 12:59:35 PM UTC 24 Oct 09 12:59:52 PM UTC 24 737220346 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1539261755 Oct 09 12:58:10 PM UTC 24 Oct 09 12:59:53 PM UTC 24 790553552 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2855518390 Oct 09 12:22:06 PM UTC 24 Oct 09 01:00:15 PM UTC 24 141992666154 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2717859132 Oct 09 12:59:31 PM UTC 24 Oct 09 01:00:17 PM UTC 24 767389586 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.957155290 Oct 09 01:00:18 PM UTC 24 Oct 09 01:00:24 PM UTC 24 712916788 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3531276263 Oct 09 12:53:32 PM UTC 24 Oct 09 01:00:37 PM UTC 24 11252501168 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1649442416 Oct 09 12:57:43 PM UTC 24 Oct 09 01:00:39 PM UTC 24 2457882985 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2526888090 Oct 09 12:53:39 PM UTC 24 Oct 09 01:00:40 PM UTC 24 218396218852 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2083880543 Oct 09 12:59:53 PM UTC 24 Oct 09 01:00:43 PM UTC 24 1635234280 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1778370040 Oct 09 12:57:27 PM UTC 24 Oct 09 01:00:47 PM UTC 24 6317680851 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.877500881 Oct 09 01:00:48 PM UTC 24 Oct 09 01:00:50 PM UTC 24 38242688 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.975568144 Oct 09 01:00:40 PM UTC 24 Oct 09 01:00:54 PM UTC 24 2356798428 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.440465668 Oct 09 12:56:05 PM UTC 24 Oct 09 01:00:55 PM UTC 24 3456816216 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1242670508 Oct 09 12:50:37 PM UTC 24 Oct 09 01:01:24 PM UTC 24 63297673644 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.411849161 Oct 09 12:53:59 PM UTC 24 Oct 09 01:01:27 PM UTC 24 16778958439 ps
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