Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	339336825	1			T2	1970		T4	109		T5	3380
instr_valid_dis	301656556	1			T2	1970		T4	109		T5	3380
instr_en	28139496	1			T29	16386		T18	219118		T47	131766

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14581388	1			T29	41420		T30	98280		T18	43146
sram_ifetch_valid_disable	298967803	1			T2	1970		T4	109		T5	3380
sram_ifetch_enable	25787634	1			T29	77974		T30	20096		T18	97154

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	339336825	1			T2	1970		T4	109		T5	3380
hw_debug_en_valid_off	289182417	1			T2	1970		T4	109		T5	3380
hw_debug_en_on	38747894	1			T29	24352		T30	76604		T18	38228

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	298967803	1			T2	1970		T4	109		T5	3380
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	282457084	1			T2	1970		T4	109		T5	3380
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13199922	1			T18	78818		T47	116894		T19	140848
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4232008	1			T29	41420		T47	82		T19	28014
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1694372	1			T29	41420		T141	66042		T153	19286
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1806850	1			T47	82		T19	28014		T146	36048
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7895844	1			T30	60864		T19	31114		T48	39616
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5676982	1			T30	60864		T141	33840		T146	36806
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1644362	1			T19	31114		T48	6068		T146	45588
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	18264996	1			T30	15644		T18	20000		T47	132710
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	9672822	1			T30	15644		T47	17266		T20	50288
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7413612	1			T18	20000		T47	115444		T19	51042

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10068156	1			T29	16386		T18	97154		T47	14790
lc_exec_en	12587054	1			T29	24352		T30	96		T18	18228
valid_exec_dis	287394677	1			T2	1970		T4	109		T5	3380
invalid_exec_dis	40369022	1			T29	119394		T30	118376		T18	140300