Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.59 99.50 96.05 99.72 100.00 97.34 99.13 98.35


Total tests in report: 1087
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.80 61.80 90.03 90.03 65.08 65.08 66.18 66.18 23.81 23.81 75.74 75.74 92.90 92.90 18.83 18.83 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3448994480
81.42 19.62 95.22 5.20 79.93 14.85 89.43 23.24 71.43 47.62 84.31 8.58 94.93 2.03 54.66 35.83 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1361667389
87.93 6.51 97.40 2.18 83.85 3.92 92.49 3.06 80.95 9.52 90.20 5.88 95.65 0.72 74.95 20.29 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2502115505
91.12 3.19 98.41 1.01 83.85 0.00 93.32 0.83 100.00 19.05 91.67 1.47 95.65 0.00 74.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1153862915
93.03 1.90 98.74 0.34 87.41 3.56 94.15 0.83 100.00 0.00 93.87 2.21 95.65 0.00 81.35 6.40 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2091545806
94.41 1.38 98.91 0.17 89.79 2.38 96.83 2.69 100.00 0.00 95.34 1.47 96.09 0.43 83.91 2.56 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3405641170
95.22 0.81 99.16 0.25 89.79 0.00 97.80 0.96 100.00 0.00 95.83 0.49 96.23 0.14 87.75 3.84 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.434931579
96.01 0.79 99.16 0.00 90.38 0.59 97.80 0.00 100.00 0.00 95.83 0.00 96.23 0.00 92.69 4.94 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.659400536
96.44 0.43 99.41 0.25 91.69 1.31 98.28 0.48 100.00 0.00 96.81 0.98 96.23 0.00 92.69 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.1498438072
96.78 0.33 99.41 0.00 91.69 0.00 98.28 0.00 100.00 0.00 96.81 0.00 97.10 0.87 94.15 1.46 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1417555389
97.02 0.24 99.41 0.00 92.16 0.48 98.28 0.00 100.00 0.00 97.30 0.49 97.83 0.72 94.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.827387503
97.25 0.24 99.41 0.00 92.16 0.00 98.28 0.00 100.00 0.00 97.30 0.00 97.83 0.00 95.80 1.65 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.256487171
97.45 0.20 99.41 0.00 92.16 0.00 98.35 0.07 100.00 0.00 97.30 0.00 99.13 1.30 95.80 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2511589792
97.59 0.14 99.50 0.08 92.16 0.00 99.24 0.90 100.00 0.00 97.30 0.00 99.13 0.00 95.80 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1538656963
97.73 0.14 99.50 0.00 92.52 0.36 99.31 0.07 100.00 0.00 97.30 0.00 99.13 0.00 96.34 0.55 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1505633169
97.83 0.10 99.50 0.00 92.52 0.00 99.31 0.00 100.00 0.00 97.30 0.00 99.13 0.00 97.07 0.73 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1044601746
97.91 0.08 99.50 0.00 92.52 0.00 99.66 0.34 100.00 0.00 97.30 0.00 99.13 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2861481782
97.97 0.06 99.50 0.00 92.87 0.36 99.72 0.07 100.00 0.00 97.30 0.00 99.13 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.321617042
98.02 0.05 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.30 0.00 99.13 0.00 97.62 0.37 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1184504479
98.07 0.05 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.30 0.00 99.13 0.00 97.99 0.37 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.799198631
98.13 0.05 99.50 0.00 92.99 0.12 99.72 0.00 100.00 0.00 97.55 0.25 99.13 0.00 97.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3861495111
98.15 0.03 99.50 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.17 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2665699079
98.18 0.03 99.50 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.3245594388

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.836091657
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2961454932
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1865542623
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2592349479
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4137939884
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2123542280
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1374918673
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1331450675
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2063650305
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.659146916
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.842147203
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2810510077
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.134003910
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1476789261
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.876978403
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3653286277
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2115661310
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1791558730
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1499415698
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1933400399
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.924921322
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.635542597
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.882169715
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2099747160
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2661245362
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1490563585
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2092550646
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2869116774
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2678473777
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3204949723
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3975555255
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2292328038
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2889674535
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.247186029
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.667396284
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1153081631
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1993655233
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.337237194
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.244017211
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2836463942
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3737013329
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2637250070
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3419446262
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2984540253
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1360082288
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2107805313
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2796323907
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1237633944
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4206599845
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2080906914
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1304969308
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3342957503
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1564942598
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.413595119
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4016344051
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3685289565
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.995512285
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.726864060
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3434106000
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2445339761
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.747368862
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1475865326
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1915056303
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4263592003
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2962373478
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3067949848
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.404451169
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.840901588
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.689413330
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3880980809
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2692051617
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.194593880
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1606318666
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.104476305
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1389670259
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1305269003
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.365914161
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3911990236
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4234261120
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4010304823
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2605418533
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.651124039
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.641208550
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4034343920
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.223956141
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.67025025
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Total test records in report: 1087
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.321617042 Oct 12 02:37:16 AM UTC 24 Oct 12 02:37:19 AM UTC 24 36764303 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2502115505 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:20 AM UTC 24 403721476 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1538656963 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:20 AM UTC 24 1399035839 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.3245594388 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:23 AM UTC 24 5490266120 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3649104118 Oct 12 02:37:20 AM UTC 24 Oct 12 02:37:26 AM UTC 24 777998894 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.451514124 Oct 12 02:37:24 AM UTC 24 Oct 12 02:37:26 AM UTC 24 43637094 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1312818615 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:26 AM UTC 24 11296963659 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.229923185 Oct 12 02:37:23 AM UTC 24 Oct 12 02:37:27 AM UTC 24 180527278 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1092857064 Oct 12 02:37:16 AM UTC 24 Oct 12 02:37:29 AM UTC 24 1852725693 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3448994480 Oct 12 02:37:19 AM UTC 24 Oct 12 02:37:31 AM UTC 24 9802519238 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.453232048 Oct 12 02:37:16 AM UTC 24 Oct 12 02:37:33 AM UTC 24 818879817 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1983919530 Oct 12 02:37:27 AM UTC 24 Oct 12 02:37:34 AM UTC 24 1349503526 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.2892747008 Oct 12 02:37:23 AM UTC 24 Oct 12 02:37:34 AM UTC 24 670892832 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.542944982 Oct 12 02:37:32 AM UTC 24 Oct 12 02:37:35 AM UTC 24 14812992 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4252954138 Oct 12 02:37:32 AM UTC 24 Oct 12 02:37:38 AM UTC 24 317824863 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.72699600 Oct 12 02:37:14 AM UTC 24 Oct 12 02:37:39 AM UTC 24 1485467416 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2861481782 Oct 12 02:37:13 AM UTC 24 Oct 12 02:37:41 AM UTC 24 940220031 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.3234882286 Oct 12 02:37:24 AM UTC 24 Oct 12 02:37:42 AM UTC 24 4938492108 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.1498438072 Oct 12 02:37:30 AM UTC 24 Oct 12 02:37:42 AM UTC 24 711101115 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.916845219 Oct 12 02:37:18 AM UTC 24 Oct 12 02:37:46 AM UTC 24 755181147 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.656388728 Oct 12 02:37:27 AM UTC 24 Oct 12 02:37:46 AM UTC 24 2521175605 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3405641170 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:48 AM UTC 24 5053677619 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2859052747 Oct 12 02:37:43 AM UTC 24 Oct 12 02:37:50 AM UTC 24 344509696 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1973959156 Oct 12 02:37:15 AM UTC 24 Oct 12 02:37:50 AM UTC 24 4786493372 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1964005652 Oct 12 02:37:51 AM UTC 24 Oct 12 02:37:53 AM UTC 24 22322624 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3528466019 Oct 12 02:37:31 AM UTC 24 Oct 12 02:37:53 AM UTC 24 2417682682 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4061189877 Oct 12 02:37:50 AM UTC 24 Oct 12 02:37:56 AM UTC 24 356763308 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1361667389 Oct 12 02:37:23 AM UTC 24 Oct 12 02:37:59 AM UTC 24 7738780578 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3289728037 Oct 12 02:37:47 AM UTC 24 Oct 12 02:38:01 AM UTC 24 2995455910 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.3212896833 Oct 12 02:37:33 AM UTC 24 Oct 12 02:38:06 AM UTC 24 2737062071 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1128873753 Oct 12 02:37:51 AM UTC 24 Oct 12 02:38:06 AM UTC 24 549184954 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.642789153 Oct 12 02:37:35 AM UTC 24 Oct 12 02:38:20 AM UTC 24 2051475811 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3572044983 Oct 12 02:37:15 AM UTC 24 Oct 12 02:38:22 AM UTC 24 794610985 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.480657342 Oct 12 02:38:02 AM UTC 24 Oct 12 02:38:24 AM UTC 24 11266755131 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.4197766465 Oct 12 02:37:19 AM UTC 24 Oct 12 02:38:24 AM UTC 24 18591627239 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1796354550 Oct 12 02:38:20 AM UTC 24 Oct 12 02:38:27 AM UTC 24 1345463555 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1337858291 Oct 12 02:37:26 AM UTC 24 Oct 12 02:38:34 AM UTC 24 3872550326 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.350121433 Oct 12 02:38:25 AM UTC 24 Oct 12 02:38:34 AM UTC 24 676944737 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.207605142 Oct 12 02:37:57 AM UTC 24 Oct 12 02:38:38 AM UTC 24 5649813464 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3500285450 Oct 12 02:38:35 AM UTC 24 Oct 12 02:38:39 AM UTC 24 182894241 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.759663160 Oct 12 02:38:39 AM UTC 24 Oct 12 02:38:41 AM UTC 24 15645381 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.4143718523 Oct 12 02:37:36 AM UTC 24 Oct 12 02:38:51 AM UTC 24 3144686560 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3009565664 Oct 12 02:37:27 AM UTC 24 Oct 12 02:38:59 AM UTC 24 63170077223 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.4026632313 Oct 12 02:38:03 AM UTC 24 Oct 12 02:39:04 AM UTC 24 15317366137 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.2537683534 Oct 12 02:38:40 AM UTC 24 Oct 12 02:39:05 AM UTC 24 974935818 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3781553941 Oct 12 02:37:37 AM UTC 24 Oct 12 02:39:09 AM UTC 24 3206306557 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2298730476 Oct 12 02:37:47 AM UTC 24 Oct 12 02:39:12 AM UTC 24 8172938289 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3528926428 Oct 12 02:37:40 AM UTC 24 Oct 12 02:39:19 AM UTC 24 21238430420 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2102769046 Oct 12 02:37:27 AM UTC 24 Oct 12 02:39:21 AM UTC 24 827823239 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3416576137 Oct 12 02:39:10 AM UTC 24 Oct 12 02:39:23 AM UTC 24 685901574 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.460670562 Oct 12 02:37:29 AM UTC 24 Oct 12 02:39:36 AM UTC 24 32783344363 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.672187507 Oct 12 02:39:36 AM UTC 24 Oct 12 02:39:44 AM UTC 24 1348640741 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.250152588 Oct 12 02:37:43 AM UTC 24 Oct 12 02:39:47 AM UTC 24 2039040269 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2932837194 Oct 12 02:37:48 AM UTC 24 Oct 12 02:39:47 AM UTC 24 2557922740 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.810769562 Oct 12 02:37:21 AM UTC 24 Oct 12 02:39:57 AM UTC 24 9394051199 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2718406938 Oct 12 02:39:49 AM UTC 24 Oct 12 02:40:01 AM UTC 24 664901678 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1417555389 Oct 12 02:37:21 AM UTC 24 Oct 12 02:40:03 AM UTC 24 4537681904 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.694253763 Oct 12 02:38:00 AM UTC 24 Oct 12 02:40:05 AM UTC 24 3182450967 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3492382655 Oct 12 02:40:04 AM UTC 24 Oct 12 02:40:06 AM UTC 24 41413170 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.247467664 Oct 12 02:39:00 AM UTC 24 Oct 12 02:40:09 AM UTC 24 498569270 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.101099393 Oct 12 02:38:28 AM UTC 24 Oct 12 02:40:09 AM UTC 24 3993583149 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3572064110 Oct 12 02:39:06 AM UTC 24 Oct 12 02:40:18 AM UTC 24 763404615 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3310690073 Oct 12 02:37:15 AM UTC 24 Oct 12 02:40:29 AM UTC 24 9818003783 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.434931579 Oct 12 02:37:57 AM UTC 24 Oct 12 02:40:31 AM UTC 24 24219927984 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2852727064 Oct 12 02:37:29 AM UTC 24 Oct 12 02:40:35 AM UTC 24 13830461339 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3276117518 Oct 12 02:40:18 AM UTC 24 Oct 12 02:40:48 AM UTC 24 1225670757 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1766951297 Oct 12 02:38:25 AM UTC 24 Oct 12 02:40:48 AM UTC 24 1596491792 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3636922935 Oct 12 02:37:35 AM UTC 24 Oct 12 02:40:56 AM UTC 24 3194856984 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3447369449 Oct 12 02:37:25 AM UTC 24 Oct 12 02:41:02 AM UTC 24 3714066900 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.940337369 Oct 12 02:40:36 AM UTC 24 Oct 12 02:41:06 AM UTC 24 14120367030 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1320563217 Oct 12 02:40:49 AM UTC 24 Oct 12 02:41:09 AM UTC 24 6980367156 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.91951599 Oct 12 02:41:06 AM UTC 24 Oct 12 02:41:12 AM UTC 24 363719983 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1497274529 Oct 12 02:39:48 AM UTC 24 Oct 12 02:41:22 AM UTC 24 10915717574 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.2642151413 Oct 12 02:41:22 AM UTC 24 Oct 12 02:41:33 AM UTC 24 2646750521 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2529407613 Oct 12 02:40:06 AM UTC 24 Oct 12 02:41:40 AM UTC 24 1162893737 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.86458888 Oct 12 02:40:33 AM UTC 24 Oct 12 02:41:46 AM UTC 24 758252163 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3611036482 Oct 12 02:41:47 AM UTC 24 Oct 12 02:41:49 AM UTC 24 15407668 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.651422457 Oct 12 02:40:07 AM UTC 24 Oct 12 02:41:56 AM UTC 24 6136458093 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2194201813 Oct 12 02:41:50 AM UTC 24 Oct 12 02:42:03 AM UTC 24 452365726 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1798689018 Oct 12 02:37:14 AM UTC 24 Oct 12 02:42:04 AM UTC 24 7308412253 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3033224457 Oct 12 02:41:33 AM UTC 24 Oct 12 02:42:08 AM UTC 24 2477423146 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1560635525 Oct 12 02:37:18 AM UTC 24 Oct 12 02:42:17 AM UTC 24 10613550092 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1505633169 Oct 12 02:39:13 AM UTC 24 Oct 12 02:42:23 AM UTC 24 17936618762 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1138310355 Oct 12 02:37:54 AM UTC 24 Oct 12 02:42:24 AM UTC 24 3647246327 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2739042285 Oct 12 02:37:16 AM UTC 24 Oct 12 02:42:27 AM UTC 24 6717358112 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.266182616 Oct 12 02:39:58 AM UTC 24 Oct 12 02:42:31 AM UTC 24 2308500587 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.520861422 Oct 12 02:42:24 AM UTC 24 Oct 12 02:42:35 AM UTC 24 2819710116 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1665134338 Oct 12 02:42:27 AM UTC 24 Oct 12 02:42:39 AM UTC 24 1592538789 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.2861654129 Oct 12 02:37:27 AM UTC 24 Oct 12 02:42:49 AM UTC 24 2453726423 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.322838943 Oct 12 02:41:12 AM UTC 24 Oct 12 02:42:49 AM UTC 24 8653760597 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2577037382 Oct 12 02:42:50 AM UTC 24 Oct 12 02:42:55 AM UTC 24 4176397910 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.501949469 Oct 12 02:42:25 AM UTC 24 Oct 12 02:43:03 AM UTC 24 3038005632 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.3821403637 Oct 12 02:43:04 AM UTC 24 Oct 12 02:43:16 AM UTC 24 1380194578 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2945940518 Oct 12 02:37:42 AM UTC 24 Oct 12 02:43:22 AM UTC 24 6779885961 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1556752812 Oct 12 02:42:09 AM UTC 24 Oct 12 02:43:32 AM UTC 24 551343578 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.982570320 Oct 12 02:43:33 AM UTC 24 Oct 12 02:43:35 AM UTC 24 14997473 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2461974394 Oct 12 02:39:20 AM UTC 24 Oct 12 02:43:50 AM UTC 24 4863591863 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2710219864 Oct 12 02:37:16 AM UTC 24 Oct 12 02:43:54 AM UTC 24 5374828559 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3052853927 Oct 12 02:43:16 AM UTC 24 Oct 12 02:44:03 AM UTC 24 4030730526 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.273625659 Oct 12 02:41:10 AM UTC 24 Oct 12 02:44:21 AM UTC 24 41342732729 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1153862915 Oct 12 02:37:15 AM UTC 24 Oct 12 02:44:24 AM UTC 24 89836749104 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.862551318 Oct 12 02:38:52 AM UTC 24 Oct 12 02:44:25 AM UTC 24 15113515955 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2886023916 Oct 12 02:43:37 AM UTC 24 Oct 12 02:44:33 AM UTC 24 5831179403 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4044451927 Oct 12 02:44:23 AM UTC 24 Oct 12 02:44:44 AM UTC 24 529491714 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.360844208 Oct 12 02:44:34 AM UTC 24 Oct 12 02:44:57 AM UTC 24 1430496934 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1466993666 Oct 12 02:37:27 AM UTC 24 Oct 12 02:45:04 AM UTC 24 7417709708 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2507217078 Oct 12 02:44:26 AM UTC 24 Oct 12 02:45:27 AM UTC 24 1525152858 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1120377800 Oct 12 02:38:23 AM UTC 24 Oct 12 02:45:32 AM UTC 24 13825265084 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3230440222 Oct 12 02:45:28 AM UTC 24 Oct 12 02:45:35 AM UTC 24 422703569 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.591861509 Oct 12 02:39:05 AM UTC 24 Oct 12 02:45:39 AM UTC 24 65434962487 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.640402962 Oct 12 02:42:56 AM UTC 24 Oct 12 02:45:41 AM UTC 24 4483160012 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.445302204 Oct 12 02:45:40 AM UTC 24 Oct 12 02:45:52 AM UTC 24 1346587586 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2958378761 Oct 12 02:45:53 AM UTC 24 Oct 12 02:45:55 AM UTC 24 20327803 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.829698245 Oct 12 02:45:41 AM UTC 24 Oct 12 02:46:02 AM UTC 24 494207263 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1916974593 Oct 12 02:44:46 AM UTC 24 Oct 12 02:46:20 AM UTC 24 13271749776 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2448275495 Oct 12 02:37:15 AM UTC 24 Oct 12 02:46:24 AM UTC 24 5139598291 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2000720886 Oct 12 02:37:15 AM UTC 24 Oct 12 02:46:27 AM UTC 24 8216138086 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3433004350 Oct 12 02:37:36 AM UTC 24 Oct 12 02:46:37 AM UTC 24 16286950917 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1655538812 Oct 12 02:39:46 AM UTC 24 Oct 12 02:46:39 AM UTC 24 138030142934 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2272149152 Oct 12 02:37:19 AM UTC 24 Oct 12 02:46:50 AM UTC 24 54074916287 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4020525566 Oct 12 02:37:24 AM UTC 24 Oct 12 02:46:55 AM UTC 24 102148993056 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3460577598 Oct 12 02:40:10 AM UTC 24 Oct 12 02:46:55 AM UTC 24 13842387556 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3586487415 Oct 12 02:46:29 AM UTC 24 Oct 12 02:46:58 AM UTC 24 1308916703 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4273833542 Oct 12 02:37:15 AM UTC 24 Oct 12 02:46:59 AM UTC 24 12787897612 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.3110057160 Oct 12 02:37:42 AM UTC 24 Oct 12 02:47:12 AM UTC 24 12560370262 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1983330438 Oct 12 02:47:13 AM UTC 24 Oct 12 02:47:20 AM UTC 24 351198571 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.682814367 Oct 12 02:38:06 AM UTC 24 Oct 12 02:47:29 AM UTC 24 33872617985 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3539055640 Oct 12 02:45:56 AM UTC 24 Oct 12 02:47:35 AM UTC 24 4976244204 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2091545806 Oct 12 02:37:20 AM UTC 24 Oct 12 02:47:36 AM UTC 24 4180939872 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.2580865466 Oct 12 02:47:36 AM UTC 24 Oct 12 02:47:48 AM UTC 24 2648716112 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2315863853 Oct 12 02:46:56 AM UTC 24 Oct 12 02:47:58 AM UTC 24 17594395739 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.887280719 Oct 12 02:41:57 AM UTC 24 Oct 12 02:47:58 AM UTC 24 12667829715 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3885385253 Oct 12 02:47:59 AM UTC 24 Oct 12 02:48:01 AM UTC 24 16920747 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2332473430 Oct 12 02:42:05 AM UTC 24 Oct 12 02:48:20 AM UTC 24 35393567891 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3650789259 Oct 12 02:37:20 AM UTC 24 Oct 12 02:50:49 AM UTC 24 13338421163 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2956516992 Oct 12 02:39:24 AM UTC 24 Oct 12 02:48:23 AM UTC 24 19106156621 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2899992746 Oct 12 02:45:36 AM UTC 24 Oct 12 02:48:24 AM UTC 24 41039281257 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2561324424 Oct 12 02:40:49 AM UTC 24 Oct 12 02:48:28 AM UTC 24 9143512720 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2802437948 Oct 12 02:46:51 AM UTC 24 Oct 12 02:48:29 AM UTC 24 3061178517 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3731226366 Oct 12 02:48:00 AM UTC 24 Oct 12 02:48:29 AM UTC 24 15152608458 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1037142204 Oct 12 02:46:40 AM UTC 24 Oct 12 02:48:32 AM UTC 24 802141992 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2892049062 Oct 12 02:46:56 AM UTC 24 Oct 12 02:48:43 AM UTC 24 7982464252 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.4135388703 Oct 12 02:42:50 AM UTC 24 Oct 12 02:48:44 AM UTC 24 114855705739 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3135453630 Oct 12 02:48:25 AM UTC 24 Oct 12 02:48:54 AM UTC 24 5272532707 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3180598845 Oct 12 02:48:30 AM UTC 24 Oct 12 02:48:54 AM UTC 24 730807099 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3474714115 Oct 12 02:45:32 AM UTC 24 Oct 12 02:48:56 AM UTC 24 14097070549 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3870715648 Oct 12 02:40:30 AM UTC 24 Oct 12 02:49:00 AM UTC 24 18318444315 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1486625608 Oct 12 02:48:55 AM UTC 24 Oct 12 02:49:01 AM UTC 24 3036423352 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.4080939148 Oct 12 02:49:01 AM UTC 24 Oct 12 02:49:11 AM UTC 24 693865226 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.4109658632 Oct 12 02:46:03 AM UTC 24 Oct 12 02:49:15 AM UTC 24 11279563227 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3778529664 Oct 12 02:47:37 AM UTC 24 Oct 12 02:49:34 AM UTC 24 9337350662 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2039018475 Oct 12 02:49:35 AM UTC 24 Oct 12 02:49:37 AM UTC 24 63987141 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3109139883 Oct 12 02:49:12 AM UTC 24 Oct 12 02:49:39 AM UTC 24 1599409356 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1128043223 Oct 12 02:48:33 AM UTC 24 Oct 12 02:49:49 AM UTC 24 10561743356 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.750002823 Oct 12 02:47:30 AM UTC 24 Oct 12 02:50:01 AM UTC 24 10208880474 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3240339000 Oct 12 02:48:31 AM UTC 24 Oct 12 02:50:05 AM UTC 24 899203734 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1333876349 Oct 12 02:49:00 AM UTC 24 Oct 12 02:50:26 AM UTC 24 2751903821 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1939644207 Oct 12 02:50:06 AM UTC 24 Oct 12 02:50:52 AM UTC 24 1932331548 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3310502467 Oct 12 02:44:04 AM UTC 24 Oct 12 02:50:53 AM UTC 24 4758940766 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.261256091 Oct 12 02:49:38 AM UTC 24 Oct 12 02:51:13 AM UTC 24 1403584364 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1557003854 Oct 12 02:50:51 AM UTC 24 Oct 12 02:51:14 AM UTC 24 800714643 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2731605979 Oct 12 02:50:53 AM UTC 24 Oct 12 02:51:21 AM UTC 24 740430959 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.1924497362 Oct 12 02:51:15 AM UTC 24 Oct 12 02:51:42 AM UTC 24 462905602 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2638400438 Oct 12 02:42:18 AM UTC 24 Oct 12 02:51:50 AM UTC 24 19283462008 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3717559311 Oct 12 02:51:43 AM UTC 24 Oct 12 02:51:50 AM UTC 24 1260876531 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.256487171 Oct 12 02:37:27 AM UTC 24 Oct 12 02:52:16 AM UTC 24 15677486671 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2691481227 Oct 12 02:37:27 AM UTC 24 Oct 12 02:52:16 AM UTC 24 13754806135 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.1422869152 Oct 12 02:52:17 AM UTC 24 Oct 12 02:52:26 AM UTC 24 2639771885 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3603379850 Oct 12 02:48:56 AM UTC 24 Oct 12 02:52:40 AM UTC 24 28836470928 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.305335578 Oct 12 02:52:41 AM UTC 24 Oct 12 02:52:43 AM UTC 24 21976051 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1093356367 Oct 12 02:50:54 AM UTC 24 Oct 12 02:52:44 AM UTC 24 45196707900 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2044300509 Oct 12 02:46:24 AM UTC 24 Oct 12 02:52:55 AM UTC 24 5131477083 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2999610391 Oct 12 02:45:04 AM UTC 24 Oct 12 02:53:13 AM UTC 24 8295294473 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2244959373 Oct 12 02:51:50 AM UTC 24 Oct 12 02:53:13 AM UTC 24 8630464834 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2598242975 Oct 12 02:52:18 AM UTC 24 Oct 12 02:53:18 AM UTC 24 1483747800 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3452622049 Oct 12 02:53:14 AM UTC 24 Oct 12 02:53:35 AM UTC 24 4270319841 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3025033799 Oct 12 02:46:38 AM UTC 24 Oct 12 02:53:47 AM UTC 24 21885891633 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3726538684 Oct 12 02:37:52 AM UTC 24 Oct 12 02:53:56 AM UTC 24 19863083675 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1730431161 Oct 12 02:50:02 AM UTC 24 Oct 12 02:53:59 AM UTC 24 6648153986 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3924187944 Oct 12 02:37:15 AM UTC 24 Oct 12 02:54:01 AM UTC 24 7060635180 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1839047604 Oct 12 02:38:42 AM UTC 24 Oct 12 02:54:02 AM UTC 24 39561507472 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1235298767 Oct 12 02:53:48 AM UTC 24 Oct 12 02:54:07 AM UTC 24 732975053 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.183512292 Oct 12 02:48:24 AM UTC 24 Oct 12 02:54:11 AM UTC 24 44827537015 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1888860726 Oct 12 02:54:08 AM UTC 24 Oct 12 02:54:15 AM UTC 24 1300413949 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2634660589 Oct 12 02:47:21 AM UTC 24 Oct 12 02:54:32 AM UTC 24 55277917989 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2767360152 Oct 12 02:39:22 AM UTC 24 Oct 12 02:54:45 AM UTC 24 31830883341 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.3186223221 Oct 12 02:54:34 AM UTC 24 Oct 12 02:54:46 AM UTC 24 1378105564 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.4095242779 Oct 12 02:52:44 AM UTC 24 Oct 12 02:54:49 AM UTC 24 3830937503 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.970569604 Oct 12 02:54:50 AM UTC 24 Oct 12 02:54:52 AM UTC 24 14078327 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2687336662 Oct 12 02:54:46 AM UTC 24 Oct 12 02:54:53 AM UTC 24 251019339 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1881923859 Oct 12 02:42:04 AM UTC 24 Oct 12 02:55:01 AM UTC 24 405231945596 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3001618018 Oct 12 02:53:36 AM UTC 24 Oct 12 02:55:18 AM UTC 24 799262629 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2311991507 Oct 12 02:54:53 AM UTC 24 Oct 12 02:55:19 AM UTC 24 1974732656 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.720251823 Oct 12 02:41:03 AM UTC 24 Oct 12 02:55:24 AM UTC 24 9290630292 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3763461367 Oct 12 02:53:57 AM UTC 24 Oct 12 02:55:31 AM UTC 24 12587385479 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3897321684 Oct 12 02:54:00 AM UTC 24 Oct 12 02:55:37 AM UTC 24 3995169957 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.753669581 Oct 12 02:55:19 AM UTC 24 Oct 12 02:55:42 AM UTC 24 9317951076 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1840482246 Oct 12 02:55:33 AM UTC 24 Oct 12 02:55:57 AM UTC 24 1468550976 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.705013219 Oct 12 02:37:32 AM UTC 24 Oct 12 02:56:05 AM UTC 24 25713660110 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1882002138 Oct 12 02:48:44 AM UTC 24 Oct 12 02:56:05 AM UTC 24 32557080664 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2711543069 Oct 12 02:44:58 AM UTC 24 Oct 12 02:56:11 AM UTC 24 15805192866 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2675795103 Oct 12 02:50:26 AM UTC 24 Oct 12 02:56:16 AM UTC 24 10777474769 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4139167861 Oct 12 02:56:12 AM UTC 24 Oct 12 02:56:19 AM UTC 24 345776038 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1057754392 Oct 12 02:48:29 AM UTC 24 Oct 12 02:56:21 AM UTC 24 33015284412 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.3891565255 Oct 12 02:56:06 AM UTC 24 Oct 12 02:56:25 AM UTC 24 1050041267 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1483833467 Oct 12 02:55:38 AM UTC 24 Oct 12 02:56:27 AM UTC 24 1540560725 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3422650629 Oct 12 02:56:22 AM UTC 24 Oct 12 02:56:31 AM UTC 24 2881071068 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3655797422 Oct 12 02:56:32 AM UTC 24 Oct 12 02:56:34 AM UTC 24 40870338 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.982244383 Oct 12 02:55:43 AM UTC 24 Oct 12 02:56:39 AM UTC 24 8081612415 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1348885717 Oct 12 02:38:07 AM UTC 24 Oct 12 02:56:40 AM UTC 24 9699577478 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2319811356 Oct 12 02:56:25 AM UTC 24 Oct 12 02:56:40 AM UTC 24 998091846 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.37134525 Oct 12 02:56:35 AM UTC 24 Oct 12 02:56:51 AM UTC 24 433469861 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4196903743 Oct 12 02:44:26 AM UTC 24 Oct 12 02:57:02 AM UTC 24 268327090539 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2317481764 Oct 12 02:56:51 AM UTC 24 Oct 12 02:57:04 AM UTC 24 744475519 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2227666209 Oct 12 02:54:16 AM UTC 24 Oct 12 02:57:13 AM UTC 24 7839935564 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3510733677 Oct 12 02:43:51 AM UTC 24 Oct 12 02:57:18 AM UTC 24 88772537130 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1213888719 Oct 12 02:57:05 AM UTC 24 Oct 12 02:57:24 AM UTC 24 726270071 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.714016193 Oct 12 02:57:14 AM UTC 24 Oct 12 02:57:31 AM UTC 24 6806544796 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2935924921 Oct 12 02:37:41 AM UTC 24 Oct 12 02:57:38 AM UTC 24 16181352029 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1296112997 Oct 12 02:46:59 AM UTC 24 Oct 12 02:57:44 AM UTC 24 9615990544 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.690719523 Oct 12 02:52:45 AM UTC 24 Oct 12 02:57:44 AM UTC 24 21728071939 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1443117174 Oct 12 02:56:19 AM UTC 24 Oct 12 02:57:45 AM UTC 24 2836441102 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2708302638 Oct 12 02:57:18 AM UTC 24 Oct 12 02:57:45 AM UTC 24 6647659893 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2267056906 Oct 12 02:57:45 AM UTC 24 Oct 12 02:57:52 AM UTC 24 404876218 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.709900932 Oct 12 02:57:46 AM UTC 24 Oct 12 02:57:57 AM UTC 24 1357983952 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2077919312 Oct 12 02:54:11 AM UTC 24 Oct 12 02:58:15 AM UTC 24 10798339000 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2412838245 Oct 12 02:58:16 AM UTC 24 Oct 12 02:58:19 AM UTC 24 165110273 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.276371954 Oct 12 02:53:13 AM UTC 24 Oct 12 02:58:37 AM UTC 24 18929704624 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.129999939 Oct 12 02:44:54 AM UTC 24 Oct 12 02:58:37 AM UTC 24 145335259687 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3006326824 Oct 12 02:38:18 AM UTC 24 Oct 12 02:58:50 AM UTC 24 17760997378 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.1049214503 Oct 12 02:58:19 AM UTC 24 Oct 12 02:58:55 AM UTC 24 1416660744 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3805112570 Oct 12 02:57:53 AM UTC 24 Oct 12 02:58:58 AM UTC 24 1730018442 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3701517819 Oct 12 02:58:56 AM UTC 24 Oct 12 02:59:11 AM UTC 24 1851259222 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2114457673 Oct 12 02:51:50 AM UTC 24 Oct 12 02:59:14 AM UTC 24 57549709142 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3859602188 Oct 12 02:49:40 AM UTC 24 Oct 12 02:59:33 AM UTC 24 87248855139 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1890088256 Oct 12 02:54:54 AM UTC 24 Oct 12 02:59:40 AM UTC 24 7944339769 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.4178684978 Oct 12 02:42:36 AM UTC 24 Oct 12 02:59:43 AM UTC 24 28656046442 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2293678014 Oct 12 02:55:18 AM UTC 24 Oct 12 02:59:48 AM UTC 24 6306758861 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3038097803 Oct 12 02:59:12 AM UTC 24 Oct 12 03:00:12 AM UTC 24 14592760754 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1820763559 Oct 12 03:00:13 AM UTC 24 Oct 12 03:00:18 AM UTC 24 346829056 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3025020803 Oct 12 02:59:15 AM UTC 24 Oct 12 03:00:29 AM UTC 24 765245262 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3753523759 Oct 12 02:56:17 AM UTC 24 Oct 12 03:00:32 AM UTC 24 41398718268 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.963669344 Oct 12 02:55:25 AM UTC 24 Oct 12 03:00:36 AM UTC 24 19703870444 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3239332595 Oct 12 03:00:32 AM UTC 24 Oct 12 03:00:46 AM UTC 24 7343244050 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.827387503 Oct 12 03:00:36 AM UTC 24 Oct 12 03:00:56 AM UTC 24 687400587 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2425339971 Oct 12 03:00:56 AM UTC 24 Oct 12 03:00:58 AM UTC 24 12753737 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3409796144 Oct 12 02:37:34 AM UTC 24 Oct 12 03:01:15 AM UTC 24 75225837912 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.538966028 Oct 12 02:48:55 AM UTC 24 Oct 12 03:01:18 AM UTC 24 27878287536 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.3338407781 Oct 12 03:01:00 AM UTC 24 Oct 12 03:01:20 AM UTC 24 3407007602 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2943751409 Oct 12 02:53:20 AM UTC 24 Oct 12 03:01:20 AM UTC 24 36379803757 ps
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