Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	351116128	1			T1	5752		T2	13176		T4	15996
instr_valid_dis	316745541	1			T1	5752		T2	13176		T4	15996
instr_en	25943840	1			T26	53324		T27	328910		T42	99934

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10396256	1			T26	70046		T27	112538		T42	18980
sram_ifetch_valid_disable	318236367	1			T1	5752		T2	13176		T4	15996
sram_ifetch_enable	22483505	1			T26	77462		T27	107638		T42	73208

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	351116128	1			T1	5752		T2	13176		T4	15996
hw_debug_en_valid_off	314516734	1			T1	5752		T2	13176		T4	15996
hw_debug_en_on	24474200	1			T12	14768		T26	45064		T27	157056

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	318236367	1			T1	5752		T2	13176		T4	15996
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	301379439	1			T1	5752		T2	13176		T4	15996
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13328840	1			T26	25796		T27	108734		T42	35198
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4123810	1			T26	34328		T27	14582		T42	16746
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2219146	1			T26	34328		T19	19714		T147	45020
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1291428	1			T27	14582		T42	16746		T148	24632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3843426	1			T26	35666		T27	43532		T42	2234
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1516216	1			T26	35666		T19	13898		T153	44776
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1828532	1			T27	43532		T42	2234		T18	19522
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11126988	1			T12	14768		T27	59066		T42	55066
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6295252	1			T42	25700		T18	13466		T19	5386
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3496408	1			T27	59066		T42	29366		T18	29040

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8187430	1			T26	27476		T27	107638		T42	45756
lc_exec_en	9503786	1			T26	9398		T27	54458		T42	38742
valid_exec_dis	312740379	1			T1	5752		T2	13176		T4	15996
invalid_exec_dis	32879761	1			T26	147508		T27	220176		T42	92188