Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	350704711	1			T1	184		T3	1958		T4	52
instr_valid_dis	308923113	1			T1	184		T3	1958		T4	52
instr_en	30247678	1			T27	243186		T28	12138		T160	188800

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13136050	1			T27	45016		T28	12138		T160	37998
sram_ifetch_valid_disable	310990940	1			T1	184		T3	1958		T4	52
sram_ifetch_enable	26577721	1			T29	19649		T27	113708		T28	88888

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	350704711	1			T1	184		T3	1958		T4	52
hw_debug_en_valid_off	311396806	1			T1	184		T3	1958		T4	52
hw_debug_en_on	24960417	1			T27	60768		T28	77952		T18	14910

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	310990940	1			T1	184		T3	1958		T4	52
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	292501092	1			T1	184		T3	1958		T4	52
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13747350	1			T27	84462		T157	103758		T162	108838
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4962984	1			T27	26916		T28	12138		T133	19410
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2395906	1			T133	19410		T19	20086		T164	34978
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1945478	1			T27	26916		T28	12138		T157	1434
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5800694	1			T160	37998		T133	13122		T162	31544
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3358232	1			T133	13122		T158	20482		T155	8278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2052584	1			T160	37998		T162	31544		T155	29100
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10394261	1			T27	922		T28	1178		T133	82168
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5857356	1			T133	82168		T19	24502		T157	37000
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3464297	1			T27	922		T157	83758		T162	99582

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11137812	1			T27	113708		T160	150802		T157	68404
lc_exec_en	8765462	1			T27	59846		T28	76774		T18	14910
valid_exec_dis	305047526	1			T1	184		T3	1958		T4	52
invalid_exec_dis	39713771	1			T29	19649		T27	158724		T28	101026