Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.00 99.19 94.49 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1034
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.02 85.02 96.32 96.32 82.90 82.90 93.53 93.53 66.67 66.67 87.91 87.91 94.30 94.30 73.49 73.49 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.131444064
89.16 4.15 97.55 1.23 85.27 2.38 96.21 2.69 80.95 14.29 91.00 3.08 95.47 1.17 77.70 4.20 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.577782588
92.38 3.22 98.53 0.98 85.27 0.00 97.11 0.90 100.00 19.05 92.42 1.42 95.47 0.00 77.88 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.4234288666
93.92 1.54 98.53 0.00 87.65 2.38 97.45 0.34 100.00 0.00 94.08 1.66 95.47 0.00 84.28 6.40 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1391253482
94.98 1.06 98.69 0.16 88.48 0.83 97.66 0.21 100.00 0.00 94.79 0.71 96.05 0.58 89.21 4.94 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3875943523
95.72 0.74 98.86 0.16 90.50 2.02 98.42 0.76 100.00 0.00 95.50 0.71 96.64 0.58 90.13 0.91 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.235846017
96.31 0.59 99.10 0.25 90.50 0.00 98.42 0.00 100.00 0.00 95.73 0.24 96.78 0.15 93.60 3.47 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1998663371
96.51 0.21 99.10 0.00 90.62 0.12 98.48 0.07 100.00 0.00 95.73 0.00 96.78 0.00 94.88 1.28 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3807116154
96.71 0.20 99.10 0.00 90.62 0.00 98.55 0.07 100.00 0.00 95.73 0.00 98.10 1.32 94.88 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2647624883
96.85 0.14 99.10 0.00 90.62 0.00 98.62 0.07 100.00 0.00 95.73 0.00 98.98 0.88 94.88 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2225295582
96.98 0.13 99.18 0.08 90.62 0.00 99.45 0.83 100.00 0.00 95.73 0.00 98.98 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2657751779
97.10 0.12 99.18 0.00 90.86 0.24 99.45 0.00 100.00 0.00 96.21 0.47 99.12 0.15 94.88 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3810260473
97.20 0.10 99.18 0.00 90.86 0.00 99.45 0.00 100.00 0.00 96.21 0.00 99.12 0.00 95.61 0.73 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594800708
97.31 0.10 99.18 0.00 90.86 0.00 99.45 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.34 0.73 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3423595225
97.38 0.07 99.18 0.00 91.21 0.36 99.59 0.14 100.00 0.00 96.21 0.00 99.12 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2924235063
97.44 0.06 99.18 0.00 91.33 0.12 99.72 0.14 100.00 0.00 96.21 0.00 99.12 0.00 96.53 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3541301807
97.49 0.05 99.18 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2681023888
97.52 0.03 99.18 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2708648398
97.55 0.03 99.18 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1887419023
97.57 0.03 99.18 0.00 91.33 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.4027976402

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.511986542
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1926564144
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1396804040
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3803987788
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2278086019
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.908835872
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1339827093
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2760018587
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3668971882
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3515718892
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3145584366
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4162278403
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3649140971
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4249414938
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1181933087
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3004193061
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.59764951
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4187662777
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2064098175
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.344618374
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3040727561
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4279034655
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2306101128
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2150396975
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3899733114
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3195721300
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.223365279
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.910450779
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.136575115
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4163776834
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.592531579
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4142826836
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3059178695
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2522114917
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1863185056
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2721084634
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3066366662
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.112594984
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.722410766
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1513941916
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3175788529
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1408119047
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1640121793
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2168218406
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.668327961
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1771996384
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2095396532
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1423211900
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.785044860
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2598023772
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1625266400
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1562848506
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2700584102
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2310962814
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.771367296
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2304091762
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2852411986
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4182201323
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2497514508
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3420428491
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3696777065
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.700514490
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.480015766
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1452049007
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4415388
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.248210046
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1119615641
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3023261508
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3446389192
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2740709964
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3565584142
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1205134655
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2672275696
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3070021338
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1385360010
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4076058444
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1100451006
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3568126881
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4018065477
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1333675183
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1481983889
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3585206945
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2705779020
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1674342743
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2496768197
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.567981444
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.415262454
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4116671992
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2312213079
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.256940106
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2799504064
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3732704078
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1459336051
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1548359975
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4041308992
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.895591805
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.300325681
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1418206608
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3664601474
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.471481008
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1774328768
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2021503197
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1741197795
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2372037405
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/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2160347672
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.952994661
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.4050398031
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.783278463
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2631251957
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.829821043
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.18574473
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3004946803
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1054893089
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2453125048
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2881153038
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1980142624
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1271596236
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3553066791
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4006996191
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3725511662
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.4256584908
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3237231028
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.385060415
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3380341776
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3526405756
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2681485788
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.792766370
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2046866713
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3851468364
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3419850107
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3414171828
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.4267876514
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1328185196
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3378928380
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1792634667
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2137322495
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1612876798
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2644952200
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.4069823300
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3125975154
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2523597639
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2338477573
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.296442239
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.118857928
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.118246542
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.726246039
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.481873582
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1366213695
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.828657066
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3907296773
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1052674047
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3092620512
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.735931739
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3284472789
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.59643205
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1864383891
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1506358747
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3680415262
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2359321682
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1457172166
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1773264428
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2534398808
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1845346929
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3730613271
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.184034167
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4243601165
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.19463090
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3026711449
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2258132708
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3687623703
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4109622897
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2592158910
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.578021252
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2065363612
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.425951711
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1177433447
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3116900410
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.340005709
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2799346807
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.841117055
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.711037656
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2132134185
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3650285326
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1662457659
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.590250329
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.4292011985
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.260818569
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1749707749
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.422907832
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1767270239
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2908543077
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3734705637
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3964573118
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1321163608
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2383894034
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3951692130



Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1793693299 Feb 08 02:48:44 PM UTC 25 Feb 08 02:49:04 PM UTC 25 864804323 ps
T2 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.900611871 Feb 08 02:48:44 PM UTC 25 Feb 08 02:49:14 PM UTC 25 1020694339 ps
T3 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2657751779 Feb 08 02:49:24 PM UTC 25 Feb 08 02:49:31 PM UTC 25 716601300 ps
T4 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1008507338 Feb 08 02:48:46 PM UTC 25 Feb 08 02:49:37 PM UTC 25 747073344 ps
T5 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.577782588 Feb 08 02:48:47 PM UTC 25 Feb 08 02:49:41 PM UTC 25 5455460362 ps
T9 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4186287287 Feb 08 02:48:46 PM UTC 25 Feb 08 02:49:55 PM UTC 25 780854432 ps
T10 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1276140775 Feb 08 02:49:37 PM UTC 25 Feb 08 02:51:16 PM UTC 25 2674983885 ps
T6 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.235846017 Feb 08 02:51:17 PM UTC 25 Feb 08 02:51:21 PM UTC 25 1673266143 ps
T11 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.546642001 Feb 08 02:51:22 PM UTC 25 Feb 08 02:51:24 PM UTC 25 73950644 ps
T12 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.131444064 Feb 08 02:49:42 PM UTC 25 Feb 08 02:51:26 PM UTC 25 2477816317 ps
T32 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.307494715 Feb 08 02:51:25 PM UTC 25 Feb 08 02:51:42 PM UTC 25 842849487 ps
T33 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2705580214 Feb 08 02:49:32 PM UTC 25 Feb 08 02:52:52 PM UTC 25 40687877720 ps
T34 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2145342115 Feb 08 02:53:05 PM UTC 25 Feb 08 02:53:24 PM UTC 25 2007138213 ps
T26 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.292257432 Feb 08 02:49:06 PM UTC 25 Feb 08 02:53:33 PM UTC 25 9488295775 ps
T35 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2335789205 Feb 08 02:48:44 PM UTC 25 Feb 08 02:53:50 PM UTC 25 62136134644 ps
T36 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1761574101 Feb 08 02:53:34 PM UTC 25 Feb 08 02:54:11 PM UTC 25 3130449007 ps
T37 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3929819982 Feb 08 02:53:24 PM UTC 25 Feb 08 02:54:33 PM UTC 25 1575708561 ps
T7 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1760945746 Feb 08 02:53:52 PM UTC 25 Feb 08 02:54:41 PM UTC 25 21024008537 ps
T28 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2499080317 Feb 08 02:54:48 PM UTC 25 Feb 08 02:54:54 PM UTC 25 351358457 ps
T62 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.4050277064 Feb 08 02:51:27 PM UTC 25 Feb 08 02:55:49 PM UTC 25 8269717697 ps
T38 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1998663371 Feb 08 02:48:46 PM UTC 25 Feb 08 02:56:08 PM UTC 25 18632311371 ps
T24 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.307271803 Feb 08 02:56:08 PM UTC 25 Feb 08 02:56:45 PM UTC 25 8604942535 ps
T16 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.93287499 Feb 08 02:57:23 PM UTC 25 Feb 08 02:57:29 PM UTC 25 879263548 ps
T61 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3156381863 Feb 08 02:52:53 PM UTC 25 Feb 08 02:57:31 PM UTC 25 64282689735 ps
T43 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2225295582 Feb 08 02:55:50 PM UTC 25 Feb 08 02:57:32 PM UTC 25 11113306948 ps
T13 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3110682424 Feb 08 02:57:30 PM UTC 25 Feb 08 02:57:32 PM UTC 25 15134272 ps
T78 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.4104520392 Feb 08 02:57:32 PM UTC 25 Feb 08 02:58:17 PM UTC 25 1329567920 ps
T151 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3221970278 Feb 08 02:58:17 PM UTC 25 Feb 08 02:58:24 PM UTC 25 352519431 ps
T105 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2620005456 Feb 08 02:53:10 PM UTC 25 Feb 08 02:58:26 PM UTC 25 13198398607 ps
T154 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2923071379 Feb 08 02:58:27 PM UTC 25 Feb 08 02:59:05 PM UTC 25 2612607364 ps
T27 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1391253482 Feb 08 02:49:16 PM UTC 25 Feb 08 02:59:36 PM UTC 25 29216651748 ps
T155 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4101793508 Feb 08 02:59:07 PM UTC 25 Feb 08 03:00:01 PM UTC 25 808604265 ps
T156 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.868505090 Feb 08 02:54:55 PM UTC 25 Feb 08 03:00:12 PM UTC 25 8047794159 ps
T29 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2008791447 Feb 08 03:00:23 PM UTC 25 Feb 08 03:00:29 PM UTC 25 361078380 ps
T8 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3862613525 Feb 08 02:59:37 PM UTC 25 Feb 08 03:00:45 PM UTC 25 14414502157 ps
T152 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2569890155 Feb 08 02:48:44 PM UTC 25 Feb 08 03:01:00 PM UTC 25 61759329570 ps
T25 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.8091918 Feb 08 03:00:45 PM UTC 25 Feb 08 03:01:08 PM UTC 25 637554671 ps
T17 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2844531714 Feb 08 03:01:09 PM UTC 25 Feb 08 03:01:14 PM UTC 25 711871618 ps
T15 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2844171177 Feb 08 03:01:14 PM UTC 25 Feb 08 03:01:16 PM UTC 25 25182211 ps
T157 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1403553932 Feb 08 03:01:15 PM UTC 25 Feb 08 03:02:41 PM UTC 25 5965461431 ps
T42 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3771749598 Feb 08 02:54:34 PM UTC 25 Feb 08 03:03:37 PM UTC 25 66186998875 ps
T39 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2011575188 Feb 08 02:48:47 PM UTC 25 Feb 08 03:03:39 PM UTC 25 35250072562 ps
T85 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3475387784 Feb 08 03:00:36 PM UTC 25 Feb 08 03:03:44 PM UTC 25 4521577452 ps
T106 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2415816550 Feb 08 02:57:34 PM UTC 25 Feb 08 03:04:08 PM UTC 25 4857331431 ps
T158 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3579049007 Feb 08 03:03:40 PM UTC 25 Feb 08 03:04:13 PM UTC 25 472983258 ps
T159 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.2446785400 Feb 08 02:48:44 PM UTC 25 Feb 08 03:04:32 PM UTC 25 202210482411 ps
T160 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3079371808 Feb 08 03:04:14 PM UTC 25 Feb 08 03:04:53 PM UTC 25 3043143839 ps
T161 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.390645435 Feb 08 03:04:09 PM UTC 25 Feb 08 03:05:27 PM UTC 25 1560253436 ps
T68 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3014100162 Feb 08 03:04:33 PM UTC 25 Feb 08 03:06:19 PM UTC 25 11009095606 ps
T18 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1137281902 Feb 08 03:00:23 PM UTC 25 Feb 08 03:06:48 PM UTC 25 13698286926 ps
T162 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1959387393 Feb 08 03:06:48 PM UTC 25 Feb 08 03:06:54 PM UTC 25 1408135868 ps
T19 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3807116154 Feb 08 02:54:42 PM UTC 25 Feb 08 03:07:12 PM UTC 25 65669487517 ps
T44 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.4234288666 Feb 08 03:00:30 PM UTC 25 Feb 08 03:07:19 PM UTC 25 21337047599 ps
T107 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1672857349 Feb 08 02:58:24 PM UTC 25 Feb 08 03:07:27 PM UTC 25 25365858063 ps
T147 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.921533528 Feb 08 03:05:28 PM UTC 25 Feb 08 03:07:59 PM UTC 25 6258098561 ps
T30 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1888681643 Feb 08 03:07:54 PM UTC 25 Feb 08 03:07:59 PM UTC 25 232674420 ps
T14 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1646222515 Feb 08 03:08:00 PM UTC 25 Feb 08 03:08:02 PM UTC 25 27752108 ps
T163 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.4034202269 Feb 08 03:08:00 PM UTC 25 Feb 08 03:08:23 PM UTC 25 3278880771 ps
T40 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1218804566 Feb 08 02:54:12 PM UTC 25 Feb 08 03:09:34 PM UTC 25 15841199976 ps
T164 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2502302477 Feb 08 03:09:34 PM UTC 25 Feb 08 03:09:52 PM UTC 25 3369680575 ps
T47 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.209070357 Feb 08 03:07:20 PM UTC 25 Feb 08 03:10:17 PM UTC 25 8363714498 ps
T48 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2336088044 Feb 08 03:07:12 PM UTC 25 Feb 08 03:10:31 PM UTC 25 38605572325 ps
T165 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3555007013 Feb 08 03:10:32 PM UTC 25 Feb 08 03:10:44 PM UTC 25 696062010 ps
T108 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1008569609 Feb 08 03:03:37 PM UTC 25 Feb 08 03:10:46 PM UTC 25 19506037211 ps
T21 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1118553772 Feb 08 03:10:37 PM UTC 25 Feb 08 03:11:36 PM UTC 25 30372607698 ps
T166 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2170019896 Feb 08 03:10:18 PM UTC 25 Feb 08 03:11:44 PM UTC 25 801234107 ps
T167 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.555676831 Feb 08 03:11:44 PM UTC 25 Feb 08 03:11:49 PM UTC 25 361632840 ps
T168 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.829238794 Feb 08 03:01:17 PM UTC 25 Feb 08 03:12:12 PM UTC 25 8256451357 ps
T41 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2809382840 Feb 08 03:00:02 PM UTC 25 Feb 08 03:12:29 PM UTC 25 14126742330 ps
T169 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3533840492 Feb 08 03:02:42 PM UTC 25 Feb 08 03:12:58 PM UTC 25 34462803135 ps
T170 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1440332469 Feb 08 02:57:33 PM UTC 25 Feb 08 03:13:01 PM UTC 25 25637645545 ps
T31 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.540382995 Feb 08 03:12:59 PM UTC 25 Feb 08 03:13:03 PM UTC 25 1743465993 ps
T171 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3807686632 Feb 08 03:13:02 PM UTC 25 Feb 08 03:13:04 PM UTC 25 15378837 ps
T86 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.554477052 Feb 08 03:10:45 PM UTC 25 Feb 08 03:13:06 PM UTC 25 10387158627 ps
T109 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.68079887 Feb 08 03:08:24 PM UTC 25 Feb 08 03:13:11 PM UTC 25 4486214628 ps
T172 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.385060415 Feb 08 03:13:04 PM UTC 25 Feb 08 03:13:51 PM UTC 25 502830140 ps
T87 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3422001622 Feb 08 03:12:13 PM UTC 25 Feb 08 03:13:57 PM UTC 25 10552706879 ps
T52 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3522816825 Feb 08 03:06:55 PM UTC 25 Feb 08 03:14:10 PM UTC 25 81140720612 ps
T173 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.678577854 Feb 08 03:03:44 PM UTC 25 Feb 08 03:14:24 PM UTC 25 93500006604 ps
T174 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.792766370 Feb 08 03:14:24 PM UTC 25 Feb 08 03:14:36 PM UTC 25 681371925 ps
T175 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4006996191 Feb 08 03:13:52 PM UTC 25 Feb 08 03:14:40 PM UTC 25 6511319057 ps
T176 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2881153038 Feb 08 03:14:11 PM UTC 25 Feb 08 03:15:02 PM UTC 25 784494110 ps
T88 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1795308926 Feb 08 03:04:55 PM UTC 25 Feb 08 03:15:06 PM UTC 25 22402116679 ps
T65 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.653581968 Feb 08 03:12:28 PM UTC 25 Feb 08 03:15:18 PM UTC 25 7299001493 ps
T177 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.4256584908 Feb 08 03:15:19 PM UTC 25 Feb 08 03:15:25 PM UTC 25 345143120 ps
T178 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.4227797775 Feb 08 02:51:43 PM UTC 25 Feb 08 03:15:31 PM UTC 25 73341326162 ps
T22 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3541301807 Feb 08 03:14:37 PM UTC 25 Feb 08 03:16:16 PM UTC 25 46172084667 ps
T179 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2681485788 Feb 08 03:13:12 PM UTC 25 Feb 08 03:16:46 PM UTC 25 6929230764 ps
T143 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1945110393 Feb 08 03:10:47 PM UTC 25 Feb 08 03:16:50 PM UTC 25 43192922168 ps
T180 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3004946803 Feb 08 03:16:50 PM UTC 25 Feb 08 03:16:52 PM UTC 25 18111051 ps
T142 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.1737037129 Feb 08 03:00:23 PM UTC 25 Feb 08 03:17:10 PM UTC 25 56138271846 ps
T181 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2523597639 Feb 08 03:16:53 PM UTC 25 Feb 08 03:17:11 PM UTC 25 3054391231 ps
T182 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2084169183 Feb 08 03:09:52 PM UTC 25 Feb 08 03:17:56 PM UTC 25 71529902842 ps
T45 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3258083509 Feb 08 03:11:49 PM UTC 25 Feb 08 03:18:05 PM UTC 25 64072115857 ps
T183 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1612876798 Feb 08 03:18:06 PM UTC 25 Feb 08 03:18:26 PM UTC 25 1060732786 ps
T97 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1980142624 Feb 08 03:15:32 PM UTC 25 Feb 08 03:18:46 PM UTC 25 18286444659 ps
T53 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3526405756 Feb 08 03:16:17 PM UTC 25 Feb 08 03:18:58 PM UTC 25 17188610184 ps
T184 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1328185196 Feb 08 03:18:47 PM UTC 25 Feb 08 03:19:08 PM UTC 25 9815708394 ps
T185 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.118246542 Feb 08 03:18:58 PM UTC 25 Feb 08 03:19:17 PM UTC 25 732647785 ps
T153 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.1045875067 Feb 08 03:06:20 PM UTC 25 Feb 08 03:19:22 PM UTC 25 15255023185 ps
T186 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.628266168 Feb 08 03:08:00 PM UTC 25 Feb 08 03:19:34 PM UTC 25 15328767252 ps
T23 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.4267876514 Feb 08 03:19:08 PM UTC 25 Feb 08 03:21:05 PM UTC 25 13711256000 ps
T187 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.4069823300 Feb 08 03:21:07 PM UTC 25 Feb 08 03:21:13 PM UTC 25 360617669 ps
T188 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.118857928 Feb 08 03:17:57 PM UTC 25 Feb 08 03:21:46 PM UTC 25 9178655099 ps
T46 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1271596236 Feb 08 03:15:26 PM UTC 25 Feb 08 03:22:37 PM UTC 25 121825600557 ps
T66 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.296442239 Feb 08 03:22:38 PM UTC 25 Feb 08 03:22:54 PM UTC 25 305735036 ps
T189 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.2384794354 Feb 08 02:57:33 PM UTC 25 Feb 08 03:22:58 PM UTC 25 211835370462 ps
T190 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3725511662 Feb 08 03:13:58 PM UTC 25 Feb 08 03:23:00 PM UTC 25 79427984711 ps
T191 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3851468364 Feb 08 03:22:59 PM UTC 25 Feb 08 03:23:01 PM UTC 25 18843627 ps
T192 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2644952200 Feb 08 03:18:27 PM UTC 25 Feb 08 03:23:56 PM UTC 25 41480915739 ps
T148 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2453125048 Feb 08 03:15:04 PM UTC 25 Feb 08 03:24:30 PM UTC 25 10342237604 ps
T193 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2359321682 Feb 08 03:23:01 PM UTC 25 Feb 08 03:24:41 PM UTC 25 1549644789 ps
T54 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3378928380 Feb 08 03:21:47 PM UTC 25 Feb 08 03:24:42 PM UTC 25 2452750453 ps
T20 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3447763778 Feb 08 03:11:36 PM UTC 25 Feb 08 03:24:53 PM UTC 25 57752143976 ps
T149 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3237231028 Feb 08 03:15:07 PM UTC 25 Feb 08 03:24:56 PM UTC 25 12339225256 ps
T194 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2137322495 Feb 08 03:17:10 PM UTC 25 Feb 08 03:25:02 PM UTC 25 8600784638 ps
T195 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2534398808 Feb 08 03:24:56 PM UTC 25 Feb 08 03:25:09 PM UTC 25 1394369229 ps
T196 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1052674047 Feb 08 03:24:54 PM UTC 25 Feb 08 03:25:21 PM UTC 25 2833526883 ps
T197 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.59643205 Feb 08 03:24:42 PM UTC 25 Feb 08 03:26:04 PM UTC 25 2874156958 ps
T198 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1506358747 Feb 08 03:26:05 PM UTC 25 Feb 08 03:26:11 PM UTC 25 691943545 ps
T146 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3125975154 Feb 08 03:19:36 PM UTC 25 Feb 08 03:26:23 PM UTC 25 2256267436 ps
T199 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1054893089 Feb 08 03:13:07 PM UTC 25 Feb 08 03:26:26 PM UTC 25 66480817927 ps
T200 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3907296773 Feb 08 03:24:57 PM UTC 25 Feb 08 03:27:30 PM UTC 25 12710514714 ps
T201 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3553066791 Feb 08 03:13:05 PM UTC 25 Feb 08 03:27:32 PM UTC 25 133820579901 ps
T202 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.481873582 Feb 08 03:27:33 PM UTC 25 Feb 08 03:27:35 PM UTC 25 14545613 ps
T55 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3092620512 Feb 08 03:26:24 PM UTC 25 Feb 08 03:27:50 PM UTC 25 10642763482 ps
T203 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1792634667 Feb 08 03:21:14 PM UTC 25 Feb 08 03:27:57 PM UTC 25 21884422610 ps
T204 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.425951711 Feb 08 03:27:36 PM UTC 25 Feb 08 03:27:59 PM UTC 25 556569075 ps
T56 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1457172166 Feb 08 03:26:27 PM UTC 25 Feb 08 03:28:46 PM UTC 25 7671943296 ps
T205 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1773264428 Feb 08 03:24:31 PM UTC 25 Feb 08 03:28:54 PM UTC 25 4295255214 ps
T206 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4109622897 Feb 08 03:28:11 PM UTC 25 Feb 08 03:28:56 PM UTC 25 3696119048 ps
T207 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3414171828 Feb 08 03:19:23 PM UTC 25 Feb 08 03:28:57 PM UTC 25 31475187551 ps
T208 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.726246039 Feb 08 03:25:03 PM UTC 25 Feb 08 03:28:58 PM UTC 25 8419164447 ps
T209 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2799346807 Feb 08 03:28:57 PM UTC 25 Feb 08 03:29:06 PM UTC 25 1390763358 ps
T210 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.19463090 Feb 08 03:28:54 PM UTC 25 Feb 08 03:29:18 PM UTC 25 703231821 ps
T211 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.18574473 Feb 08 03:14:41 PM UTC 25 Feb 08 03:29:24 PM UTC 25 16720754342 ps
T212 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3284472789 Feb 08 03:23:02 PM UTC 25 Feb 08 03:29:28 PM UTC 25 32698169273 ps
T213 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.578021252 Feb 08 03:29:25 PM UTC 25 Feb 08 03:29:31 PM UTC 25 1354932365 ps
T214 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2046866713 Feb 08 03:19:18 PM UTC 25 Feb 08 03:29:36 PM UTC 25 11178075878 ps
T215 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4243601165 Feb 08 03:28:58 PM UTC 25 Feb 08 03:29:48 PM UTC 25 8853033958 ps
T67 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3116900410 Feb 08 03:29:37 PM UTC 25 Feb 08 03:30:01 PM UTC 25 862997779 ps
T216 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2924235063 Feb 08 03:30:02 PM UTC 25 Feb 08 03:30:04 PM UTC 25 44073773 ps
T217 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3734705637 Feb 08 03:30:05 PM UTC 25 Feb 08 03:30:21 PM UTC 25 2648039914 ps
T150 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.184034167 Feb 08 03:29:06 PM UTC 25 Feb 08 03:30:47 PM UTC 25 12537489501 ps
T57 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3026711449 Feb 08 03:29:32 PM UTC 25 Feb 08 03:31:02 PM UTC 25 13796498540 ps
T218 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3687623703 Feb 08 03:27:52 PM UTC 25 Feb 08 03:31:33 PM UTC 25 25541337061 ps
T219 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1749707749 Feb 08 03:31:34 PM UTC 25 Feb 08 03:31:42 PM UTC 25 426615352 ps
T220 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1845346929 Feb 08 03:28:59 PM UTC 25 Feb 08 03:32:12 PM UTC 25 5559461590 ps
T221 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1864383891 Feb 08 03:24:42 PM UTC 25 Feb 08 03:32:16 PM UTC 25 19138947031 ps
T222 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1662457659 Feb 08 03:32:13 PM UTC 25 Feb 08 03:32:29 PM UTC 25 1446051046 ps
T223 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3951692130 Feb 08 03:32:17 PM UTC 25 Feb 08 03:32:45 PM UTC 25 4229792045 ps
T224 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.735931739 Feb 08 03:26:12 PM UTC 25 Feb 08 03:32:55 PM UTC 25 41399080181 ps
T225 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.828657066 Feb 08 03:25:10 PM UTC 25 Feb 08 03:32:58 PM UTC 25 14010955051 ps
T226 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.340005709 Feb 08 03:28:00 PM UTC 25 Feb 08 03:33:05 PM UTC 25 5486020518 ps
T227 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3650285326 Feb 08 03:32:30 PM UTC 25 Feb 08 03:33:08 PM UTC 25 33185570319 ps
T228 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1767270239 Feb 08 03:33:06 PM UTC 25 Feb 08 03:33:12 PM UTC 25 360854555 ps
T229 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.841117055 Feb 08 03:32:46 PM UTC 25 Feb 08 03:34:00 PM UTC 25 9350774899 ps
T230 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2383894034 Feb 08 03:31:03 PM UTC 25 Feb 08 03:34:17 PM UTC 25 8489275438 ps
T231 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.711037656 Feb 08 03:34:26 PM UTC 25 Feb 08 03:34:28 PM UTC 25 42620123 ps
T49 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1321163608 Feb 08 03:34:01 PM UTC 25 Feb 08 03:34:54 PM UTC 25 15347665782 ps
T232 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2882704394 Feb 08 03:34:29 PM UTC 25 Feb 08 03:34:56 PM UTC 25 1126671238 ps
T233 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.590250329 Feb 08 03:33:12 PM UTC 25 Feb 08 03:35:00 PM UTC 25 30617231361 ps
T234 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.4292011985 Feb 08 03:33:08 PM UTC 25 Feb 08 03:35:20 PM UTC 25 2040641410 ps
T235 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.260818569 Feb 08 03:30:22 PM UTC 25 Feb 08 03:35:23 PM UTC 25 21355078331 ps
T236 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4162219877 Feb 08 03:35:21 PM UTC 25 Feb 08 03:35:48 PM UTC 25 622508626 ps
T237 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2258132708 Feb 08 03:29:29 PM UTC 25 Feb 08 03:35:56 PM UTC 25 43118935281 ps
T238 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.226693707 Feb 08 03:08:03 PM UTC 25 Feb 08 03:36:43 PM UTC 25 68684066387 ps
T239 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2065363612 Feb 08 03:29:19 PM UTC 25 Feb 08 03:36:47 PM UTC 25 2696642713 ps
T240 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3628177599 Feb 08 03:35:57 PM UTC 25 Feb 08 03:36:51 PM UTC 25 827671163 ps
T241 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1669052789 Feb 08 03:35:48 PM UTC 25 Feb 08 03:37:07 PM UTC 25 3183755714 ps
T242 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3680415262 Feb 08 03:25:22 PM UTC 25 Feb 08 03:38:29 PM UTC 25 65208091261 ps
T243 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2856530428 Feb 08 03:38:30 PM UTC 25 Feb 08 03:38:38 PM UTC 25 1474600045 ps
T244 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3605679448 Feb 08 03:36:44 PM UTC 25 Feb 08 03:38:44 PM UTC 25 14220963580 ps
T245 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2132134185 Feb 08 03:32:56 PM UTC 25 Feb 08 03:39:43 PM UTC 25 5798033448 ps
T246 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.422907832 Feb 08 03:31:43 PM UTC 25 Feb 08 03:40:21 PM UTC 25 29341453336 ps
T247 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1765814767 Feb 08 03:39:44 PM UTC 25 Feb 08 03:40:27 PM UTC 25 2292234864 ps
T248 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3741249655 Feb 08 03:40:28 PM UTC 25 Feb 08 03:40:30 PM UTC 25 42075257 ps
T249 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.447910863 Feb 08 03:35:24 PM UTC 25 Feb 08 03:40:37 PM UTC 25 10663188574 ps
T250 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2592158910 Feb 08 03:28:47 PM UTC 25 Feb 08 03:40:39 PM UTC 25 97767935670 ps
T251 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.1443911650 Feb 08 03:40:31 PM UTC 25 Feb 08 03:40:39 PM UTC 25 489594732 ps
T252 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2010383916 Feb 08 03:38:39 PM UTC 25 Feb 08 03:40:51 PM UTC 25 7592674611 ps
T253 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.4241325211 Feb 08 03:36:48 PM UTC 25 Feb 08 03:40:54 PM UTC 25 5444193991 ps
T254 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3085347075 Feb 08 03:38:44 PM UTC 25 Feb 08 03:41:02 PM UTC 25 1591557819 ps
T255 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4172874775 Feb 08 03:40:51 PM UTC 25 Feb 08 03:41:09 PM UTC 25 950233286 ps
T256 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2048105317 Feb 08 03:41:09 PM UTC 25 Feb 08 03:41:21 PM UTC 25 2681690785 ps
T257 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.3262034408 Feb 08 03:41:02 PM UTC 25 Feb 08 03:41:55 PM UTC 25 5222534174 ps
T144 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2908543077 Feb 08 03:32:59 PM UTC 25 Feb 08 03:41:57 PM UTC 25 11719227503 ps
T258 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3598284804 Feb 08 03:35:01 PM UTC 25 Feb 08 03:42:27 PM UTC 25 6460754069 ps
T259 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.676883031 Feb 08 03:41:22 PM UTC 25 Feb 08 03:43:24 PM UTC 25 15155161821 ps
T260 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1684034889 Feb 08 03:43:25 PM UTC 25 Feb 08 03:43:32 PM UTC 25 2238818804 ps
T261 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1177433447 Feb 08 03:29:49 PM UTC 25 Feb 08 03:43:45 PM UTC 25 44759630592 ps
T262 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3419850107 Feb 08 03:17:12 PM UTC 25 Feb 08 03:43:50 PM UTC 25 316633696413 ps
T50 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2790505982 Feb 08 03:43:50 PM UTC 25 Feb 08 03:44:45 PM UTC 25 2022089074 ps
T263 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2533960184 Feb 08 03:43:45 PM UTC 25 Feb 08 03:45:18 PM UTC 25 1953526306 ps
T264 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3178337769 Feb 08 03:45:19 PM UTC 25 Feb 08 03:45:21 PM UTC 25 15873256 ps
T265 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3064859154 Feb 08 03:37:08 PM UTC 25 Feb 08 03:45:22 PM UTC 25 2489926648 ps
T266 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3141064256 Feb 08 03:45:22 PM UTC 25 Feb 08 03:45:33 PM UTC 25 1390895856 ps
T267 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1366213695 Feb 08 03:23:57 PM UTC 25 Feb 08 03:46:07 PM UTC 25 16470232383 ps
T268 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1040722074 Feb 08 03:40:40 PM UTC 25 Feb 08 03:48:14 PM UTC 25 20549519821 ps
T269 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3837150910 Feb 08 03:47:40 PM UTC 25 Feb 08 03:48:17 PM UTC 25 3940966416 ps
T270 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3721750724 Feb 08 03:48:18 PM UTC 25 Feb 08 03:48:38 PM UTC 25 2724894150 ps
T271 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2436097039 Feb 08 03:40:55 PM UTC 25 Feb 08 03:48:45 PM UTC 25 17258121947 ps
T272 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1643664411 Feb 08 03:48:39 PM UTC 25 Feb 08 03:49:09 PM UTC 25 713774859 ps
T273 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.11181887 Feb 08 03:48:46 PM UTC 25 Feb 08 03:50:05 PM UTC 25 32359930191 ps
T274 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1064023751 Feb 08 03:43:33 PM UTC 25 Feb 08 03:50:27 PM UTC 25 125753939760 ps
T275 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1869283783 Feb 08 03:50:28 PM UTC 25 Feb 08 03:50:34 PM UTC 25 436359043 ps
T276 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3649889636 Feb 08 03:34:54 PM UTC 25 Feb 08 03:50:43 PM UTC 25 18576773405 ps
T277 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2397985391 Feb 08 03:36:52 PM UTC 25 Feb 08 03:50:54 PM UTC 25 10666091314 ps
T110 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1507344276 Feb 08 03:50:56 PM UTC 25 Feb 08 03:51:07 PM UTC 25 530973011 ps
T118 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2415356466 Feb 08 03:41:58 PM UTC 25 Feb 08 03:51:48 PM UTC 25 106408933011 ps
T119 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3156922593 Feb 08 03:51:49 PM UTC 25 Feb 08 03:51:51 PM UTC 25 13444369 ps
T120 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2468323106 Feb 08 03:46:08 PM UTC 25 Feb 08 03:51:55 PM UTC 25 27009083773 ps
T121 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1538646535 Feb 08 03:51:52 PM UTC 25 Feb 08 03:52:16 PM UTC 25 1153305448 ps
T122 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3204338936 Feb 08 03:50:43 PM UTC 25 Feb 08 03:53:13 PM UTC 25 9770323463 ps
T123 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.4027976402 Feb 08 02:56:46 PM UTC 25 Feb 08 03:53:24 PM UTC 25 171606724619 ps
T124 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3519587430 Feb 08 03:40:38 PM UTC 25 Feb 08 03:53:28 PM UTC 25 7693506776 ps
T125 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.218897594 Feb 08 03:53:24 PM UTC 25 Feb 08 03:53:40 PM UTC 25 766205451 ps
T126 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2335013721 Feb 08 03:49:10 PM UTC 25 Feb 08 03:54:21 PM UTC 25 6606096323 ps
T278 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1264847024 Feb 08 03:50:35 PM UTC 25 Feb 08 03:54:32 PM UTC 25 25871080198 ps
T279 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3730613271 Feb 08 03:27:59 PM UTC 25 Feb 08 03:54:36 PM UTC 25 38086997058 ps
T280 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1148721725 Feb 08 03:53:40 PM UTC 25 Feb 08 03:54:39 PM UTC 25 1024071725 ps
T281 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1732542690 Feb 08 03:41:56 PM UTC 25 Feb 08 03:55:06 PM UTC 25 64260957241 ps
T145 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3276434937 Feb 08 03:42:28 PM UTC 25 Feb 08 03:55:09 PM UTC 25 4849594566 ps
T282 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1864238898 Feb 08 03:50:04 PM UTC 25 Feb 08 03:55:14 PM UTC 25 9409651605 ps
T283 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.675010184 Feb 08 03:48:15 PM UTC 25 Feb 08 03:55:15 PM UTC 25 20565103153 ps
T129 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1036154470 Feb 08 03:07:28 PM UTC 25 Feb 08 03:55:16 PM UTC 25 466682728725 ps
T284 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4245011293 Feb 08 03:55:10 PM UTC 25 Feb 08 03:55:16 PM UTC 25 345603147 ps
T285 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2609498217 Feb 08 03:54:33 PM UTC 25 Feb 08 03:55:23 PM UTC 25 4996470356 ps
T286 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.4228314987 Feb 08 03:55:24 PM UTC 25 Feb 08 03:55:26 PM UTC 25 13697989 ps
T287 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2684037535 Feb 08 03:54:22 PM UTC 25 Feb 08 03:55:30 PM UTC 25 5924524341 ps
T288 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2747029766 Feb 08 03:55:16 PM UTC 25 Feb 08 03:55:33 PM UTC 25 719154356 ps
T289 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.3280556984 Feb 08 03:55:27 PM UTC 25 Feb 08 03:55:43 PM UTC 25 778782660 ps
T290 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.1891321848 Feb 08 03:50:06 PM UTC 25 Feb 08 03:56:17 PM UTC 25 5220523236 ps
T291 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1353408454 Feb 08 03:56:18 PM UTC 25 Feb 08 03:56:37 PM UTC 25 915983814 ps
T292 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2441262233 Feb 08 03:34:57 PM UTC 25 Feb 08 03:56:58 PM UTC 25 94165521373 ps
T293 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1615977659 Feb 08 03:56:59 PM UTC 25 Feb 08 03:57:31 PM UTC 25 725532761 ps
T294 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.4171520681 Feb 08 03:57:32 PM UTC 25 Feb 08 03:57:55 PM UTC 25 2836978352 ps
T295 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3392890394 Feb 08 03:55:15 PM UTC 25 Feb 08 03:57:58 PM UTC 25 24162979825 ps
T296 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3746990684 Feb 08 03:55:14 PM UTC 25 Feb 08 03:58:18 PM UTC 25 10449502934 ps
T297 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2391196225 Feb 08 03:57:56 PM UTC 25 Feb 08 03:59:25 PM UTC 25 12797817434 ps
T298 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2338477573 Feb 08 03:22:56 PM UTC 25 Feb 08 04:00:01 PM UTC 25 63943194315 ps
T299 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2283364530 Feb 08 03:53:14 PM UTC 25 Feb 08 04:00:09 PM UTC 25 5468503929 ps
T300 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1374139825 Feb 08 04:00:02 PM UTC 25 Feb 08 04:00:28 PM UTC 25 413132957 ps
T301 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2565169428 Feb 08 03:55:07 PM UTC 25 Feb 08 04:00:30 PM UTC 25 7535891715 ps
T302 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1532510381 Feb 08 03:53:28 PM UTC 25 Feb 08 04:00:33 PM UTC 25 264139608738 ps
T303 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3308087874 Feb 08 04:00:34 PM UTC 25 Feb 08 04:00:36 PM UTC 25 88186546 ps
T304 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2045341381 Feb 08 03:55:44 PM UTC 25 Feb 08 04:00:39 PM UTC 25 9418125188 ps
T305 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.426788465 Feb 08 04:00:37 PM UTC 25 Feb 08 04:01:02 PM UTC 25 1032775726 ps
T306 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3964573118 Feb 08 03:34:18 PM UTC 25 Feb 08 04:02:06 PM UTC 25 44084627609 ps
T307 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3464395129 Feb 08 04:00:22 PM UTC 25 Feb 08 04:02:23 PM UTC 25 3029502967 ps