Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.64 99.50 96.05 99.72 100.00 97.34 99.13 98.72


Total tests in report: 1085
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.29 68.29 86.25 86.25 66.51 66.51 89.60 89.60 9.52 9.52 71.32 71.32 93.04 93.04 61.79 61.79 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1871598553
80.38 12.08 91.11 4.86 70.19 3.68 89.60 0.00 76.19 66.67 78.92 7.60 94.64 1.59 61.97 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1351326285
87.93 7.55 96.90 5.78 81.00 10.81 93.39 3.79 90.48 14.29 88.24 9.31 96.96 2.32 68.56 6.58 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3847464745
91.44 3.51 98.07 1.17 84.92 3.92 96.66 3.27 100.00 9.52 91.67 3.43 97.10 0.14 71.66 3.11 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1122332131
93.68 2.24 98.83 0.75 88.24 3.33 97.76 1.10 100.00 0.00 94.12 2.45 97.10 0.00 79.71 8.04 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.758248133
94.70 1.02 99.16 0.34 90.26 2.02 98.66 0.90 100.00 0.00 95.59 1.47 97.68 0.58 81.54 1.83 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2747028838
95.46 0.76 99.16 0.00 90.86 0.59 98.66 0.00 100.00 0.00 95.59 0.00 97.68 0.00 86.29 4.75 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2714408037
96.03 0.57 99.16 0.00 91.57 0.71 98.66 0.00 100.00 0.00 96.32 0.74 97.68 0.00 88.85 2.56 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.38897520
96.53 0.49 99.16 0.00 91.57 0.00 98.66 0.00 100.00 0.00 96.32 0.00 97.83 0.14 92.14 3.29 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2725222936
96.85 0.32 99.41 0.25 92.40 0.83 98.66 0.00 100.00 0.00 97.30 0.98 97.83 0.00 92.32 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2560649329
97.13 0.29 99.41 0.00 92.40 0.00 98.66 0.00 100.00 0.00 97.30 0.00 97.83 0.00 94.33 2.01 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.4085521484
97.28 0.15 99.41 0.00 92.40 0.00 98.73 0.07 100.00 0.00 97.55 0.25 97.83 0.00 95.06 0.73 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2590759523
97.42 0.13 99.50 0.08 92.40 0.00 99.59 0.86 100.00 0.00 97.55 0.00 97.83 0.00 95.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1373144802
97.55 0.13 99.50 0.00 92.40 0.00 99.66 0.07 100.00 0.00 97.55 0.00 98.70 0.87 95.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.513788318
97.68 0.13 99.50 0.00 92.40 0.00 99.66 0.00 100.00 0.00 97.55 0.00 98.70 0.00 95.98 0.91 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3878811764
97.79 0.10 99.50 0.00 92.40 0.00 99.66 0.00 100.00 0.00 97.55 0.00 98.70 0.00 96.71 0.73 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3358390995
97.87 0.09 99.50 0.00 92.76 0.36 99.72 0.07 100.00 0.00 97.55 0.00 98.70 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1065006648
97.95 0.08 99.50 0.00 92.76 0.00 99.72 0.00 100.00 0.00 97.55 0.00 98.70 0.00 97.44 0.55 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2738925833
98.02 0.07 99.50 0.00 92.87 0.12 99.72 0.00 100.00 0.00 97.55 0.00 98.70 0.00 97.81 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.731423568
98.08 0.06 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.43 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2760407636
98.14 0.05 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.17 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2844825835
98.16 0.03 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2188881805
98.19 0.03 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2664612311
98.21 0.03 99.50 0.00 92.87 0.00 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2358952874
98.23 0.02 99.50 0.00 92.99 0.12 99.72 0.00 100.00 0.00 97.55 0.00 99.13 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3100958806

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1357163134
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1050342668
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.243899518
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1388364218
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2994785783
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3699000948
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1717964335
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2900033711
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3151927024
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2918053945
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3361252583
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3410882639
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3697974352
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4125515659
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1170866586
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1454873047
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2797885502
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1261618367
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2716968063
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1766106610
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3036274387
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4167380166
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.92605218
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.271201088
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.210491530
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3500529987
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1324869362
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.928346622
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.551311628
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.513016501
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.564210901
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4021640482
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3350504573
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.958860221
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.588943026
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1681216774
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1119054415
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497762244
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4027465319
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2329366543
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3636359053
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.139893037
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1568414766
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.326677908
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3479917450
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3921176476
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.49245614
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1879822756
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.896223956
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.990331901
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3428238204
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2092567173
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.996960694
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2916978221
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1840448618
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.128801436
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.606412488
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2943685469
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.428787611
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1007916994
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1587001164
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3311366279
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2487079916
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1142827656
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3818248147
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1106872229
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.135151338
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.190525145
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.960702548
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2429120029
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1969723078
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3070382139
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3589969846
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1186994339
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.261587619
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1608061353
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4017986900
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1369646382
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.922076775
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.81111660
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4105613984
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2064867187
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Total test records in report: 1085
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2883728368 Oct 15 01:11:44 AM UTC 24 Oct 15 01:11:52 AM UTC 24 7374570520 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1814398726 Oct 15 01:11:52 AM UTC 24 Oct 15 01:11:53 AM UTC 24 24588406 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1476168517 Oct 15 01:11:52 AM UTC 24 Oct 15 01:11:55 AM UTC 24 655430991 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1065006648 Oct 15 01:11:54 AM UTC 24 Oct 15 01:11:56 AM UTC 24 29788500 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.307005227 Oct 15 01:11:50 AM UTC 24 Oct 15 01:11:58 AM UTC 24 754448422 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1373144802 Oct 15 01:11:45 AM UTC 24 Oct 15 01:11:59 AM UTC 24 1023370174 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1871598553 Oct 15 01:11:50 AM UTC 24 Oct 15 01:11:59 AM UTC 24 203882473 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3497805589 Oct 15 01:11:52 AM UTC 24 Oct 15 01:11:59 AM UTC 24 375459473 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.173207742 Oct 15 01:11:54 AM UTC 24 Oct 15 01:12:00 AM UTC 24 905816897 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3547952880 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:02 AM UTC 24 2688070185 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.196533936 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:03 AM UTC 24 1833491766 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2884708124 Oct 15 01:12:02 AM UTC 24 Oct 15 01:12:04 AM UTC 24 17329497 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.121395246 Oct 15 01:11:43 AM UTC 24 Oct 15 01:12:04 AM UTC 24 3087955014 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.981834855 Oct 15 01:12:00 AM UTC 24 Oct 15 01:12:06 AM UTC 24 675646238 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3847464745 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:07 AM UTC 24 1871280556 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2069533390 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:07 AM UTC 24 1038534491 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1116118061 Oct 15 01:11:55 AM UTC 24 Oct 15 01:12:09 AM UTC 24 1559724604 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3218639505 Oct 15 01:11:44 AM UTC 24 Oct 15 01:12:10 AM UTC 24 10060081588 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.590551811 Oct 15 01:12:01 AM UTC 24 Oct 15 01:12:10 AM UTC 24 686237033 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.3784604325 Oct 15 01:11:54 AM UTC 24 Oct 15 01:12:19 AM UTC 24 3946442793 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4101660540 Oct 15 01:11:56 AM UTC 24 Oct 15 01:12:21 AM UTC 24 2512228006 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2590759523 Oct 15 01:11:43 AM UTC 24 Oct 15 01:12:21 AM UTC 24 1142768127 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2747028838 Oct 15 01:12:02 AM UTC 24 Oct 15 01:12:23 AM UTC 24 285988068 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2994045029 Oct 15 01:12:12 AM UTC 24 Oct 15 01:12:24 AM UTC 24 361873049 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.4095404976 Oct 15 01:12:23 AM UTC 24 Oct 15 01:12:28 AM UTC 24 13692091 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2312658289 Oct 15 01:12:22 AM UTC 24 Oct 15 01:12:28 AM UTC 24 262428893 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2616295767 Oct 15 01:11:54 AM UTC 24 Oct 15 01:12:29 AM UTC 24 2349065555 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3774315972 Oct 15 01:11:56 AM UTC 24 Oct 15 01:12:31 AM UTC 24 7060744880 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.937273316 Oct 15 01:12:16 AM UTC 24 Oct 15 01:12:34 AM UTC 24 3471018999 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3229013382 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:36 AM UTC 24 751188442 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3461706076 Oct 15 01:12:09 AM UTC 24 Oct 15 01:12:44 AM UTC 24 5771055866 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1122332131 Oct 15 01:11:52 AM UTC 24 Oct 15 01:12:44 AM UTC 24 15369687468 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1571923101 Oct 15 01:12:01 AM UTC 24 Oct 15 01:12:46 AM UTC 24 5572971962 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1401848026 Oct 15 01:12:29 AM UTC 24 Oct 15 01:12:48 AM UTC 24 2126366966 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1654670019 Oct 15 01:11:44 AM UTC 24 Oct 15 01:12:51 AM UTC 24 10138693447 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.428502400 Oct 15 01:12:20 AM UTC 24 Oct 15 01:12:52 AM UTC 24 496418021 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1829652014 Oct 15 01:12:47 AM UTC 24 Oct 15 01:12:54 AM UTC 24 1782103082 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2186526464 Oct 15 01:12:04 AM UTC 24 Oct 15 01:13:01 AM UTC 24 703296039 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.2690819631 Oct 15 01:12:54 AM UTC 24 Oct 15 01:13:06 AM UTC 24 6577464179 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2154343796 Oct 15 01:12:55 AM UTC 24 Oct 15 01:13:06 AM UTC 24 216594634 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2466087966 Oct 15 01:13:07 AM UTC 24 Oct 15 01:13:09 AM UTC 24 38160826 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2827552402 Oct 15 01:12:24 AM UTC 24 Oct 15 01:13:13 AM UTC 24 1185656107 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2589637744 Oct 15 01:11:52 AM UTC 24 Oct 15 01:13:14 AM UTC 24 2782047266 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.306220672 Oct 15 01:13:07 AM UTC 24 Oct 15 01:13:14 AM UTC 24 418382655 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2680943504 Oct 15 01:12:32 AM UTC 24 Oct 15 01:13:16 AM UTC 24 6602219343 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1192304403 Oct 15 01:11:56 AM UTC 24 Oct 15 01:13:21 AM UTC 24 5155883530 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4257416566 Oct 15 01:13:16 AM UTC 24 Oct 15 01:13:24 AM UTC 24 2248939751 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3923695966 Oct 15 01:12:30 AM UTC 24 Oct 15 01:13:31 AM UTC 24 766098560 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1580932766 Oct 15 01:12:08 AM UTC 24 Oct 15 01:13:35 AM UTC 24 1367397902 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2591995014 Oct 15 01:12:09 AM UTC 24 Oct 15 01:13:47 AM UTC 24 28842329854 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1151009207 Oct 15 01:13:22 AM UTC 24 Oct 15 01:13:49 AM UTC 24 1613617794 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.32239713 Oct 15 01:12:09 AM UTC 24 Oct 15 01:13:53 AM UTC 24 4596569155 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.315505229 Oct 15 01:13:25 AM UTC 24 Oct 15 01:13:54 AM UTC 24 2419494642 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1351326285 Oct 15 01:12:00 AM UTC 24 Oct 15 01:13:54 AM UTC 24 6015341702 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1217542011 Oct 15 01:13:50 AM UTC 24 Oct 15 01:13:56 AM UTC 24 694519428 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2560649329 Oct 15 01:13:54 AM UTC 24 Oct 15 01:14:06 AM UTC 24 1323699039 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1351766200 Oct 15 01:13:10 AM UTC 24 Oct 15 01:14:30 AM UTC 24 1366731083 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3732207641 Oct 15 01:14:31 AM UTC 24 Oct 15 01:14:33 AM UTC 24 35836754 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2854665830 Oct 15 01:13:57 AM UTC 24 Oct 15 01:15:08 AM UTC 24 4708935375 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2121529453 Oct 15 01:11:45 AM UTC 24 Oct 15 01:15:12 AM UTC 24 23578606202 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2460662628 Oct 15 01:12:35 AM UTC 24 Oct 15 01:15:13 AM UTC 24 51010654733 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1324613228 Oct 15 01:11:52 AM UTC 24 Oct 15 01:15:20 AM UTC 24 20694678951 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.739566871 Oct 15 01:15:15 AM UTC 24 Oct 15 01:15:21 AM UTC 24 343133986 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3890087305 Oct 15 01:12:15 AM UTC 24 Oct 15 01:15:23 AM UTC 24 19964413070 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.4042844307 Oct 15 01:13:54 AM UTC 24 Oct 15 01:15:29 AM UTC 24 3990365723 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2725600642 Oct 15 01:12:53 AM UTC 24 Oct 15 01:15:47 AM UTC 24 10122541599 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.4204396208 Oct 15 01:12:14 AM UTC 24 Oct 15 01:15:57 AM UTC 24 23888827193 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2004715628 Oct 15 01:14:35 AM UTC 24 Oct 15 01:15:58 AM UTC 24 1803790885 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2738925833 Oct 15 01:13:32 AM UTC 24 Oct 15 01:16:00 AM UTC 24 148770286263 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.980967399 Oct 15 01:11:45 AM UTC 24 Oct 15 01:16:03 AM UTC 24 4697465273 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3757397710 Oct 15 01:16:01 AM UTC 24 Oct 15 01:16:07 AM UTC 24 364938858 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.4284345601 Oct 15 01:11:43 AM UTC 24 Oct 15 01:16:21 AM UTC 24 3467199345 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1081857295 Oct 15 01:14:47 AM UTC 24 Oct 15 01:16:21 AM UTC 24 9935913402 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.1588548272 Oct 15 01:16:22 AM UTC 24 Oct 15 01:16:32 AM UTC 24 669012926 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1523426633 Oct 15 01:15:24 AM UTC 24 Oct 15 01:16:36 AM UTC 24 757730158 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.221631048 Oct 15 01:16:37 AM UTC 24 Oct 15 01:16:39 AM UTC 24 18136954 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3339334179 Oct 15 01:15:22 AM UTC 24 Oct 15 01:16:46 AM UTC 24 4464589219 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.758248133 Oct 15 01:12:45 AM UTC 24 Oct 15 01:16:59 AM UTC 24 2555341864 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3796269534 Oct 15 01:16:40 AM UTC 24 Oct 15 01:17:03 AM UTC 24 872122815 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1336331881 Oct 15 01:13:53 AM UTC 24 Oct 15 01:17:07 AM UTC 24 27740420669 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3969598227 Oct 15 01:15:30 AM UTC 24 Oct 15 01:17:08 AM UTC 24 61926644599 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.740010748 Oct 15 01:12:09 AM UTC 24 Oct 15 01:17:19 AM UTC 24 11566528737 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2905883254 Oct 15 01:11:56 AM UTC 24 Oct 15 01:17:19 AM UTC 24 5918441080 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1068938446 Oct 15 01:17:19 AM UTC 24 Oct 15 01:17:30 AM UTC 24 4806769441 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2562094558 Oct 15 01:11:54 AM UTC 24 Oct 15 01:17:31 AM UTC 24 4441554278 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1523619089 Oct 15 01:17:08 AM UTC 24 Oct 15 01:17:38 AM UTC 24 3853754225 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1560719779 Oct 15 01:12:00 AM UTC 24 Oct 15 01:17:42 AM UTC 24 21000848897 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1933067900 Oct 15 01:17:21 AM UTC 24 Oct 15 01:17:48 AM UTC 24 3061893306 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1123999563 Oct 15 01:17:48 AM UTC 24 Oct 15 01:17:55 AM UTC 24 367379477 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3633966142 Oct 15 01:11:55 AM UTC 24 Oct 15 01:18:02 AM UTC 24 4675461630 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.662130537 Oct 15 01:13:15 AM UTC 24 Oct 15 01:18:02 AM UTC 24 7701305032 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1628069853 Oct 15 01:15:13 AM UTC 24 Oct 15 01:18:03 AM UTC 24 2921559076 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.433761599 Oct 15 01:17:31 AM UTC 24 Oct 15 01:18:10 AM UTC 24 3610886616 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.3952714254 Oct 15 01:18:03 AM UTC 24 Oct 15 01:18:14 AM UTC 24 707838327 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3240730802 Oct 15 01:18:15 AM UTC 24 Oct 15 01:18:17 AM UTC 24 17766322 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2725222936 Oct 15 01:12:29 AM UTC 24 Oct 15 01:18:26 AM UTC 24 60730857835 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2243253479 Oct 15 01:18:04 AM UTC 24 Oct 15 01:18:32 AM UTC 24 1593461969 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2690184580 Oct 15 01:11:52 AM UTC 24 Oct 15 01:18:36 AM UTC 24 4304578772 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1109562880 Oct 15 01:16:07 AM UTC 24 Oct 15 01:18:37 AM UTC 24 6365163413 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3884132415 Oct 15 01:18:18 AM UTC 24 Oct 15 01:18:42 AM UTC 24 1402947003 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4069153104 Oct 15 01:12:10 AM UTC 24 Oct 15 01:18:46 AM UTC 24 54250913742 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1940922577 Oct 15 01:12:49 AM UTC 24 Oct 15 01:18:47 AM UTC 24 57622184488 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2324084903 Oct 15 01:11:43 AM UTC 24 Oct 15 01:18:50 AM UTC 24 16483044409 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3981826040 Oct 15 01:16:23 AM UTC 24 Oct 15 01:19:06 AM UTC 24 10876049478 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3656557909 Oct 15 01:18:53 AM UTC 24 Oct 15 01:19:29 AM UTC 24 2971370473 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.4256490220 Oct 15 01:12:07 AM UTC 24 Oct 15 01:19:38 AM UTC 24 10549810719 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1992705440 Oct 15 01:11:52 AM UTC 24 Oct 15 01:19:42 AM UTC 24 50904638444 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1869763058 Oct 15 01:19:39 AM UTC 24 Oct 15 01:19:45 AM UTC 24 683672748 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3499876361 Oct 15 01:18:53 AM UTC 24 Oct 15 01:19:46 AM UTC 24 1493785722 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3749163996 Oct 15 01:12:28 AM UTC 24 Oct 15 01:19:50 AM UTC 24 20512857888 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.3269983028 Oct 15 01:19:47 AM UTC 24 Oct 15 01:19:56 AM UTC 24 1377478191 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3814942135 Oct 15 01:18:38 AM UTC 24 Oct 15 01:19:56 AM UTC 24 1211025084 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.742291111 Oct 15 01:19:57 AM UTC 24 Oct 15 01:19:59 AM UTC 24 14979958 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.460266086 Oct 15 01:18:53 AM UTC 24 Oct 15 01:19:59 AM UTC 24 9641601040 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2427804298 Oct 15 01:13:16 AM UTC 24 Oct 15 01:20:07 AM UTC 24 22009506037 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.201593297 Oct 15 01:11:43 AM UTC 24 Oct 15 01:20:07 AM UTC 24 22094816875 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.38897520 Oct 15 01:19:51 AM UTC 24 Oct 15 01:20:26 AM UTC 24 1332352893 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2588899386 Oct 15 01:20:27 AM UTC 24 Oct 15 01:20:33 AM UTC 24 374016381 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3998402977 Oct 15 01:11:52 AM UTC 24 Oct 15 01:20:39 AM UTC 24 28620869390 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.111150562 Oct 15 01:20:00 AM UTC 24 Oct 15 01:20:56 AM UTC 24 14976092174 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2589030801 Oct 15 01:17:04 AM UTC 24 Oct 15 01:21:01 AM UTC 24 3144873196 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.497585575 Oct 15 01:18:02 AM UTC 24 Oct 15 01:21:10 AM UTC 24 10033825019 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3551548553 Oct 15 01:20:40 AM UTC 24 Oct 15 01:21:17 AM UTC 24 2977001230 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1487156754 Oct 15 01:20:57 AM UTC 24 Oct 15 01:21:46 AM UTC 24 787999030 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4070536253 Oct 15 01:13:32 AM UTC 24 Oct 15 01:21:50 AM UTC 24 8511314212 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3483270629 Oct 15 01:21:51 AM UTC 24 Oct 15 01:21:56 AM UTC 24 352846308 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1107090965 Oct 15 01:12:10 AM UTC 24 Oct 15 01:21:59 AM UTC 24 10955440759 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.372997616 Oct 15 01:11:57 AM UTC 24 Oct 15 01:22:17 AM UTC 24 22140804622 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.4085521484 Oct 15 01:11:52 AM UTC 24 Oct 15 01:22:19 AM UTC 24 6130855529 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.395283502 Oct 15 01:16:03 AM UTC 24 Oct 15 01:22:22 AM UTC 24 94573582450 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.642234483 Oct 15 01:22:18 AM UTC 24 Oct 15 01:22:26 AM UTC 24 697770866 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1153651719 Oct 15 01:22:27 AM UTC 24 Oct 15 01:22:29 AM UTC 24 25162548 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2681180647 Oct 15 01:11:45 AM UTC 24 Oct 15 01:22:39 AM UTC 24 14642665504 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.580973144 Oct 15 01:21:02 AM UTC 24 Oct 15 01:22:45 AM UTC 24 13705521048 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2838867405 Oct 15 01:19:43 AM UTC 24 Oct 15 01:22:49 AM UTC 24 6987924912 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1155613192 Oct 15 01:19:47 AM UTC 24 Oct 15 01:22:50 AM UTC 24 4540283936 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1229512196 Oct 15 01:15:21 AM UTC 24 Oct 15 01:22:50 AM UTC 24 15892452737 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2111610891 Oct 15 01:18:37 AM UTC 24 Oct 15 01:22:53 AM UTC 24 3569040259 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.514876565 Oct 15 01:22:30 AM UTC 24 Oct 15 01:22:58 AM UTC 24 4990529045 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2783512227 Oct 15 01:11:45 AM UTC 24 Oct 15 01:23:07 AM UTC 24 6196656453 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1334556790 Oct 15 01:22:51 AM UTC 24 Oct 15 01:23:12 AM UTC 24 7235343863 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1566483187 Oct 15 01:22:59 AM UTC 24 Oct 15 01:23:16 AM UTC 24 2846286724 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1122843324 Oct 15 01:12:00 AM UTC 24 Oct 15 01:23:18 AM UTC 24 2572174573 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.111316130 Oct 15 01:19:30 AM UTC 24 Oct 15 01:23:22 AM UTC 24 1289121777 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3914198858 Oct 15 01:13:35 AM UTC 24 Oct 15 01:23:28 AM UTC 24 6338206562 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2036627446 Oct 15 01:23:23 AM UTC 24 Oct 15 01:23:30 AM UTC 24 2809855215 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3101598765 Oct 15 01:20:08 AM UTC 24 Oct 15 01:23:40 AM UTC 24 3212668526 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3100958806 Oct 15 01:23:08 AM UTC 24 Oct 15 01:23:50 AM UTC 24 23453504961 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.1165973902 Oct 15 01:23:41 AM UTC 24 Oct 15 01:23:52 AM UTC 24 700239859 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1263036858 Oct 15 01:15:58 AM UTC 24 Oct 15 01:23:56 AM UTC 24 8762372316 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2399897116 Oct 15 01:23:57 AM UTC 24 Oct 15 01:23:59 AM UTC 24 23856172 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1207332326 Oct 15 01:23:52 AM UTC 24 Oct 15 01:24:04 AM UTC 24 634138065 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3782059949 Oct 15 01:15:47 AM UTC 24 Oct 15 01:24:05 AM UTC 24 6574117994 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2349532231 Oct 15 01:12:10 AM UTC 24 Oct 15 01:24:07 AM UTC 24 33094401108 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.586364839 Oct 15 01:22:20 AM UTC 24 Oct 15 01:24:15 AM UTC 24 1268765319 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.182885471 Oct 15 01:11:52 AM UTC 24 Oct 15 01:24:21 AM UTC 24 25717746352 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2333751071 Oct 15 01:24:00 AM UTC 24 Oct 15 01:24:28 AM UTC 24 1964184037 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.569353572 Oct 15 01:22:54 AM UTC 24 Oct 15 01:24:31 AM UTC 24 813979816 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.904592717 Oct 15 01:24:15 AM UTC 24 Oct 15 01:24:35 AM UTC 24 6398690216 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2711164891 Oct 15 01:21:11 AM UTC 24 Oct 15 01:24:35 AM UTC 24 6243714701 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2329396447 Oct 15 01:24:32 AM UTC 24 Oct 15 01:24:44 AM UTC 24 2683656414 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1872216082 Oct 15 01:17:56 AM UTC 24 Oct 15 01:24:53 AM UTC 24 21565325566 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3455021078 Oct 15 01:21:58 AM UTC 24 Oct 15 01:24:54 AM UTC 24 5722485978 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.988676135 Oct 15 01:24:55 AM UTC 24 Oct 15 01:25:01 AM UTC 24 678616873 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.654167685 Oct 15 01:12:45 AM UTC 24 Oct 15 01:25:03 AM UTC 24 14588297642 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3033730189 Oct 15 01:22:00 AM UTC 24 Oct 15 01:25:22 AM UTC 24 91070420941 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3574824874 Oct 15 01:11:59 AM UTC 24 Oct 15 01:25:26 AM UTC 24 36803939358 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.1323449460 Oct 15 01:25:23 AM UTC 24 Oct 15 01:25:34 AM UTC 24 817093249 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1230635548 Oct 15 01:24:36 AM UTC 24 Oct 15 01:25:48 AM UTC 24 33440381257 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3322964890 Oct 15 01:17:32 AM UTC 24 Oct 15 01:25:48 AM UTC 24 25619869893 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2011310631 Oct 15 01:24:29 AM UTC 24 Oct 15 01:25:48 AM UTC 24 1549574358 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1399361382 Oct 15 01:25:49 AM UTC 24 Oct 15 01:25:51 AM UTC 24 11715559 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.662033047 Oct 15 01:25:27 AM UTC 24 Oct 15 01:25:56 AM UTC 24 728305773 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3779020535 Oct 15 01:18:27 AM UTC 24 Oct 15 01:25:58 AM UTC 24 7386652300 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2108911100 Oct 15 01:21:46 AM UTC 24 Oct 15 01:26:05 AM UTC 24 8732607863 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3343527426 Oct 15 01:25:49 AM UTC 24 Oct 15 01:26:07 AM UTC 24 5407663779 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2336543985 Oct 15 01:24:05 AM UTC 24 Oct 15 01:26:13 AM UTC 24 3771631127 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4009397532 Oct 15 01:18:53 AM UTC 24 Oct 15 01:26:13 AM UTC 24 129400478691 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2109275698 Oct 15 01:11:52 AM UTC 24 Oct 15 01:26:14 AM UTC 24 34275581530 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.4226087402 Oct 15 01:17:08 AM UTC 24 Oct 15 01:26:23 AM UTC 24 15550135132 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3002905092 Oct 15 01:19:07 AM UTC 24 Oct 15 01:26:24 AM UTC 24 31836700481 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3881177330 Oct 15 01:23:30 AM UTC 24 Oct 15 01:26:29 AM UTC 24 3248937756 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.867954380 Oct 15 01:25:59 AM UTC 24 Oct 15 01:26:34 AM UTC 24 3101623534 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.94950855 Oct 15 01:26:08 AM UTC 24 Oct 15 01:26:35 AM UTC 24 2692559288 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.41139118 Oct 15 01:26:30 AM UTC 24 Oct 15 01:26:37 AM UTC 24 710175711 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3449474505 Oct 15 01:16:46 AM UTC 24 Oct 15 01:26:40 AM UTC 24 6208629920 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.1935608650 Oct 15 01:26:38 AM UTC 24 Oct 15 01:26:49 AM UTC 24 1328637828 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3342060340 Oct 15 01:17:42 AM UTC 24 Oct 15 01:26:50 AM UTC 24 3178488526 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3885542461 Oct 15 01:26:50 AM UTC 24 Oct 15 01:26:52 AM UTC 24 49478928 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2479397181 Oct 15 01:26:14 AM UTC 24 Oct 15 01:26:54 AM UTC 24 1456084687 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3584778359 Oct 15 01:20:35 AM UTC 24 Oct 15 01:26:54 AM UTC 24 153021289089 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4088212996 Oct 15 01:11:45 AM UTC 24 Oct 15 01:27:04 AM UTC 24 30716188839 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3673394498 Oct 15 01:26:53 AM UTC 24 Oct 15 01:27:15 AM UTC 24 3137662674 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1391668651 Oct 15 01:12:25 AM UTC 24 Oct 15 01:27:17 AM UTC 24 167899500280 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2610684650 Oct 15 01:27:16 AM UTC 24 Oct 15 01:27:39 AM UTC 24 823100332 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1195471780 Oct 15 01:26:36 AM UTC 24 Oct 15 01:27:56 AM UTC 24 7035686066 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3279072302 Oct 15 01:26:14 AM UTC 24 Oct 15 01:27:56 AM UTC 24 51675976684 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.527784426 Oct 15 01:26:41 AM UTC 24 Oct 15 01:28:03 AM UTC 24 3195088397 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1252867443 Oct 15 01:22:49 AM UTC 24 Oct 15 01:28:12 AM UTC 24 4438912244 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2641052285 Oct 15 01:25:04 AM UTC 24 Oct 15 01:28:31 AM UTC 24 75241669710 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3032335977 Oct 15 01:12:06 AM UTC 24 Oct 15 01:28:32 AM UTC 24 37797762615 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3399294981 Oct 15 01:13:48 AM UTC 24 Oct 15 01:28:36 AM UTC 24 13565138440 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4286865578 Oct 15 01:28:34 AM UTC 24 Oct 15 01:28:40 AM UTC 24 2279579641 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1719154304 Oct 15 01:27:40 AM UTC 24 Oct 15 01:28:57 AM UTC 24 3303550728 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.959771577 Oct 15 01:26:35 AM UTC 24 Oct 15 01:29:04 AM UTC 24 28764862744 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.2415610783 Oct 15 01:28:58 AM UTC 24 Oct 15 01:29:08 AM UTC 24 1346017123 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3211154615 Oct 15 01:27:57 AM UTC 24 Oct 15 01:29:14 AM UTC 24 2995108532 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.415558512 Oct 15 01:29:15 AM UTC 24 Oct 15 01:29:17 AM UTC 24 31457968 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1791931095 Oct 15 01:25:49 AM UTC 24 Oct 15 01:29:19 AM UTC 24 18438476181 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.723674338 Oct 15 01:24:08 AM UTC 24 Oct 15 01:29:26 AM UTC 24 5040638327 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3124235997 Oct 15 01:27:57 AM UTC 24 Oct 15 01:29:27 AM UTC 24 49605876467 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1515078031 Oct 15 01:29:18 AM UTC 24 Oct 15 01:29:53 AM UTC 24 1450208708 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.4267319910 Oct 15 01:28:41 AM UTC 24 Oct 15 01:30:11 AM UTC 24 2707935579 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3759994909 Oct 15 01:11:43 AM UTC 24 Oct 15 01:30:16 AM UTC 24 46251709862 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.348185266 Oct 15 01:29:54 AM UTC 24 Oct 15 01:30:28 AM UTC 24 1850255008 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4043712856 Oct 15 01:23:28 AM UTC 24 Oct 15 01:30:30 AM UTC 24 14284914649 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3538766611 Oct 15 01:25:57 AM UTC 24 Oct 15 01:30:33 AM UTC 24 3893582456 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.740966370 Oct 15 01:30:17 AM UTC 24 Oct 15 01:31:08 AM UTC 24 778218553 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1444037653 Oct 15 01:30:31 AM UTC 24 Oct 15 01:31:10 AM UTC 24 24352944643 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1376810117 Oct 15 01:25:02 AM UTC 24 Oct 15 01:31:16 AM UTC 24 86156380962 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.372506429 Oct 15 01:29:05 AM UTC 24 Oct 15 01:31:19 AM UTC 24 3949349892 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2252131929 Oct 15 01:31:17 AM UTC 24 Oct 15 01:31:25 AM UTC 24 2576993853 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.2363972419 Oct 15 01:26:25 AM UTC 24 Oct 15 01:31:36 AM UTC 24 7401482874 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.731423568 Oct 15 01:26:25 AM UTC 24 Oct 15 01:31:46 AM UTC 24 4325097809 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.3104936601 Oct 15 01:31:37 AM UTC 24 Oct 15 01:31:46 AM UTC 24 1389421541 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2451831930 Oct 15 01:19:05 AM UTC 24 Oct 15 01:31:55 AM UTC 24 33817799390 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3359631405 Oct 15 01:31:55 AM UTC 24 Oct 15 01:31:58 AM UTC 24 25292941 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1536775640 Oct 15 01:30:29 AM UTC 24 Oct 15 01:32:00 AM UTC 24 787002145 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3542684613 Oct 15 01:27:18 AM UTC 24 Oct 15 01:32:03 AM UTC 24 23375178212 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.271899818 Oct 15 01:20:00 AM UTC 24 Oct 15 01:32:10 AM UTC 24 14662497093 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2810576236 Oct 15 01:12:37 AM UTC 24 Oct 15 01:32:10 AM UTC 24 66584924680 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.155248949 Oct 15 01:31:59 AM UTC 24 Oct 15 01:32:10 AM UTC 24 2869366203 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.4155770571 Oct 15 01:32:11 AM UTC 24 Oct 15 01:32:43 AM UTC 24 5977431811 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.888575364 Oct 15 01:31:46 AM UTC 24 Oct 15 01:32:58 AM UTC 24 10237029995 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3127870039 Oct 15 01:26:06 AM UTC 24 Oct 15 01:33:00 AM UTC 24 10244855605 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.717992861 Oct 15 01:32:43 AM UTC 24 Oct 15 01:33:05 AM UTC 24 714056246 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3647671161 Oct 15 01:28:38 AM UTC 24 Oct 15 01:33:07 AM UTC 24 114999341583 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2102493649 Oct 15 01:27:05 AM UTC 24 Oct 15 01:33:40 AM UTC 24 11175239495 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1082736453 Oct 15 01:22:51 AM UTC 24 Oct 15 01:33:51 AM UTC 24 89293667542 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2643237286 Oct 15 01:33:52 AM UTC 24 Oct 15 01:33:58 AM UTC 24 1768417285 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3783354174 Oct 15 01:33:01 AM UTC 24 Oct 15 01:34:08 AM UTC 24 7214540080 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.768497300 Oct 15 01:31:26 AM UTC 24 Oct 15 01:34:15 AM UTC 24 5264949986 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3995710817 Oct 15 01:34:10 AM UTC 24 Oct 15 01:34:25 AM UTC 24 6007473934 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.835466997 Oct 15 01:34:16 AM UTC 24 Oct 15 01:34:30 AM UTC 24 573003314 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.586673244 Oct 15 01:34:31 AM UTC 24 Oct 15 01:34:33 AM UTC 24 43964393 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.827169114 Oct 15 01:32:59 AM UTC 24 Oct 15 01:34:47 AM UTC 24 11186658469 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.3634495003 Oct 15 01:30:12 AM UTC 24 Oct 15 01:34:51 AM UTC 24 10210516640 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1882931405 Oct 15 01:13:15 AM UTC 24 Oct 15 01:34:58 AM UTC 24 43331621499 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3028884775 Oct 15 01:29:27 AM UTC 24 Oct 15 01:35:11 AM UTC 24 20846772194 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1414654889 Oct 15 01:24:22 AM UTC 24 Oct 15 01:35:16 AM UTC 24 16571777990 ps
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