Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv


Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
escalated_cp 2 0 2 100.00 100 1 1 2
key_seed_valid_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_seed_valid_cross 4 0 4 100.00 100 1 1 0


Summary for Variable escalated_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for escalated_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8117 1 T1 2 T2 1 T3 1
auto[1] 859 1 T5 7 T7 4 T8 8


Summary for Variable key_seed_valid_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_seed_valid_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4504 1 T1 2 T2 1 T4 2
auto[1] 4472 1 T3 1 T5 13 T9 1


Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key_seed_valid_cross

Bins
key_seed_valid_cp   escalated_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 4077 1 T1 2 T2 1 T4 2
auto[0] auto[1] 427 1 T5 3 T7 1 T8 5
auto[1] auto[0] 4040 1 T3 1 T5 9 T9 1
auto[1] auto[1] 432 1 T5 4 T7 3 T8 3