SRAM_CTRL/RET Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.422m	2.005ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	29.839us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	26.104us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.100s	998.068us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	30.286us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.430s	137.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	26.104us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	30.286us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.720s	1.336ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.290s	830.149us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	25.417m	41.708ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.193m	15.549ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.385m	7.949ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.040m	6.090ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.540s	2.906ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.409m	23.893ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.839m	233.922us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.127m	104.995ms	49	50	98.00
V2	max_throughput	sram_ctrl_max_throughput	2.753m	1.610ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.668m	609.718us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.852m	28.458ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.180s	45.748us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.699h	442.151ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.710s	26.321us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.480s	151.404us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.480s	151.404us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	29.839us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	26.104us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	30.286us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	174.625us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	29.839us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	26.104us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	30.286us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	174.625us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.250s	481.909us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
		sram_ctrl_tl_intg_err	3.060s	581.340us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.060s	581.340us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.852m	28.458ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	26.104us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.409m	23.893ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.409m	23.893ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.409m	23.893ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.540s	2.906ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.250s	481.909us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.422m	2.005ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.422m	2.005ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.409m	23.893ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.540s	2.906ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.422m	2.005ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.340s	683.132us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.540h	518.316us	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_partial_access_b2b has 1 failures.
  - 29.sram_ctrl_partial_access_b2b.3101720507
    Line 249, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_executable has 1 failures.
  - 38.sram_ctrl_executable.938572285
    Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 5.sram_ctrl_multiple_keys.833301537
    Line 241, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10407753072 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x2989754d
  UVM_INFO @ 10407753072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 21.sram_ctrl_smoke.3770040390
    Line 241, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 10487571153 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbd0f6ae8
  UVM_INFO @ 10487571153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 29.sram_ctrl_executable.1507070540
    Line 261, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 68868377746 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x3c27041b
  UVM_INFO @ 68868377746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (sram_ctrl_scoreboard.sv:525) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: sram_ctrl_regs_reg_block.status has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.sram_ctrl_stress_all_with_rand_reset.1822208959
    Line 524, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 721875191 ps: (sram_ctrl_scoreboard.sv:525) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (24 [0x18] vs 0 [0x0]) reg name: sram_ctrl_regs_reg_block.status
  UVM_INFO @ 721875191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: 50278df8b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `50278df8b`