SRAM_CTRL/RET Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.164m 4.117ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.100s 16.925us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 1.050s 16.422us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 3.880s 681.246us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.140s 66.645us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.350s 38.351us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.050s 16.422us 20 20 100.00
sram_ctrl_csr_aliasing 1.140s 66.645us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 16.470s 850.592us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 8.550s 369.766us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.012m 61.879ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.541m 3.395ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.936m 19.220ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 21.894m 65.533ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 14.160s 705.490us 50 50 100.00
V2 executable sram_ctrl_executable 27.533m 12.126ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.286m 1.198ms 49 50 98.00
sram_ctrl_partial_access_b2b 10.313m 95.349ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.478m 139.609us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.074m 586.147us 50 50 100.00
V2 regwen sram_ctrl_regwen 29.937m 5.666ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 1.310s 151.772us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.798h 178.406ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 1.070s 14.514us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.980s 606.270us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.980s 606.270us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.100s 16.925us 5 5 100.00
sram_ctrl_csr_rw 1.050s 16.422us 20 20 100.00
sram_ctrl_csr_aliasing 1.140s 66.645us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.280s 57.953us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.100s 16.925us 5 5 100.00
sram_ctrl_csr_rw 1.050s 16.422us 20 20 100.00
sram_ctrl_csr_aliasing 1.140s 66.645us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.280s 57.953us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 8.620s 5.150ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
sram_ctrl_tl_intg_err 4.520s 297.189us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 4.520s 297.189us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.937m 5.666ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.050s 16.422us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 27.533m 12.126ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 27.533m 12.126ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 27.533m 12.126ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 14.160s 705.490us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 8.620s 5.150ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.164m 4.117ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.164m 4.117ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.164m 4.117ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 27.533m 12.126ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 14.160s 705.490us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.164m 4.117ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.540s 691.050us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 13.769m 11.059ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.98 99.16 94.49 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results