f8b3c19a2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sram_ctrl_smoke | 2.178m | 664.864us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.670s | 15.968us | 5 | 5 | 100.00 |
V1 | csr_rw | sram_ctrl_csr_rw | 0.680s | 14.449us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.860s | 502.392us | 5 | 5 | 100.00 |
V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.700s | 30.124us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 3.020s | 54.353us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.680s | 14.449us | 20 | 20 | 100.00 |
sram_ctrl_csr_aliasing | 0.700s | 30.124us | 5 | 5 | 100.00 | ||
V1 | mem_walk | sram_ctrl_mem_walk | 10.080s | 2.414ms | 50 | 50 | 100.00 |
V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.500s | 175.770us | 50 | 50 | 100.00 |
V1 | TOTAL | 205 | 205 | 100.00 | |||
V2 | multiple_keys | sram_ctrl_multiple_keys | 26.830m | 73.138ms | 50 | 50 | 100.00 |
V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.356m | 28.127ms | 50 | 50 | 100.00 |
V2 | bijection | sram_ctrl_bijection | 1.433m | 5.688ms | 50 | 50 | 100.00 |
V2 | access_during_key_req | sram_ctrl_access_during_key_req | 31.910m | 7.456ms | 50 | 50 | 100.00 |
V2 | lc_escalation | sram_ctrl_lc_escalation | 21.940s | 1.960ms | 50 | 50 | 100.00 |
V2 | executable | sram_ctrl_executable | 29.574m | 13.631ms | 48 | 50 | 96.00 |
V2 | partial_access | sram_ctrl_partial_access | 2.752m | 226.895us | 50 | 50 | 100.00 |
sram_ctrl_partial_access_b2b | 8.759m | 21.056ms | 50 | 50 | 100.00 | ||
V2 | max_throughput | sram_ctrl_max_throughput | 2.218m | 141.660us | 50 | 50 | 100.00 |
sram_ctrl_throughput_w_partial_write | 2.819m | 758.667us | 50 | 50 | 100.00 | ||
V2 | regwen | sram_ctrl_regwen | 33.556m | 73.332ms | 49 | 50 | 98.00 |
V2 | ram_cfg | sram_ctrl_ram_cfg | 1.220s | 35.253us | 50 | 50 | 100.00 |
V2 | stress_all | sram_ctrl_stress_all | 2.225h | 92.666ms | 48 | 50 | 96.00 |
V2 | alert_test | sram_ctrl_alert_test | 0.690s | 32.918us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.480s | 560.066us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.480s | 560.066us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.670s | 15.968us | 5 | 5 | 100.00 |
sram_ctrl_csr_rw | 0.680s | 14.449us | 20 | 20 | 100.00 | ||
sram_ctrl_csr_aliasing | 0.700s | 30.124us | 5 | 5 | 100.00 | ||
sram_ctrl_same_csr_outstanding | 0.760s | 72.528us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.670s | 15.968us | 5 | 5 | 100.00 |
sram_ctrl_csr_rw | 0.680s | 14.449us | 20 | 20 | 100.00 | ||
sram_ctrl_csr_aliasing | 0.700s | 30.124us | 5 | 5 | 100.00 | ||
sram_ctrl_same_csr_outstanding | 0.760s | 72.528us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 735 | 740 | 99.32 | |||
V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 11.080s | 2.458ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
sram_ctrl_tl_intg_err | 2.750s | 1.284ms | 20 | 20 | 100.00 | ||
V2S | prim_count_check | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.750s | 1.284ms | 20 | 20 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 33.556m | 73.332ms | 49 | 50 | 98.00 |
V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.680s | 14.449us | 20 | 20 | 100.00 |
V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 29.574m | 13.631ms | 48 | 50 | 96.00 |
V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 29.574m | 13.631ms | 48 | 50 | 96.00 |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 29.574m | 13.631ms | 48 | 50 | 96.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 21.940s | 1.960ms | 50 | 50 | 100.00 |
V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 11.080s | 2.458ms | 20 | 20 | 100.00 |
V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.178m | 664.864us | 50 | 50 | 100.00 |
V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.178m | 664.864us | 50 | 50 | 100.00 |
V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 29.574m | 13.631ms | 48 | 50 | 96.00 |
V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 21.940s | 1.960ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.178m | 664.864us | 50 | 50 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 2.870s | 330.332us | 5 | 5 | 100.00 |
V2S | TOTAL | 45 | 45 | 100.00 | |||
V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 2.022h | 27.070ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 1035 | 1040 | 99.52 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.26 | 99.16 | 93.54 | 100.00 | 70.00 | 97.41 | 99.70 | 100.00 |
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=*
has 3 failures:
Test sram_ctrl_executable has 2 failures.
4.sram_ctrl_executable.3520176824
Line 245, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest/run.log
UVM_FATAL @ 23576864550 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xc655202d
UVM_INFO @ 23576864550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_executable.237463031
Line 257, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest/run.log
UVM_FATAL @ 41944997752 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x57ab7a12
UVM_INFO @ 41944997752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_stress_all has 1 failures.
27.sram_ctrl_stress_all.2186920059
Line 267, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 84933595062 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x12416736
UVM_INFO @ 84933595062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=*
has 1 failures:
15.sram_ctrl_regwen.2496206975
Line 247, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 42773118114 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x715f334
UVM_INFO @ 42773118114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch
has 1 failures:
47.sram_ctrl_stress_all.595209057
Line 339, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 13645828875 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x6a [1101010] vs 0x19 [11001]) addr 0xe553e8d read out mismatch
UVM_INFO @ 13645828875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---