SRAM_CTRL/RET Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.817m	513.593us	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	93.064us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	172.927us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.370s	715.413us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.050s	25.071us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.950s	126.494us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	172.927us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	25.071us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.730s	2.713ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.240s	183.071us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	30.007m	33.474ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.819m	5.176ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.717m	3.868ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.628m	20.788ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.220s	931.544us	50	50	100.00
V2	executable	sram_ctrl_executable	30.311m	17.089ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.740m	743.830us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.098m	51.931ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.302m	2.598ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.902m	285.134us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.733m	108.282ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.400s	48.458us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.859h	384.307ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.110s	82.545us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.440s	292.781us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.440s	292.781us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	93.064us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	172.927us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	25.071us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.160s	43.983us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	93.064us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	172.927us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	25.071us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.160s	43.983us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.060s	1.053ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
		sram_ctrl_tl_intg_err	4.030s	190.432us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.030s	190.432us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.733m	108.282ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	27.733m	108.282ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	172.927us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.311m	17.089ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.311m	17.089ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.311m	17.089ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.220s	931.544us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.060s	1.053ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.940s	49.206us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.817m	513.593us	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.817m	513.593us	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.311m	17.089ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.220s	931.544us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.817m	513.593us	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.870s	387.798us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.519m	24.419ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1077	1090	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	16	16	15	93.75
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.63	99.48	96.05	99.72	100.00	97.29	99.12	98.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.7311154387300963426727285765311305993558566989918695742654414826545056343549
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5404669822 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5404669822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_stress_all_with_rand_reset.79710461014128912360023664604606402879826970213264848585280439327922736521260
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 605241470 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 605241470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.79719751246178792465911238482704845883051391891841631065674103079486474803463
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35215737 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  35215737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.39313218021730582409957296242294262238499673088137041766429078760078042194864
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  66912924 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  66912924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 7.sram_ctrl_smoke.66963794869203663214940362502812558073080867735871341817473361598814574545031
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 10489373694 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x369f54b3
  UVM_INFO @ 10489373694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 44.sram_ctrl_stress_all.55714066732271200692120910036584650839106040995371727745094465965942551144179
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 13734721475 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xb369a74d
  UVM_INFO @ 13734721475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `12e3b8572e`