SRAM_CTRL/RET Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.449m	8.875ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	20.077us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	33.829us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	411.132us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	49.675us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	152.116us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	33.829us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	49.675us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.050s	8.724ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.310s	177.871us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	22.250m	91.800ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.240m	4.104ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.290m	13.847ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.846m	5.097ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.380s	3.252ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.040m	20.456ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.146m	527.507us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.326m	24.326ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.502m	611.092us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.954m	611.881us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.353m	23.079ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.950s	87.957us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.304h	285.872ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.680s	12.392us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.000s	578.813us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.000s	578.813us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	20.077us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	33.829us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	49.675us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	84.852us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	20.077us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	33.829us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	49.675us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	84.852us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.840s	2.138ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.120s	3.643ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.120s	3.643ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.353m	23.079ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	33.829us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.040m	20.456ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.040m	20.456ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.040m	20.456ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.380s	3.252ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.840s	2.138ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.449m	8.875ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.449m	8.875ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.040m	20.456ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.380s	3.252ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.449m	8.875ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.190s	1.255ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.709m	2.426ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1019	1040	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 12 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.13019976870255096027146311011193642342142757759189366066507701761085123021537
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2276556097 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2276556097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_stress_all_with_rand_reset.58811979675623860966544001751150145689325519038745240824960100760571126681152
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 621811138 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 621811138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

15.sram_ctrl_stress_all.101934246620408776061045128790699280158064505594847150309066024643921206813127
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  95735981 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  95735981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.sram_ctrl_stress_all.47725863008350375817562275821956347697747000302389506287300978753544767577937
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  57311764 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  57311764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 0.sram_ctrl_executable.107327483244100628293608212802760897131004679540559437016951178887409372825608
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 26783829308 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7cdff954
  UVM_INFO @ 26783829308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_executable.28521411439169202919815489863512722571506437424643146898667758813308286398393
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 20829970033 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x483b5b62
  UVM_INFO @ 20829970033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.68856379837865697821754075658427707351666264684030386873756089514144480443958
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 317958428 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 317958428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 37.sram_ctrl_multiple_keys.92564266533605010453464352029169431926818768519002584874178688228834056339391
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 36963967484 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x15a430f7
  UVM_INFO @ 36963967484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```