SRAM_CTRL/RET Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.600s	427.865us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	23.779us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.320s	122.118us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.900s	42.440us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.870s	590.811us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.390s	166.171us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	16.770m	21.947ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.191m	6.491ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.460m	9.249ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.202m	4.471ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.450s	985.754us	50	50	100.00
V2	executable	sram_ctrl_executable	18.893m	23.162ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	15.020s	445.205us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.494m	42.306ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.219m	209.242us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.438m	237.420us	50	50	100.00
V2	regwen	sram_ctrl_regwen	11.510m	19.384ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.930s	40.672us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.114h	121.463ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.670s	16.601us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.490s	117.100us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.490s	117.100us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	23.779us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.700s	23.886us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	23.779us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.700s	23.886us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.990s	362.187us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
		sram_ctrl_tl_intg_err	1.570s	163.314us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.570s	163.314us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.510m	19.384ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	18.893m	23.162ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	18.893m	23.162ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	18.893m	23.162ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.450s	985.754us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.990s	362.187us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.600s	427.865us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.600s	427.865us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	18.893m	23.162ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.450s	985.754us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.600s	427.865us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.000s	216.403us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.332m	624.328us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1040	1040	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.95	100.00	97.69	99.14	100.00	99.71	99.70	96.44

Past Results

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