Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148482282	1			T1	12284		T2	10326		T3	747882
instr_valid_dis	115964131	1			T1	12284		T2	10326		T3	747882
instr_en	22998948	1			T21	5571		T22	478516		T14	184976

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10632745	1			T7	64456		T21	5571		T22	225930
sram_ifetch_valid_disable	115442458	1			T1	12284		T2	10326		T3	747882
sram_ifetch_enable	22407079	1			T7	186660		T22	164962		T14	486756

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148482282	1			T1	12284		T2	10326		T3	747882
hw_debug_en_valid_off	114609994	1			T1	12284		T2	10326		T3	747882
hw_debug_en_on	22655329	1			T7	254812		T22	269336		T14	408570

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115442458	1			T1	12284		T2	10326		T3	747882
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102146367	1			T1	12284		T2	10326		T3	747882
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9446010	1			T22	87624		T14	8880		T121	167600
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3811783	1			T22	32514		T122	84		T41	36280
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1411131	1			T128	17730		T129	73806		T131	2186
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1703670	1			T22	32514		T122	84		T41	36280
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4475854	1			T22	131736		T14	33744		T121	77118
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1939772	1			T122	20000		T132	58014		T133	14844
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1981046	1			T22	131736		T14	33744		T121	77118
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8875782	1			T7	139904		T22	74980		T14	118866
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3402750	1			T14	35720		T122	41290		T120	81902
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3789056	1			T22	39316		T14	7592		T121	20064

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8971482	1			T22	164962		T14	121032		T121	113526
lc_exec_en	9303693	1			T7	114908		T22	62620		T14	255960
valid_exec_dis	111369831	1			T1	12284		T2	10326		T3	747882
invalid_exec_dis	33039824	1			T7	251116		T21	5571		T22	390892