Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total tests in report: 1028
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.94 87.94 98.10 98.10 77.20 77.20 86.47 86.47 100.00 100.00 91.15 91.15 94.90 94.90 67.73 67.73 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3920933804
93.28 5.35 99.15 1.04 90.04 12.84 96.99 10.52 100.00 0.00 97.05 5.90 94.90 0.00 74.86 7.13 /workspace/coverage/default/35.sram_ctrl_stress_all.4036888176
96.04 2.76 99.53 0.38 94.23 4.18 97.49 0.50 100.00 0.00 97.94 0.88 96.25 1.35 86.87 12.01 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.884198536
97.13 1.08 99.72 0.19 95.09 0.87 98.07 0.57 100.00 0.00 98.82 0.88 96.25 0.00 91.93 5.07 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.713464219
97.78 0.65 99.91 0.19 97.26 2.16 98.43 0.36 100.00 0.00 99.71 0.88 96.85 0.60 92.31 0.38 /workspace/coverage/default/2.sram_ctrl_sec_cm.1043482987
98.27 0.49 99.91 0.00 97.26 0.00 99.25 0.82 100.00 0.00 99.71 0.00 96.85 0.00 94.93 2.63 /workspace/coverage/default/22.sram_ctrl_regwen.375381159
98.52 0.25 99.91 0.00 97.26 0.00 99.25 0.00 100.00 0.00 99.71 0.00 97.30 0.45 96.25 1.31 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4077538236
98.75 0.23 99.91 0.00 97.55 0.29 99.28 0.04 100.00 0.00 99.71 0.00 98.20 0.90 96.62 0.38 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.349644446
98.92 0.17 99.91 0.00 97.55 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.40 1.20 96.62 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2180921332
99.08 0.16 99.91 0.00 97.55 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.40 0.00 97.75 1.13 /workspace/coverage/default/34.sram_ctrl_executable.283285512
99.24 0.16 99.91 0.00 97.55 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.55 0.15 98.69 0.94 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.221817466
99.36 0.12 100.00 0.09 97.55 0.00 100.00 0.72 100.00 0.00 99.71 0.00 99.55 0.00 98.69 0.00 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2675764488
99.44 0.08 100.00 0.00 97.55 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.25 0.56 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4103302842
99.51 0.07 100.00 0.00 97.69 0.14 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.62 0.38 /workspace/coverage/default/14.sram_ctrl_stress_all.3541140425
99.55 0.04 100.00 0.00 97.98 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.62 0.00 /workspace/coverage/default/12.sram_ctrl_alert_test.1730614155
99.58 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.81 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.250746878
99.61 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 100.00 0.19 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2234412100
99.63 0.02 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.15 100.00 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3681546538

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4275038454
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.110237628
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3628232554
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1626709471
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1733161199
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2723819927
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1322663047
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3804290263
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1109668316
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.70288961
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3676096953
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.353527323
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4238720383
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2264853204
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1742743466
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.868093873
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3552669190
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1929484570
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1063053132
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3274844310
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3576135926
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.121437900
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3365240948
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3716533836
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.756953250
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.335094954
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3831731534
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3195125774
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1769701249
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1173789455
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1183761335
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2762797685
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2071714476
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2923998622
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2833392682
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4176809807
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.711317031
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1335312838
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1203055515
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.252822174
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1572538705
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1624902036
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2899232722
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3796313990
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3317496132
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.31790909
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.379869594
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1013235478
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2620115827
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2693029427
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3370744741
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2432420267
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4024618446
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1846034115
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2844946381
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3792280545
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1777426893
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2203013687
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2836262982
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2973883291
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3920999224
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4047057368
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2601918936
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4254635619
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2706939857
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1093485361
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3338085891
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1360710448
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3151522893
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2008318548
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1738190695
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.428219443
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.892658686
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1889514202
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4018284860
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2351515888
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2873867090
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2589652400
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.696713903
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.48788199
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4227561052
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1671978962
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2762834971
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2264394542
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1169578040
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3375504488
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1701277109
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1189764839
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3656755946
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1091631278
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1452463414
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1888578638
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2850593942
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.637049155
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.454490218
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2561035767
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1111497659
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1939331551
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3197412270
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2099850965
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.681578342
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2265159721
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2498453515
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.426821753
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1642895032
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2518288593
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1388186237
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.340882422
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1997585948
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3631839616
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.492454820
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.101550169
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1911259871
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.976896020
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3250830384
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2121664997
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3126459963
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.835516215
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.996612064
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1157037482
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2965814893
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.411436689
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3697656609
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1685537425
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.143886142
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3368182346
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3402752384
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1785342603
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2995247060
/workspace/coverage/default/0.sram_ctrl_alert_test.313871267
/workspace/coverage/default/0.sram_ctrl_bijection.3532353867
/workspace/coverage/default/0.sram_ctrl_executable.47573834
/workspace/coverage/default/0.sram_ctrl_lc_escalation.161409337
/workspace/coverage/default/0.sram_ctrl_max_throughput.3110608499
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2949087021
/workspace/coverage/default/0.sram_ctrl_mem_walk.992875862
/workspace/coverage/default/0.sram_ctrl_multiple_keys.984261040
/workspace/coverage/default/0.sram_ctrl_partial_access.4132164418
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2138722559
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2026912734
/workspace/coverage/default/0.sram_ctrl_regwen.1094905697
/workspace/coverage/default/0.sram_ctrl_sec_cm.546995986
/workspace/coverage/default/0.sram_ctrl_smoke.2699086946
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.804986550
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2567231328
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.663845101
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2402007364
/workspace/coverage/default/1.sram_ctrl_alert_test.4256329703
/workspace/coverage/default/1.sram_ctrl_bijection.1127040279
/workspace/coverage/default/1.sram_ctrl_executable.1038313280
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3737574470
/workspace/coverage/default/1.sram_ctrl_max_throughput.1872017164
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.548503047
/workspace/coverage/default/1.sram_ctrl_mem_walk.1179476952
/workspace/coverage/default/1.sram_ctrl_multiple_keys.642662914
/workspace/coverage/default/1.sram_ctrl_partial_access.2299586998
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.659906275
/workspace/coverage/default/1.sram_ctrl_ram_cfg.821759606
/workspace/coverage/default/1.sram_ctrl_regwen.1110450603
/workspace/coverage/default/1.sram_ctrl_sec_cm.4124540220
/workspace/coverage/default/1.sram_ctrl_smoke.3782643253
/workspace/coverage/default/1.sram_ctrl_stress_all.2488640130
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1728630092
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.998574957
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3112655964
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1066933832
/workspace/coverage/default/10.sram_ctrl_alert_test.4013844196
/workspace/coverage/default/10.sram_ctrl_bijection.1302223561
/workspace/coverage/default/10.sram_ctrl_executable.726765930
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2980702512
/workspace/coverage/default/10.sram_ctrl_max_throughput.2673204340
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2250560131
/workspace/coverage/default/10.sram_ctrl_mem_walk.90602682
/workspace/coverage/default/10.sram_ctrl_multiple_keys.61838222
/workspace/coverage/default/10.sram_ctrl_partial_access.2793920609
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1751049101
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1373420903
/workspace/coverage/default/10.sram_ctrl_regwen.1118277397
/workspace/coverage/default/10.sram_ctrl_smoke.1746639693
/workspace/coverage/default/10.sram_ctrl_stress_all.2873357237
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.852427697
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4053295937
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.578001262
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1006166364
/workspace/coverage/default/11.sram_ctrl_alert_test.3270309638
/workspace/coverage/default/11.sram_ctrl_bijection.1230919411
/workspace/coverage/default/11.sram_ctrl_executable.1297306742
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4285404984
/workspace/coverage/default/11.sram_ctrl_max_throughput.521899580
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3001639987
/workspace/coverage/default/11.sram_ctrl_mem_walk.2741378760
/workspace/coverage/default/11.sram_ctrl_multiple_keys.427491758
/workspace/coverage/default/11.sram_ctrl_partial_access.702138892
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4102293989
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2726350003
/workspace/coverage/default/11.sram_ctrl_regwen.683187905
/workspace/coverage/default/11.sram_ctrl_smoke.4082883155
/workspace/coverage/default/11.sram_ctrl_stress_all.3288261338
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1374688013
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.956072393
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3536179490
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1515342460
/workspace/coverage/default/12.sram_ctrl_bijection.3560290079
/workspace/coverage/default/12.sram_ctrl_executable.1560996289
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2804469302
/workspace/coverage/default/12.sram_ctrl_max_throughput.243792960
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.425279548
/workspace/coverage/default/12.sram_ctrl_mem_walk.2729973971
/workspace/coverage/default/12.sram_ctrl_multiple_keys.940077626
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/workspace/coverage/default/43.sram_ctrl_multiple_keys.1120222697
/workspace/coverage/default/43.sram_ctrl_partial_access.1641152933
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3690057911
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2083382602
/workspace/coverage/default/43.sram_ctrl_regwen.964929025
/workspace/coverage/default/43.sram_ctrl_smoke.3669747745
/workspace/coverage/default/43.sram_ctrl_stress_all.3178805693
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4186092895
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1404509804
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1622825847
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1055716992
/workspace/coverage/default/44.sram_ctrl_alert_test.3980946866
/workspace/coverage/default/44.sram_ctrl_bijection.2486717401
/workspace/coverage/default/44.sram_ctrl_executable.3213500212
/workspace/coverage/default/44.sram_ctrl_lc_escalation.89851348
/workspace/coverage/default/44.sram_ctrl_max_throughput.1344176826
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.684300860
/workspace/coverage/default/44.sram_ctrl_mem_walk.2420490418
/workspace/coverage/default/44.sram_ctrl_multiple_keys.145237340
/workspace/coverage/default/44.sram_ctrl_partial_access.3422922337
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2851853448
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3251935764
/workspace/coverage/default/44.sram_ctrl_regwen.564995351
/workspace/coverage/default/44.sram_ctrl_smoke.3039529093
/workspace/coverage/default/44.sram_ctrl_stress_all.4146534265
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2307520319
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3761400771
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2458700728
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2744486826
/workspace/coverage/default/45.sram_ctrl_alert_test.1632771890
/workspace/coverage/default/45.sram_ctrl_bijection.1989833732
/workspace/coverage/default/45.sram_ctrl_executable.1420477347
/workspace/coverage/default/45.sram_ctrl_lc_escalation.513927503
/workspace/coverage/default/45.sram_ctrl_max_throughput.3179771798
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3272763255
/workspace/coverage/default/45.sram_ctrl_mem_walk.352462408
/workspace/coverage/default/45.sram_ctrl_multiple_keys.70631632
/workspace/coverage/default/45.sram_ctrl_partial_access.4018929815
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.585074343
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3314878471
/workspace/coverage/default/45.sram_ctrl_regwen.3190686884
/workspace/coverage/default/45.sram_ctrl_smoke.903235494
/workspace/coverage/default/45.sram_ctrl_stress_all.1225443033
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2823054004
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.108905191
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3623755863
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3876118648
/workspace/coverage/default/46.sram_ctrl_alert_test.3128583474
/workspace/coverage/default/46.sram_ctrl_bijection.2174843752
/workspace/coverage/default/46.sram_ctrl_executable.1199716988
/workspace/coverage/default/46.sram_ctrl_max_throughput.4117372459
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2230991816
/workspace/coverage/default/46.sram_ctrl_mem_walk.3681667872
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2745351255
/workspace/coverage/default/46.sram_ctrl_partial_access.4003508959
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1393233726
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1512846522
/workspace/coverage/default/46.sram_ctrl_regwen.547378202
/workspace/coverage/default/46.sram_ctrl_smoke.2607513639
/workspace/coverage/default/46.sram_ctrl_stress_all.2236473665
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1359263295
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1357978084
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.746244336
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.603545918
/workspace/coverage/default/47.sram_ctrl_alert_test.3069442961
/workspace/coverage/default/47.sram_ctrl_bijection.2772806570
/workspace/coverage/default/47.sram_ctrl_executable.395592220
/workspace/coverage/default/47.sram_ctrl_max_throughput.664683512
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.332596455
/workspace/coverage/default/47.sram_ctrl_mem_walk.4240304529
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2549919657
/workspace/coverage/default/47.sram_ctrl_partial_access.947559690
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.150898350
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2803085012
/workspace/coverage/default/47.sram_ctrl_regwen.2519409121
/workspace/coverage/default/47.sram_ctrl_smoke.743688922
/workspace/coverage/default/47.sram_ctrl_stress_all.4079939626
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3809644524
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3409313054
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.875697872
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3615593674
/workspace/coverage/default/48.sram_ctrl_alert_test.3245971210
/workspace/coverage/default/48.sram_ctrl_bijection.4177430642
/workspace/coverage/default/48.sram_ctrl_executable.1722435814
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3919314939
/workspace/coverage/default/48.sram_ctrl_max_throughput.3854422328
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4147373091
/workspace/coverage/default/48.sram_ctrl_mem_walk.2806463876
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3922358696
/workspace/coverage/default/48.sram_ctrl_partial_access.3597583639
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1540885904
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1638060789
/workspace/coverage/default/48.sram_ctrl_regwen.477664737
/workspace/coverage/default/48.sram_ctrl_smoke.99628096
/workspace/coverage/default/48.sram_ctrl_stress_all.3161638276
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3544586681
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1213853671
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2494058902
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3308451958
/workspace/coverage/default/49.sram_ctrl_alert_test.123049001
/workspace/coverage/default/49.sram_ctrl_bijection.2941756080
/workspace/coverage/default/49.sram_ctrl_executable.2366144965
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3202765644
/workspace/coverage/default/49.sram_ctrl_max_throughput.1055591175
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2788212478
/workspace/coverage/default/49.sram_ctrl_mem_walk.108245973
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4133315440
/workspace/coverage/default/49.sram_ctrl_partial_access.1910837292
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2040671881
/workspace/coverage/default/49.sram_ctrl_ram_cfg.889070853
/workspace/coverage/default/49.sram_ctrl_regwen.700894003
/workspace/coverage/default/49.sram_ctrl_smoke.3435151327
/workspace/coverage/default/49.sram_ctrl_stress_all.1754629106
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.832502047
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1137334475
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1297344726
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4121574725
/workspace/coverage/default/5.sram_ctrl_alert_test.395643188
/workspace/coverage/default/5.sram_ctrl_bijection.2510190206
/workspace/coverage/default/5.sram_ctrl_executable.1007024165
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2704718270
/workspace/coverage/default/5.sram_ctrl_max_throughput.1625057604
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3338688575
/workspace/coverage/default/5.sram_ctrl_mem_walk.2436728241
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2809503408
/workspace/coverage/default/5.sram_ctrl_partial_access.806294012
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2399491260
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3929833296
/workspace/coverage/default/5.sram_ctrl_regwen.741247225
/workspace/coverage/default/5.sram_ctrl_smoke.2647355738
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.114470798
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3769707538
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2269023721
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.623869380
/workspace/coverage/default/6.sram_ctrl_alert_test.710677756
/workspace/coverage/default/6.sram_ctrl_bijection.3702158353
/workspace/coverage/default/6.sram_ctrl_executable.4093547052
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2068544090
/workspace/coverage/default/6.sram_ctrl_max_throughput.2736200453
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2827298626
/workspace/coverage/default/6.sram_ctrl_mem_walk.910628645
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1698289402
/workspace/coverage/default/6.sram_ctrl_partial_access.473665811
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1939407798
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2051521570
/workspace/coverage/default/6.sram_ctrl_regwen.1510954251
/workspace/coverage/default/6.sram_ctrl_smoke.1259828786
/workspace/coverage/default/6.sram_ctrl_stress_all.2842724146
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3795275852
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.657536454
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2737365319
/workspace/coverage/default/7.sram_ctrl_alert_test.1868130227
/workspace/coverage/default/7.sram_ctrl_bijection.3116379748
/workspace/coverage/default/7.sram_ctrl_executable.3992527664
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3445300524
/workspace/coverage/default/7.sram_ctrl_max_throughput.4115056856
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1401547856
/workspace/coverage/default/7.sram_ctrl_mem_walk.2902502351
/workspace/coverage/default/7.sram_ctrl_multiple_keys.759958087
/workspace/coverage/default/7.sram_ctrl_partial_access.2790023284
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3744801722
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2140631967
/workspace/coverage/default/7.sram_ctrl_regwen.1801651427
/workspace/coverage/default/7.sram_ctrl_smoke.1359680272
/workspace/coverage/default/7.sram_ctrl_stress_all.2181320349
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4024214156
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2417666073
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.835586473
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3628323742
/workspace/coverage/default/8.sram_ctrl_alert_test.2158875914
/workspace/coverage/default/8.sram_ctrl_bijection.1194570795
/workspace/coverage/default/8.sram_ctrl_executable.2729882955
/workspace/coverage/default/8.sram_ctrl_lc_escalation.175464134
/workspace/coverage/default/8.sram_ctrl_max_throughput.1617675638
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1686915957
/workspace/coverage/default/8.sram_ctrl_mem_walk.1282131215
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3801345512
/workspace/coverage/default/8.sram_ctrl_partial_access.4208838401
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.540386392
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3632396669
/workspace/coverage/default/8.sram_ctrl_regwen.4103132547
/workspace/coverage/default/8.sram_ctrl_smoke.1573547295
/workspace/coverage/default/8.sram_ctrl_stress_all.93937236
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1323933193
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2823279589
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.704932515
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3430506291
/workspace/coverage/default/9.sram_ctrl_alert_test.3102120225
/workspace/coverage/default/9.sram_ctrl_bijection.610754097
/workspace/coverage/default/9.sram_ctrl_executable.2689237159
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2347470478
/workspace/coverage/default/9.sram_ctrl_max_throughput.2068852702
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1434818755
/workspace/coverage/default/9.sram_ctrl_mem_walk.1122736892
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3676799085
/workspace/coverage/default/9.sram_ctrl_partial_access.1482157390
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4192486940
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3623983417
/workspace/coverage/default/9.sram_ctrl_regwen.3684247898
/workspace/coverage/default/9.sram_ctrl_smoke.1676181071
/workspace/coverage/default/9.sram_ctrl_stress_all.1502956654
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1555291209
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1536235314
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3678663328



Total test records in report: 1028
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/43.sram_ctrl_mem_walk.3875188958 Dec 20 01:01:49 PM PST 23 Dec 20 01:02:42 PM PST 23 441208153 ps
T2 /workspace/coverage/default/21.sram_ctrl_max_throughput.1701442579 Dec 20 12:59:20 PM PST 23 Dec 20 01:00:00 PM PST 23 317858903 ps
T3 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.540386392 Dec 20 12:58:14 PM PST 23 Dec 20 01:09:27 PM PST 23 31419743573 ps
T4 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3043505834 Dec 20 12:59:08 PM PST 23 Dec 20 01:02:57 PM PST 23 2361623531 ps
T9 /workspace/coverage/default/39.sram_ctrl_alert_test.3960653775 Dec 20 01:01:32 PM PST 23 Dec 20 01:02:08 PM PST 23 39526546 ps
T10 /workspace/coverage/default/7.sram_ctrl_alert_test.1868130227 Dec 20 12:58:11 PM PST 23 Dec 20 12:58:30 PM PST 23 22693810 ps
T11 /workspace/coverage/default/12.sram_ctrl_alert_test.1730614155 Dec 20 12:58:21 PM PST 23 Dec 20 12:58:38 PM PST 23 16119490 ps
T5 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3920933804 Dec 20 12:59:13 PM PST 23 Dec 20 12:59:40 PM PST 23 847005697 ps
T12 /workspace/coverage/default/35.sram_ctrl_alert_test.620557526 Dec 20 01:01:01 PM PST 23 Dec 20 01:01:40 PM PST 23 27089809 ps
T13 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2287142843 Dec 20 01:00:25 PM PST 23 Dec 20 01:00:36 PM PST 23 78401146 ps
T16 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3329023032 Dec 20 01:00:48 PM PST 23 Dec 20 01:04:30 PM PST 23 4455432246 ps
T6 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.445064919 Dec 20 01:00:05 PM PST 23 Dec 20 01:03:45 PM PST 23 22892482297 ps
T17 /workspace/coverage/default/2.sram_ctrl_smoke.493303243 Dec 20 12:57:58 PM PST 23 Dec 20 01:00:24 PM PST 23 143862530 ps
T18 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2402007364 Dec 20 12:58:23 PM PST 23 Dec 20 01:01:11 PM PST 23 805623031 ps
T19 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.349644446 Dec 20 12:58:17 PM PST 23 Dec 20 01:20:32 PM PST 23 16367907251 ps
T31 /workspace/coverage/default/20.sram_ctrl_ram_cfg.2236045503 Dec 20 12:59:13 PM PST 23 Dec 20 12:59:29 PM PST 23 82964386 ps
T20 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3657202152 Dec 20 01:00:50 PM PST 23 Dec 20 01:05:58 PM PST 23 2877174927 ps
T134 /workspace/coverage/default/38.sram_ctrl_mem_walk.3019161854 Dec 20 01:01:16 PM PST 23 Dec 20 01:02:08 PM PST 23 1837796696 ps
T15 /workspace/coverage/default/48.sram_ctrl_smoke.99628096 Dec 20 01:02:29 PM PST 23 Dec 20 01:03:08 PM PST 23 909235279 ps
T32 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2230218048 Dec 20 01:01:35 PM PST 23 Dec 20 01:02:11 PM PST 23 91970616 ps
T69 /workspace/coverage/default/38.sram_ctrl_smoke.1578779950 Dec 20 01:01:26 PM PST 23 Dec 20 01:02:15 PM PST 23 212350633 ps
T105 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2753327284 Dec 20 01:01:33 PM PST 23 Dec 20 01:02:10 PM PST 23 82924665 ps
T135 /workspace/coverage/default/5.sram_ctrl_ram_cfg.3929833296 Dec 20 12:58:15 PM PST 23 Dec 20 12:58:35 PM PST 23 267890376 ps
T44 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2675764488 Dec 20 12:59:08 PM PST 23 Dec 20 12:59:23 PM PST 23 91977668 ps
T136 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.550260424 Dec 20 01:00:07 PM PST 23 Dec 20 01:00:22 PM PST 23 43315350 ps
T137 /workspace/coverage/default/36.sram_ctrl_mem_walk.611129149 Dec 20 01:01:01 PM PST 23 Dec 20 01:01:47 PM PST 23 596291894 ps
T7 /workspace/coverage/default/35.sram_ctrl_stress_all.4036888176 Dec 20 01:01:01 PM PST 23 Dec 20 01:42:07 PM PST 23 54258110681 ps
T8 /workspace/coverage/default/28.sram_ctrl_lc_escalation.3353108393 Dec 20 01:00:37 PM PST 23 Dec 20 01:00:58 PM PST 23 666377466 ps
T138 /workspace/coverage/default/42.sram_ctrl_mem_walk.2510772674 Dec 20 01:01:38 PM PST 23 Dec 20 01:02:27 PM PST 23 534049005 ps
T139 /workspace/coverage/default/40.sram_ctrl_smoke.2787425187 Dec 20 01:01:30 PM PST 23 Dec 20 01:02:15 PM PST 23 264134383 ps
T140 /workspace/coverage/default/14.sram_ctrl_mem_walk.292638431 Dec 20 12:58:30 PM PST 23 Dec 20 12:58:58 PM PST 23 1302471819 ps
T141 /workspace/coverage/default/11.sram_ctrl_mem_walk.2741378760 Dec 20 12:58:31 PM PST 23 Dec 20 12:58:53 PM PST 23 77849101 ps
T21 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.884198536 Dec 20 12:58:21 PM PST 23 Dec 20 01:21:29 PM PST 23 725948827 ps
T53 /workspace/coverage/default/21.sram_ctrl_mem_walk.1000609431 Dec 20 12:59:34 PM PST 23 Dec 20 12:59:56 PM PST 23 653277406 ps
T54 /workspace/coverage/default/3.sram_ctrl_max_throughput.1478321436 Dec 20 12:58:18 PM PST 23 Dec 20 12:58:38 PM PST 23 41524418 ps
T55 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.794540949 Dec 20 01:00:10 PM PST 23 Dec 20 01:04:02 PM PST 23 35065849958 ps
T56 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.924908549 Dec 20 12:59:27 PM PST 23 Dec 20 01:04:50 PM PST 23 42795773926 ps
T57 /workspace/coverage/default/37.sram_ctrl_alert_test.683715904 Dec 20 01:01:16 PM PST 23 Dec 20 01:01:59 PM PST 23 20404892 ps
T58 /workspace/coverage/default/29.sram_ctrl_bijection.93013705 Dec 20 01:01:04 PM PST 23 Dec 20 01:02:42 PM PST 23 3854656538 ps
T22 /workspace/coverage/default/22.sram_ctrl_regwen.375381159 Dec 20 12:59:24 PM PST 23 Dec 20 01:18:02 PM PST 23 18096091404 ps
T142 /workspace/coverage/default/5.sram_ctrl_lc_escalation.2704718270 Dec 20 12:58:07 PM PST 23 Dec 20 12:58:30 PM PST 23 2939832644 ps
T76 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3853472620 Dec 20 01:01:34 PM PST 23 Dec 20 01:02:14 PM PST 23 67217147 ps
T143 /workspace/coverage/default/5.sram_ctrl_smoke.2647355738 Dec 20 12:58:06 PM PST 23 Dec 20 12:58:24 PM PST 23 158001708 ps
T14 /workspace/coverage/default/29.sram_ctrl_stress_all.784723835 Dec 20 01:00:39 PM PST 23 Dec 20 01:31:43 PM PST 23 73019735913 ps
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T144 /workspace/coverage/default/23.sram_ctrl_max_throughput.1994609133 Dec 20 12:59:27 PM PST 23 Dec 20 01:00:07 PM PST 23 343576908 ps
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T29 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2856542402 Dec 20 12:59:23 PM PST 23 Dec 20 01:12:18 PM PST 23 230668740 ps
T59 /workspace/coverage/default/37.sram_ctrl_stress_all.1018156437 Dec 20 01:01:25 PM PST 23 Dec 20 01:19:37 PM PST 23 11426596114 ps
T30 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4186092895 Dec 20 01:01:45 PM PST 23 Dec 20 01:18:40 PM PST 23 798576267 ps
T146 /workspace/coverage/default/41.sram_ctrl_partial_access.389847078 Dec 20 01:01:32 PM PST 23 Dec 20 01:03:10 PM PST 23 313298399 ps
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T100 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2417666073 Dec 20 12:58:11 PM PST 23 Dec 20 01:03:09 PM PST 23 5898063752 ps
T148 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3115666173 Dec 20 01:00:05 PM PST 23 Dec 20 01:12:53 PM PST 23 12164524731 ps
T149 /workspace/coverage/default/37.sram_ctrl_bijection.3494305015 Dec 20 01:00:51 PM PST 23 Dec 20 01:02:14 PM PST 23 2565431339 ps
T150 /workspace/coverage/default/38.sram_ctrl_max_throughput.3777756149 Dec 20 01:01:17 PM PST 23 Dec 20 01:02:26 PM PST 23 89444613 ps
T101 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.221817466 Dec 20 12:59:45 PM PST 23 Dec 20 01:05:33 PM PST 23 61218392956 ps
T102 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.876662960 Dec 20 01:00:48 PM PST 23 Dec 20 01:04:25 PM PST 23 2354146421 ps
T77 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.966904236 Dec 20 12:58:24 PM PST 23 Dec 20 01:00:27 PM PST 23 10854374544 ps
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T151 /workspace/coverage/default/18.sram_ctrl_partial_access.3374894972 Dec 20 12:59:03 PM PST 23 Dec 20 01:01:17 PM PST 23 621603936 ps
T152 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3409313054 Dec 20 01:03:02 PM PST 23 Dec 20 01:06:26 PM PST 23 10401378041 ps
T120 /workspace/coverage/default/7.sram_ctrl_stress_all.2181320349 Dec 20 12:58:12 PM PST 23 Dec 20 01:46:06 PM PST 23 161156501884 ps
T153 /workspace/coverage/default/5.sram_ctrl_max_throughput.1625057604 Dec 20 12:58:05 PM PST 23 Dec 20 12:58:27 PM PST 23 53156833 ps
T78 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4121574725 Dec 20 12:58:03 PM PST 23 Dec 20 01:20:37 PM PST 23 4605061566 ps
T154 /workspace/coverage/default/18.sram_ctrl_max_throughput.51344781 Dec 20 12:59:06 PM PST 23 Dec 20 01:01:20 PM PST 23 279704502 ps
T155 /workspace/coverage/default/6.sram_ctrl_partial_access.473665811 Dec 20 12:58:24 PM PST 23 Dec 20 12:59:02 PM PST 23 4402799056 ps
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T79 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.80797069 Dec 20 01:00:48 PM PST 23 Dec 20 01:17:17 PM PST 23 3791877057 ps
T156 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1393233726 Dec 20 01:02:23 PM PST 23 Dec 20 01:09:16 PM PST 23 14735335668 ps
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T26 /workspace/coverage/default/17.sram_ctrl_regwen.444766429 Dec 20 12:59:07 PM PST 23 Dec 20 01:12:51 PM PST 23 2985514022 ps
T158 /workspace/coverage/default/15.sram_ctrl_max_throughput.1006006532 Dec 20 12:58:42 PM PST 23 Dec 20 12:59:20 PM PST 23 289570364 ps
T130 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3342230774 Dec 20 12:58:48 PM PST 23 Dec 20 01:06:25 PM PST 23 79782650206 ps
T159 /workspace/coverage/default/19.sram_ctrl_max_throughput.762276420 Dec 20 12:59:09 PM PST 23 Dec 20 12:59:34 PM PST 23 67679626 ps
T80 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4147373091 Dec 20 01:02:26 PM PST 23 Dec 20 01:02:52 PM PST 23 150783759 ps
T81 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2827298626 Dec 20 12:58:15 PM PST 23 Dec 20 12:58:38 PM PST 23 146792686 ps
T45 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3293063429 Dec 20 01:00:44 PM PST 23 Dec 20 01:17:10 PM PST 23 1087461724 ps
T23 /workspace/coverage/default/2.sram_ctrl_sec_cm.1043482987 Dec 20 12:58:04 PM PST 23 Dec 20 12:58:24 PM PST 23 465672765 ps
T35 /workspace/coverage/default/12.sram_ctrl_executable.1560996289 Dec 20 12:58:24 PM PST 23 Dec 20 01:15:00 PM PST 23 17489454003 ps
T160 /workspace/coverage/default/48.sram_ctrl_bijection.4177430642 Dec 20 01:02:43 PM PST 23 Dec 20 01:04:25 PM PST 23 6973422020 ps
T82 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2230991816 Dec 20 01:02:41 PM PST 23 Dec 20 01:03:10 PM PST 23 637071824 ps
T161 /workspace/coverage/default/21.sram_ctrl_partial_access.2660050894 Dec 20 12:59:17 PM PST 23 Dec 20 12:59:44 PM PST 23 1535088441 ps
T162 /workspace/coverage/default/0.sram_ctrl_max_throughput.3110608499 Dec 20 12:58:41 PM PST 23 Dec 20 01:00:55 PM PST 23 134405555 ps
T163 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.332596455 Dec 20 01:03:00 PM PST 23 Dec 20 01:03:25 PM PST 23 375725823 ps
T164 /workspace/coverage/default/37.sram_ctrl_multiple_keys.1695953056 Dec 20 01:00:53 PM PST 23 Dec 20 01:10:08 PM PST 23 56948222261 ps
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T166 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2494058902 Dec 20 01:02:27 PM PST 23 Dec 20 01:03:33 PM PST 23 212416457 ps
T167 /workspace/coverage/default/25.sram_ctrl_bijection.862897370 Dec 20 01:00:17 PM PST 23 Dec 20 01:01:47 PM PST 23 13856692127 ps
T168 /workspace/coverage/default/3.sram_ctrl_multiple_keys.2791525045 Dec 20 12:58:02 PM PST 23 Dec 20 01:13:52 PM PST 23 91225572366 ps
T169 /workspace/coverage/default/26.sram_ctrl_multiple_keys.3453772983 Dec 20 01:00:24 PM PST 23 Dec 20 01:08:35 PM PST 23 32235516153 ps
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T129 /workspace/coverage/default/25.sram_ctrl_stress_all.145483696 Dec 20 01:00:05 PM PST 23 Dec 20 01:20:08 PM PST 23 22303824491 ps
T62 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.379869594 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:19 PM PST 23 24189940 ps
T42 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.713464219 Dec 20 12:25:16 PM PST 23 Dec 20 12:25:37 PM PST 23 75681135 ps
T46 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2264394542 Dec 20 12:24:24 PM PST 23 Dec 20 12:24:57 PM PST 23 123153265 ps
T63 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.101550169 Dec 20 12:24:00 PM PST 23 Dec 20 12:24:40 PM PST 23 17129841 ps
T64 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3716533836 Dec 20 12:24:17 PM PST 23 Dec 20 12:25:05 PM PST 23 510540560 ps
T104 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.110237628 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:04 PM PST 23 73219110 ps
T47 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3197412270 Dec 20 12:27:37 PM PST 23 Dec 20 12:28:13 PM PST 23 59469339 ps
T99 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1322663047 Dec 20 12:24:02 PM PST 23 Dec 20 12:24:42 PM PST 23 13721417 ps
T65 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2180921332 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:52 PM PST 23 14456557 ps
T48 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3804290263 Dec 20 12:25:16 PM PST 23 Dec 20 12:25:40 PM PST 23 287075327 ps
T43 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4077538236 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:54 PM PST 23 177828483 ps
T66 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2899232722 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:07 PM PST 23 24886835 ps
T49 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.492454820 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:35 PM PST 23 63749359 ps
T67 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1685537425 Dec 20 12:24:12 PM PST 23 Dec 20 12:24:49 PM PST 23 23337390 ps
T68 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1701277109 Dec 20 12:24:26 PM PST 23 Dec 20 12:24:59 PM PST 23 19237146 ps
T70 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4176809807 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:41 PM PST 23 208133837 ps
T75 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1183761335 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:00 PM PST 23 26802215 ps
T71 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1388186237 Dec 20 12:24:15 PM PST 23 Dec 20 12:24:56 PM PST 23 815749011 ps
T50 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2498453515 Dec 20 12:24:19 PM PST 23 Dec 20 12:24:57 PM PST 23 49991034 ps
T103 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1929484570 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:58 PM PST 23 24294420 ps
T72 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1846034115 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:39 PM PST 23 916425291 ps
T51 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2071714476 Dec 20 12:24:51 PM PST 23 Dec 20 12:25:22 PM PST 23 961382800 ps
T90 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1157037482 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:51 PM PST 23 57085210 ps
T73 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1173789455 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:36 PM PST 23 1455054043 ps
T91 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1785342603 Dec 20 12:25:12 PM PST 23 Dec 20 12:25:31 PM PST 23 123682219 ps
T74 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1013235478 Dec 20 12:25:51 PM PST 23 Dec 20 12:26:27 PM PST 23 450420218 ps
T52 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.48788199 Dec 20 12:24:19 PM PST 23 Dec 20 12:24:56 PM PST 23 112546852 ps
T108 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1738190695 Dec 20 12:25:24 PM PST 23 Dec 20 12:25:50 PM PST 23 42881558 ps
T106 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2561035767 Dec 20 12:23:55 PM PST 23 Dec 20 12:24:37 PM PST 23 30149353 ps
T60 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3920999224 Dec 20 12:24:29 PM PST 23 Dec 20 12:25:04 PM PST 23 34660142 ps
T61 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.121437900 Dec 20 12:24:18 PM PST 23 Dec 20 12:24:55 PM PST 23 95020312 ps
T83 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1733161199 Dec 20 12:24:15 PM PST 23 Dec 20 12:24:52 PM PST 23 59344317 ps
T170 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.696713903 Dec 20 12:25:02 PM PST 23 Dec 20 12:25:25 PM PST 23 13874658 ps
T84 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.143886142 Dec 20 12:25:07 PM PST 23 Dec 20 12:25:32 PM PST 23 789610769 ps
T92 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3552669190 Dec 20 12:24:06 PM PST 23 Dec 20 12:24:45 PM PST 23 30056712 ps
T93 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2762834971 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:02 PM PST 23 19506456 ps
T118 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3370744741 Dec 20 12:25:13 PM PST 23 Dec 20 12:25:32 PM PST 23 403067720 ps
T107 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1203055515 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:59 PM PST 23 109711415 ps
T171 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1335312838 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:26 PM PST 23 135446148 ps
T172 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3126459963 Dec 20 12:24:12 PM PST 23 Dec 20 12:24:50 PM PST 23 25409529 ps
T85 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2706939857 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:59 PM PST 23 396252121 ps
T173 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.31790909 Dec 20 12:25:35 PM PST 23 Dec 20 12:26:06 PM PST 23 105699021 ps
T174 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.335094954 Dec 20 12:24:04 PM PST 23 Dec 20 12:24:47 PM PST 23 509054558 ps
T175 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3338085891 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:52 PM PST 23 28908755 ps
T176 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.756953250 Dec 20 12:25:18 PM PST 23 Dec 20 12:25:41 PM PST 23 16874581 ps
T177 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2099850965 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:53 PM PST 23 28688389 ps
T113 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3317496132 Dec 20 12:24:32 PM PST 23 Dec 20 12:25:05 PM PST 23 147313303 ps
T178 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2923998622 Dec 20 12:24:15 PM PST 23 Dec 20 12:24:52 PM PST 23 33326678 ps
T179 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2264853204 Dec 20 12:24:05 PM PST 23 Dec 20 12:24:44 PM PST 23 20236414 ps
T115 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4103302842 Dec 20 12:24:22 PM PST 23 Dec 20 12:24:57 PM PST 23 188952492 ps
T180 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1063053132 Dec 20 12:24:05 PM PST 23 Dec 20 12:24:44 PM PST 23 12582678 ps
T86 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1769701249 Dec 20 12:25:27 PM PST 23 Dec 20 12:25:53 PM PST 23 49976175 ps
T181 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1572538705 Dec 20 12:25:28 PM PST 23 Dec 20 12:25:55 PM PST 23 33701521 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2873867090 Dec 20 12:24:22 PM PST 23 Dec 20 12:24:56 PM PST 23 21307985 ps
T182 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1997585948 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:35 PM PST 23 230459260 ps
T183 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2203013687 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:03 PM PST 23 16416157 ps
T184 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1888578638 Dec 20 12:24:08 PM PST 23 Dec 20 12:24:47 PM PST 23 14550197 ps
T185 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2518288593 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 11729208 ps
T186 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4275038454 Dec 20 12:24:22 PM PST 23 Dec 20 12:24:56 PM PST 23 13912710 ps
T109 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2234412100 Dec 20 12:25:22 PM PST 23 Dec 20 12:25:47 PM PST 23 801794026 ps
T187 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4227561052 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:52 PM PST 23 18420167 ps
T188 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2833392682 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:19 PM PST 23 34720503 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3375504488 Dec 20 12:24:00 PM PST 23 Dec 20 12:24:45 PM PST 23 849704523 ps
T189 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1626709471 Dec 20 12:24:10 PM PST 23 Dec 20 12:24:50 PM PST 23 104194576 ps
T190 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2973883291 Dec 20 12:24:47 PM PST 23 Dec 20 12:25:19 PM PST 23 19359955 ps
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T112 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1939331551 Dec 20 12:25:12 PM PST 23 Dec 20 12:25:33 PM PST 23 496923311 ps
T191 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3576135926 Dec 20 12:24:26 PM PST 23 Dec 20 12:25:01 PM PST 23 261982513 ps
T192 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1777426893 Dec 20 12:24:18 PM PST 23 Dec 20 12:24:55 PM PST 23 104511820 ps
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T194 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3792280545 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:18 PM PST 23 149979452 ps
T195 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2620115827 Dec 20 12:25:26 PM PST 23 Dec 20 12:25:53 PM PST 23 14023135 ps
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T196 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1189764839 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:53 PM PST 23 94363839 ps
T197 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3250830384 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:07 PM PST 23 151342669 ps
T114 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.411436689 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:53 PM PST 23 1316737591 ps
T116 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3831731534 Dec 20 12:24:42 PM PST 23 Dec 20 12:25:15 PM PST 23 95897683 ps
T198 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.428219443 Dec 20 12:25:13 PM PST 23 Dec 20 12:25:34 PM PST 23 283483380 ps
T199 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3368182346 Dec 20 12:25:16 PM PST 23 Dec 20 12:25:36 PM PST 23 40622328 ps
T200 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1360710448 Dec 20 12:24:38 PM PST 23 Dec 20 12:25:12 PM PST 23 59657878 ps
T201 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2121664997 Dec 20 12:24:43 PM PST 23 Dec 20 12:25:18 PM PST 23 1757306890 ps
T202 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2850593942 Dec 20 12:24:01 PM PST 23 Dec 20 12:24:42 PM PST 23 120313332 ps
T203 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3151522893 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:03 PM PST 23 45517245 ps
T204 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1742743466 Dec 20 12:24:23 PM PST 23 Dec 20 12:24:59 PM PST 23 292438901 ps
T205 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2723819927 Dec 20 12:25:00 PM PST 23 Dec 20 12:25:29 PM PST 23 236206888 ps
T206 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.637049155 Dec 20 12:24:33 PM PST 23 Dec 20 12:25:05 PM PST 23 13643797 ps
T207 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.976896020 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 25206058 ps
T96 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.996612064 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:56 PM PST 23 405202238 ps
T208 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1091631278 Dec 20 12:24:12 PM PST 23 Dec 20 12:24:49 PM PST 23 161727715 ps
T97 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2008318548 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:24 PM PST 23 211665422 ps
T209 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4238720383 Dec 20 12:25:34 PM PST 23 Dec 20 12:26:19 PM PST 23 2502748442 ps
T210 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1671978962 Dec 20 12:24:06 PM PST 23 Dec 20 12:24:45 PM PST 23 216451128 ps
T98 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3681546538 Dec 20 12:24:55 PM PST 23 Dec 20 12:25:28 PM PST 23 402899691 ps
T211 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2589652400 Dec 20 12:25:20 PM PST 23 Dec 20 12:25:45 PM PST 23 877225438 ps
T212 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2844946381 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:07 PM PST 23 49085779 ps
T213 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4254635619 Dec 20 12:24:45 PM PST 23 Dec 20 12:25:18 PM PST 23 14401778 ps
T214 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2836262982 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:43 PM PST 23 1608454016 ps
T215 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1169578040 Dec 20 12:24:13 PM PST 23 Dec 20 12:24:50 PM PST 23 10789710 ps
T216 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3195125774 Dec 20 12:25:34 PM PST 23 Dec 20 12:26:05 PM PST 23 62306552 ps
T217 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3697656609 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 64833912 ps
T110 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4047057368 Dec 20 12:24:39 PM PST 23 Dec 20 12:25:15 PM PST 23 270519622 ps
T218 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1111497659 Dec 20 12:24:42 PM PST 23 Dec 20 12:25:17 PM PST 23 258809388 ps
T219 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2432420267 Dec 20 12:24:21 PM PST 23 Dec 20 12:24:55 PM PST 23 42471233 ps
T220 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3796313990 Dec 20 12:24:36 PM PST 23 Dec 20 12:25:13 PM PST 23 435812358 ps
T221 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1642895032 Dec 20 12:25:52 PM PST 23 Dec 20 12:26:19 PM PST 23 33217173 ps
T111 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3631839616 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:53 PM PST 23 1079033416 ps
T222 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2762797685 Dec 20 12:24:13 PM PST 23 Dec 20 12:24:54 PM PST 23 40309751 ps
T223 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.711317031 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 64314429 ps
T224 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4024618446 Dec 20 12:27:32 PM PST 23 Dec 20 12:28:09 PM PST 23 35972174 ps
T225 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2265159721 Dec 20 12:24:19 PM PST 23 Dec 20 12:24:54 PM PST 23 49187742 ps
T226 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3365240948 Dec 20 12:25:18 PM PST 23 Dec 20 12:25:39 PM PST 23 32088592 ps
T119 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.426821753 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:01 PM PST 23 1226528718 ps
T227 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2965814893 Dec 20 12:24:36 PM PST 23 Dec 20 12:25:13 PM PST 23 426791374 ps
T228 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3274844310 Dec 20 12:24:57 PM PST 23 Dec 20 12:25:25 PM PST 23 125278688 ps
T229 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.681578342 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:58 PM PST 23 1583402014 ps
T230 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1911259871 Dec 20 12:24:24 PM PST 23 Dec 20 12:25:02 PM PST 23 1214340248 ps
T231 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.340882422 Dec 20 12:25:16 PM PST 23 Dec 20 12:25:36 PM PST 23 59445734 ps
T232 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3676096953 Dec 20 12:24:15 PM PST 23 Dec 20 12:24:53 PM PST 23 217285707 ps
T233 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.454490218 Dec 20 12:24:21 PM PST 23 Dec 20 12:25:06 PM PST 23 461973980 ps
T234 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.835516215 Dec 20 12:24:10 PM PST 23 Dec 20 12:24:48 PM PST 23 43615917 ps
T235 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.250746878 Dec 20 12:24:53 PM PST 23 Dec 20 12:25:23 PM PST 23 32933859 ps
T236 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1093485361 Dec 20 12:24:14 PM PST 23 Dec 20 12:24:51 PM PST 23 18078704 ps
T237 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.353527323 Dec 20 12:24:07 PM PST 23 Dec 20 12:24:45 PM PST 23 21680378 ps
T238 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2351515888 Dec 20 12:23:55 PM PST 23 Dec 20 12:24:37 PM PST 23 59632190 ps
T239 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3628232554 Dec 20 12:23:56 PM PST 23 Dec 20 12:24:37 PM PST 23 45332867 ps
T240 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1889514202 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:59 PM PST 23 168455764 ps
T117 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.868093873 Dec 20 12:25:43 PM PST 23 Dec 20 12:26:15 PM PST 23 372829183 ps
T241 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.252822174 Dec 20 12:26:05 PM PST 23 Dec 20 12:26:31 PM PST 23 143387938 ps
T242 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2601918936 Dec 20 12:24:10 PM PST 23 Dec 20 12:24:49 PM PST 23 55668106 ps
T243 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1109668316 Dec 20 12:24:10 PM PST 23 Dec 20 12:24:50 PM PST 23 435296806 ps
T244 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1624902036 Dec 20 12:26:10 PM PST 23 Dec 20 12:26:44 PM PST 23 330469480 ps
T245 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3402752384 Dec 20 12:24:29 PM PST 23 Dec 20 12:25:04 PM PST 23 59725479 ps
T246 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3656755946 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:51 PM PST 23 321094765 ps
T247 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.70288961 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:53 PM PST 23 24238768 ps
T248 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2693029427 Dec 20 12:26:04 PM PST 23 Dec 20 12:26:31 PM PST 23 84253626 ps
T131 /workspace/coverage/default/38.sram_ctrl_executable.3168663478 Dec 20 01:01:11 PM PST 23 Dec 20 01:10:46 PM PST 23 12476923957 ps
T249 /workspace/coverage/default/34.sram_ctrl_smoke.4134630892 Dec 20 01:00:39 PM PST 23 Dec 20 01:01:56 PM PST 23 118863180 ps
T250 /workspace/coverage/default/20.sram_ctrl_partial_access.3984228685 Dec 20 12:59:09 PM PST 23 Dec 20 12:59:30 PM PST 23 247450921 ps
T24 /workspace/coverage/default/3.sram_ctrl_sec_cm.288481998 Dec 20 12:58:05 PM PST 23 Dec 20 12:58:23 PM PST 23 658752921 ps
T27 /workspace/coverage/default/8.sram_ctrl_stress_all.93937236 Dec 20 12:58:15 PM PST 23 Dec 20 01:51:52 PM PST 23 182920648642 ps
T28 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.943376788 Dec 20 01:01:01 PM PST 23 Dec 20 01:37:36 PM PST 23 1802067011 ps
T36 /workspace/coverage/default/35.sram_ctrl_mem_walk.3057108353 Dec 20 01:01:01 PM PST 23 Dec 20 01:01:50 PM PST 23 1330920901 ps
T37 /workspace/coverage/default/48.sram_ctrl_executable.1722435814 Dec 20 01:02:29 PM PST 23 Dec 20 01:20:32 PM PST 23 62347362323 ps
T38 /workspace/coverage/default/25.sram_ctrl_mem_walk.3749316585 Dec 20 01:00:06 PM PST 23 Dec 20 01:00:27 PM PST 23 262916698 ps
T39 /workspace/coverage/default/18.sram_ctrl_alert_test.685501880 Dec 20 12:59:10 PM PST 23 Dec 20 12:59:26 PM PST 23 32494866 ps
T40 /workspace/coverage/default/39.sram_ctrl_bijection.1184419351 Dec 20 01:01:23 PM PST 23 Dec 20 01:03:23 PM PST 23 6143906821 ps
T251 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3123810496 Dec 20 12:58:46 PM PST 23 Dec 20 01:00:10 PM PST 23 147816078 ps
T252 /workspace/coverage/default/10.sram_ctrl_partial_access.2793920609 Dec 20 12:58:09 PM PST 23 Dec 20 12:58:56 PM PST 23 481326704 ps
T253 /workspace/coverage/default/2.sram_ctrl_partial_access.2739487593 Dec 20 12:58:14 PM PST 23 Dec 20 12:58:36 PM PST 23 659043489 ps
T254 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2750492388 Dec 20 01:00:46 PM PST 23 Dec 20 01:01:11 PM PST 23 85037162 ps
T255 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1555291209 Dec 20 12:58:21 PM PST 23 Dec 20 01:37:20 PM PST 23 1217148131 ps
T256 /workspace/coverage/default/27.sram_ctrl_max_throughput.2611064763 Dec 20 01:00:25 PM PST 23 Dec 20 01:01:04 PM PST 23 758785262 ps
T257 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.527572408 Dec 20 01:01:34 PM PST 23 Dec 20 01:16:56 PM PST 23 13334548766 ps
T258 /workspace/coverage/default/19.sram_ctrl_alert_test.3818777316 Dec 20 12:59:12 PM PST 23 Dec 20 12:59:27 PM PST 23 71115733 ps
T259 /workspace/coverage/default/12.sram_ctrl_partial_access.2969946109 Dec 20 12:58:22 PM PST 23 Dec 20 01:00:19 PM PST 23 2082766471 ps
T260 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3160403863 Dec 20 01:00:09 PM PST 23 Dec 20 01:07:00 PM PST 23 18762290438 ps
T261 /workspace/coverage/default/25.sram_ctrl_lc_escalation.2314987007 Dec 20 12:59:46 PM PST 23 Dec 20 01:00:13 PM PST 23 1717530247 ps
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