Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43867586	1			T1	6142		T2	5163		T3	68105
triple_byte_access	2685374	1			T3	61059		T4	627		T5	26
halfword_access	4032193	1			T3	92104		T4	946		T5	29
byte_access	5381711	1			T3	122010		T4	1292		T5	43
zero_access	1356856	1			T3	30663		T4	319		T5	14

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28604859

1

T1

2048

T2

2579

T3

187194

auto[1]

28718861

1

T1

4094

T2

2584

T3

186747

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21882366	1			T1	2048		T2	2579		T3	34223
auto[0]	triple_byte_access	1338407	1			T3	30417		T4	321		T5	16
auto[0]	halfword_access	2012454	1			T3	46081		T4	473		T5	11
auto[0]	byte_access	2688782	1			T3	61213		T4	647		T5	25
auto[0]	zero_access	682850	1			T3	15260		T4	165		T5	7
auto[1]	word_access	21985220	1			T1	4094		T2	2584		T3	33882
auto[1]	triple_byte_access	1346967	1			T3	30642		T4	306		T5	10
auto[1]	halfword_access	2019739	1			T3	46023		T4	473		T5	18
auto[1]	byte_access	2692929	1			T3	60797		T4	645		T5	18
auto[1]	zero_access	674006	1			T3	15403		T4	154		T5	7