Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147468111	1			T3	147260		T4	162530		T5	545658
instr_valid_dis	113782853	1			T3	770172		T4	162530		T5	545658
instr_en	22451129	1			T3	451682		T15	69578		T16	221364

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10212419	1			T3	93282		T15	87084		T16	67822
sram_ifetch_valid_disable	114451506	1			T3	914600		T4	162530		T5	545658
sram_ifetch_enable	22804186	1			T3	464720		T15	79162		T16	76404

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147468111	1			T3	147260		T4	162530		T5	545658
hw_debug_en_valid_off	113598846	1			T3	833668		T4	162530		T5	545658
hw_debug_en_on	22806185	1			T3	494014		T15	101726		T16	76404

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114451506	1			T3	914600		T4	162530		T5	545658
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101552670	1			T3	570874		T4	162530		T5	545658
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8498258	1			T3	174350		T15	14382		T16	77138
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4109979	1			T3	37826		T15	30650		T120	13900
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1816750	1			T15	1796		T120	13900		T61	69472
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1407146	1			T3	35752		T15	28854		T25	56958
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3607506	1			T3	33758		T15	30132		T120	52610
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1387264	1			T15	30132		T26	18014		T62	2954
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1424591	1			T3	14082		T120	41082		T25	4492
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8915086	1			T3	205170		T15	66420		T120	34996
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3366281	1			T3	19060		T15	66188		T120	34996
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3852546	1			T3	116376		T15	232		T25	19168

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10006243	1			T3	214896		T15	26342		T16	76404
lc_exec_en	10283593	1			T3	255086		T15	5174		T16	76404
valid_exec_dis	109313779	1			T3	807246		T4	162530		T5	545658
invalid_exec_dis	33016605	1			T3	558002		T15	166246		T16	144226