Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total tests in report: 1029
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 97.91 97.91 80.38 80.38 85.04 85.04 100.00 100.00 93.51 93.51 94.90 94.90 67.17 67.17 /workspace/coverage/default/18.sram_ctrl_lc_escalation.3877230498
93.34 4.92 99.15 1.23 89.61 9.24 96.13 11.10 100.00 0.00 96.46 2.95 94.90 0.00 77.11 9.94 /workspace/coverage/default/15.sram_ctrl_stress_all.3347731329
96.17 2.84 99.53 0.38 94.23 4.62 96.56 0.43 100.00 0.00 97.64 1.18 96.70 1.80 88.56 11.44 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3827657942
97.23 1.06 99.72 0.19 95.09 0.87 97.14 0.57 100.00 0.00 98.53 0.88 96.70 0.00 93.43 4.88 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1973596856
97.92 0.70 99.91 0.19 97.26 2.16 97.49 0.36 100.00 0.00 99.71 1.18 97.30 0.60 93.81 0.38 /workspace/coverage/default/2.sram_ctrl_sec_cm.2304564368
98.27 0.34 99.91 0.00 97.26 0.00 97.49 0.00 100.00 0.00 99.71 0.00 97.45 0.15 96.06 2.25 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1326008427
98.58 0.31 99.91 0.00 97.26 0.00 99.28 1.79 100.00 0.00 99.71 0.00 97.45 0.00 96.44 0.38 /workspace/coverage/default/20.sram_ctrl_multiple_keys.3304468129
98.77 0.19 99.91 0.00 97.26 0.00 99.28 0.00 100.00 0.00 99.71 0.00 98.80 1.35 96.44 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.621209526
98.94 0.17 99.91 0.00 97.55 0.29 99.28 0.00 100.00 0.00 99.71 0.00 99.70 0.90 96.44 0.00 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3703058557
99.10 0.16 99.91 0.00 97.55 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.70 0.00 97.56 1.13 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3693381155
99.26 0.16 99.91 0.00 97.55 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.70 0.00 98.69 1.13 /workspace/coverage/default/49.sram_ctrl_stress_all.2013726144
99.38 0.12 100.00 0.09 97.55 0.00 100.00 0.72 100.00 0.00 99.71 0.00 99.70 0.00 98.69 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1559839033
99.48 0.11 100.00 0.00 97.55 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.44 0.75 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2307405209
99.53 0.05 100.00 0.00 97.69 0.14 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.62 0.19 /workspace/coverage/default/2.sram_ctrl_stress_all.3249381872
99.57 0.04 100.00 0.00 97.98 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.62 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.909400690
99.60 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.81 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1084618898
99.63 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 100.00 0.19 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.838259504

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4050198624
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4007235579
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342363909
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2505525573
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2661607395
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3977726456
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2849997666
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3902161499
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.870912768
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2374725580
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3636304731
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.656079532
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1049559636
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2697339950
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1431968491
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.112379345
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3554058035
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1032002929
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4270093599
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3855639383
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3555716740
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1362213540
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.658232560
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4098905315
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1096285673
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.607131666
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.435943048
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.70773584
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3198195208
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3705230816
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2281932335
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.81792611
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2893628200
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2096562733
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1266661343
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.598238915
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2890380132
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1880112551
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2439186078
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1203932152
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.177027208
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3771793648
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.874716019
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4291156823
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3332129117
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3708011872
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.633051866
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2194469497
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4182489861
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.291737391
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.591400349
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1821381266
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.713558044
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2610709881
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1546002766
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1069605576
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2223631721
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.502204
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2434219654
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2132430553
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3503289552
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2888329081
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1139543278
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.72304167
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3603879660
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2142622437
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1739898379
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1876105982
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3365182937
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4240295269
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3489721562
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3791446267
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3074426997
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1089526852
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1421156525
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.77681292
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1096343486
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3465005
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4157508339
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.112062435
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2195326560
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4049767996
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3419429238
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.645268614
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.365909852
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.997844039
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1940924361
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1279453237
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.865214650
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2809136158
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.645666084
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.952683518
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.906185428
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3063948616
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4133927703
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3174724593
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4242329390
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3039900190
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1943769654
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2381721877
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4179624844
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3627285419
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3430795378
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2165630135
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2807490891
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3570705769
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2876095590
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3885073589
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.104690453
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.266399782
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3638449577
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3687307436
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2399493865
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3374024187
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3849180449
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2379556785
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.395340794
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2604815515
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2626626395
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2247409301
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3608274564
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3534980451
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.489207592
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3100008096
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1875269662
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.576729590
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1964241361
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2444446538
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2624491391
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1410691536
/workspace/coverage/default/0.sram_ctrl_bijection.2205864825
/workspace/coverage/default/0.sram_ctrl_executable.3301536619
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2838243398
/workspace/coverage/default/0.sram_ctrl_max_throughput.856696325
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1394880700
/workspace/coverage/default/0.sram_ctrl_mem_walk.451431744
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3152340749
/workspace/coverage/default/0.sram_ctrl_partial_access.3285113462
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.23763551
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2695834017
/workspace/coverage/default/0.sram_ctrl_regwen.2970029268
/workspace/coverage/default/0.sram_ctrl_sec_cm.48146389
/workspace/coverage/default/0.sram_ctrl_smoke.2593249272
/workspace/coverage/default/0.sram_ctrl_stress_all.4266616186
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3196598115
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1367036179
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1984821175
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4232885999
/workspace/coverage/default/1.sram_ctrl_alert_test.1997624111
/workspace/coverage/default/1.sram_ctrl_bijection.2633785365
/workspace/coverage/default/1.sram_ctrl_executable.3632000352
/workspace/coverage/default/1.sram_ctrl_max_throughput.2600475075
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3151345697
/workspace/coverage/default/1.sram_ctrl_mem_walk.3410902350
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3803426762
/workspace/coverage/default/1.sram_ctrl_partial_access.1136835519
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3096423551
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3694381203
/workspace/coverage/default/1.sram_ctrl_regwen.2948504260
/workspace/coverage/default/1.sram_ctrl_sec_cm.1451852440
/workspace/coverage/default/1.sram_ctrl_smoke.2415025888
/workspace/coverage/default/1.sram_ctrl_stress_all.3758233782
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2738632958
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1741723633
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1932428555
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3477319898
/workspace/coverage/default/10.sram_ctrl_alert_test.3709077259
/workspace/coverage/default/10.sram_ctrl_bijection.3691290169
/workspace/coverage/default/10.sram_ctrl_executable.3175843387
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3439988678
/workspace/coverage/default/10.sram_ctrl_max_throughput.2588738072
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1071491085
/workspace/coverage/default/10.sram_ctrl_mem_walk.1891582700
/workspace/coverage/default/10.sram_ctrl_partial_access.3645433169
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4186268026
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2159222508
/workspace/coverage/default/10.sram_ctrl_regwen.319990738
/workspace/coverage/default/10.sram_ctrl_smoke.1545785301
/workspace/coverage/default/10.sram_ctrl_stress_all.2268013677
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1254257241
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1050914481
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2838915664
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1981438634
/workspace/coverage/default/11.sram_ctrl_alert_test.321217052
/workspace/coverage/default/11.sram_ctrl_bijection.2725095673
/workspace/coverage/default/11.sram_ctrl_executable.3059835548
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1129657456
/workspace/coverage/default/11.sram_ctrl_max_throughput.2963373552
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2853489255
/workspace/coverage/default/11.sram_ctrl_mem_walk.2405284270
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3408356059
/workspace/coverage/default/11.sram_ctrl_partial_access.3566629728
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2901378493
/workspace/coverage/default/11.sram_ctrl_regwen.3195225190
/workspace/coverage/default/11.sram_ctrl_smoke.1001791021
/workspace/coverage/default/11.sram_ctrl_stress_all.1123203841
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2676207010
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1700806915
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3015740698
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2170606121
/workspace/coverage/default/12.sram_ctrl_alert_test.3997368259
/workspace/coverage/default/12.sram_ctrl_bijection.1368622089
/workspace/coverage/default/12.sram_ctrl_executable.2908291388
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2470547654
/workspace/coverage/default/12.sram_ctrl_max_throughput.2411193452
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2208315036
/workspace/coverage/default/12.sram_ctrl_mem_walk.3088194624
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2783372770
/workspace/coverage/default/12.sram_ctrl_partial_access.1194293373
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2320931265
/workspace/coverage/default/12.sram_ctrl_ram_cfg.567328555
/workspace/coverage/default/12.sram_ctrl_regwen.2782146013
/workspace/coverage/default/12.sram_ctrl_smoke.4085867504
/workspace/coverage/default/12.sram_ctrl_stress_all.2254792684
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2163472101
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.955296847
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3422041887
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3878371624
/workspace/coverage/default/13.sram_ctrl_alert_test.958584937
/workspace/coverage/default/13.sram_ctrl_bijection.737822260
/workspace/coverage/default/13.sram_ctrl_executable.2922755092
/workspace/coverage/default/13.sram_ctrl_lc_escalation.555896359
/workspace/coverage/default/13.sram_ctrl_max_throughput.3067019142
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2269891670
/workspace/coverage/default/13.sram_ctrl_mem_walk.509274711
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2250784867
/workspace/coverage/default/13.sram_ctrl_partial_access.4116278699
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3291372940
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3033845653
/workspace/coverage/default/13.sram_ctrl_regwen.451308439
/workspace/coverage/default/13.sram_ctrl_smoke.4102269655
/workspace/coverage/default/13.sram_ctrl_stress_all.237044969
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1111879894
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.711399727
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3933504624
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.487291499
/workspace/coverage/default/14.sram_ctrl_alert_test.392845028
/workspace/coverage/default/14.sram_ctrl_bijection.2626579914
/workspace/coverage/default/14.sram_ctrl_executable.2698174349
/workspace/coverage/default/14.sram_ctrl_max_throughput.2461013050
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2517190458
/workspace/coverage/default/14.sram_ctrl_mem_walk.1320889589
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1320243627
/workspace/coverage/default/14.sram_ctrl_partial_access.1029128787
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2911623990
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3491772135
/workspace/coverage/default/14.sram_ctrl_regwen.3820866992
/workspace/coverage/default/14.sram_ctrl_smoke.3060084752
/workspace/coverage/default/14.sram_ctrl_stress_all.1921197672
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1537994069
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.418217331
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.782796944
/workspace/coverage/default/15.sram_ctrl_alert_test.98732340
/workspace/coverage/default/15.sram_ctrl_bijection.2427978722
/workspace/coverage/default/15.sram_ctrl_executable.593887468
/workspace/coverage/default/15.sram_ctrl_lc_escalation.224998146
/workspace/coverage/default/15.sram_ctrl_max_throughput.4293126595
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2475240788
/workspace/coverage/default/15.sram_ctrl_mem_walk.2116456446
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1911397941
/workspace/coverage/default/15.sram_ctrl_partial_access.2870276261
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1672713709
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2025723931
/workspace/coverage/default/15.sram_ctrl_regwen.3463357353
/workspace/coverage/default/15.sram_ctrl_smoke.3926567115
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.204663820
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4164106905
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3856196423
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2127655556
/workspace/coverage/default/16.sram_ctrl_alert_test.2046273712
/workspace/coverage/default/16.sram_ctrl_bijection.2254709228
/workspace/coverage/default/16.sram_ctrl_executable.3645270855
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1324892622
/workspace/coverage/default/16.sram_ctrl_max_throughput.2282154281
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2623552632
/workspace/coverage/default/16.sram_ctrl_mem_walk.750828327
/workspace/coverage/default/16.sram_ctrl_multiple_keys.232583596
/workspace/coverage/default/16.sram_ctrl_partial_access.2227459515
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1168570509
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1639941115
/workspace/coverage/default/16.sram_ctrl_regwen.2809130133
/workspace/coverage/default/16.sram_ctrl_smoke.3860022440
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3912074777
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2678328478
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3841920439
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.464668305
/workspace/coverage/default/17.sram_ctrl_alert_test.1248205715
/workspace/coverage/default/17.sram_ctrl_bijection.3567344716
/workspace/coverage/default/17.sram_ctrl_executable.1020429032
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3865008198
/workspace/coverage/default/17.sram_ctrl_max_throughput.1372662441
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2706692746
/workspace/coverage/default/17.sram_ctrl_mem_walk.221088875
/workspace/coverage/default/17.sram_ctrl_multiple_keys.427933909
/workspace/coverage/default/17.sram_ctrl_partial_access.3346322303
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4032006238
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2395225434
/workspace/coverage/default/17.sram_ctrl_regwen.3333043349
/workspace/coverage/default/17.sram_ctrl_smoke.1477598388
/workspace/coverage/default/17.sram_ctrl_stress_all.3077961231
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2817968166
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1574029017
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2392403297
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1274002353
/workspace/coverage/default/18.sram_ctrl_alert_test.1512211284
/workspace/coverage/default/18.sram_ctrl_bijection.4266232182
/workspace/coverage/default/18.sram_ctrl_executable.1172475958
/workspace/coverage/default/18.sram_ctrl_max_throughput.931862381
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1427188504
/workspace/coverage/default/18.sram_ctrl_mem_walk.941373473
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2674838588
/workspace/coverage/default/18.sram_ctrl_partial_access.4239432664
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2391677434
/workspace/coverage/default/18.sram_ctrl_regwen.4116708376
/workspace/coverage/default/18.sram_ctrl_smoke.719989351
/workspace/coverage/default/18.sram_ctrl_stress_all.66541511
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2973859937
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1987574088
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.582540604
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1405814594
/workspace/coverage/default/19.sram_ctrl_alert_test.2699490057
/workspace/coverage/default/19.sram_ctrl_bijection.3791778625
/workspace/coverage/default/19.sram_ctrl_executable.3147144526
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1795065898
/workspace/coverage/default/19.sram_ctrl_max_throughput.411313592
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2894336436
/workspace/coverage/default/19.sram_ctrl_mem_walk.218533890
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3289507926
/workspace/coverage/default/19.sram_ctrl_partial_access.607669328
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1373357149
/workspace/coverage/default/19.sram_ctrl_ram_cfg.4122338305
/workspace/coverage/default/19.sram_ctrl_regwen.975740648
/workspace/coverage/default/19.sram_ctrl_smoke.3062862276
/workspace/coverage/default/19.sram_ctrl_stress_all.3230507402
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1582334118
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2421154749
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.4240637458
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2801334238
/workspace/coverage/default/2.sram_ctrl_alert_test.2161696786
/workspace/coverage/default/2.sram_ctrl_bijection.3370755263
/workspace/coverage/default/2.sram_ctrl_executable.4024118908
/workspace/coverage/default/2.sram_ctrl_lc_escalation.4192454154
/workspace/coverage/default/2.sram_ctrl_max_throughput.3854029908
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3878237630
/workspace/coverage/default/2.sram_ctrl_mem_walk.2324542346
/workspace/coverage/default/2.sram_ctrl_multiple_keys.302363013
/workspace/coverage/default/2.sram_ctrl_partial_access.2818343028
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2001026440
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2997517576
/workspace/coverage/default/2.sram_ctrl_regwen.2199526689
/workspace/coverage/default/2.sram_ctrl_smoke.1540854049
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.458690978
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3504495175
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.304441760
/workspace/coverage/default/20.sram_ctrl_alert_test.3623150198
/workspace/coverage/default/20.sram_ctrl_bijection.2109000847
/workspace/coverage/default/20.sram_ctrl_executable.242591165
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1571262447
/workspace/coverage/default/20.sram_ctrl_max_throughput.2614566709
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3595101618
/workspace/coverage/default/20.sram_ctrl_mem_walk.3294613904
/workspace/coverage/default/20.sram_ctrl_partial_access.1127101046
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3439263511
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1783582395
/workspace/coverage/default/20.sram_ctrl_regwen.2528648755
/workspace/coverage/default/20.sram_ctrl_smoke.2311359751
/workspace/coverage/default/20.sram_ctrl_stress_all.2685486880
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1793401219
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.581540873
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1020399665
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2557377444
/workspace/coverage/default/21.sram_ctrl_alert_test.241755909
/workspace/coverage/default/21.sram_ctrl_bijection.3414437108
/workspace/coverage/default/21.sram_ctrl_executable.2837359418
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3005100459
/workspace/coverage/default/21.sram_ctrl_max_throughput.324905237
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2559706663
/workspace/coverage/default/21.sram_ctrl_mem_walk.123765916
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2253994752
/workspace/coverage/default/21.sram_ctrl_partial_access.3721237034
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.622043854
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2327616370
/workspace/coverage/default/21.sram_ctrl_regwen.81864568
/workspace/coverage/default/21.sram_ctrl_smoke.2575148792
/workspace/coverage/default/21.sram_ctrl_stress_all.2181370197
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2859217931
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3775066520
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2022964693
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3265577240
/workspace/coverage/default/22.sram_ctrl_alert_test.3570047713
/workspace/coverage/default/22.sram_ctrl_bijection.714655498
/workspace/coverage/default/22.sram_ctrl_executable.2459545032
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2522317319
/workspace/coverage/default/22.sram_ctrl_max_throughput.3329952603
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3946741062
/workspace/coverage/default/22.sram_ctrl_mem_walk.641225966
/workspace/coverage/default/22.sram_ctrl_multiple_keys.4139789287
/workspace/coverage/default/22.sram_ctrl_partial_access.1632527633
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1673324758
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1212513787
/workspace/coverage/default/22.sram_ctrl_regwen.2781732433
/workspace/coverage/default/22.sram_ctrl_smoke.2443123655
/workspace/coverage/default/22.sram_ctrl_stress_all.4055233580
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3296179013
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3013134654
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2590075501
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.876526479
/workspace/coverage/default/23.sram_ctrl_alert_test.4274837890
/workspace/coverage/default/23.sram_ctrl_bijection.718871242
/workspace/coverage/default/23.sram_ctrl_executable.3977809926
/workspace/coverage/default/23.sram_ctrl_lc_escalation.671235674
/workspace/coverage/default/23.sram_ctrl_max_throughput.2404862858
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3805249913
/workspace/coverage/default/23.sram_ctrl_mem_walk.4026778748
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1778189417
/workspace/coverage/default/23.sram_ctrl_partial_access.274080068
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.140123017
/workspace/coverage/default/23.sram_ctrl_ram_cfg.616156114
/workspace/coverage/default/23.sram_ctrl_regwen.2068270038
/workspace/coverage/default/23.sram_ctrl_smoke.3255808543
/workspace/coverage/default/23.sram_ctrl_stress_all.1968864983
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2959961988
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2383796795
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.294350114
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3978672893
/workspace/coverage/default/24.sram_ctrl_alert_test.532769424
/workspace/coverage/default/24.sram_ctrl_bijection.441471358
/workspace/coverage/default/24.sram_ctrl_executable.941880943
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3531551596
/workspace/coverage/default/24.sram_ctrl_max_throughput.3535015660
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1581505243
/workspace/coverage/default/24.sram_ctrl_mem_walk.1646512704
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2123583415
/workspace/coverage/default/24.sram_ctrl_partial_access.3219673844
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.489904217
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2563849917
/workspace/coverage/default/24.sram_ctrl_regwen.74540116
/workspace/coverage/default/24.sram_ctrl_smoke.1292750968
/workspace/coverage/default/24.sram_ctrl_stress_all.1178159752
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1990542267
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1765240661
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2566874679
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3221747687
/workspace/coverage/default/25.sram_ctrl_alert_test.1070644010
/workspace/coverage/default/25.sram_ctrl_bijection.126552237
/workspace/coverage/default/25.sram_ctrl_executable.3601909056
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2129545697
/workspace/coverage/default/25.sram_ctrl_max_throughput.4214123653
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1785058996
/workspace/coverage/default/25.sram_ctrl_mem_walk.265602170
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1133866278
/workspace/coverage/default/25.sram_ctrl_partial_access.1881952971
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.519179797
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3496588708
/workspace/coverage/default/25.sram_ctrl_regwen.702106274
/workspace/coverage/default/25.sram_ctrl_smoke.4099052502
/workspace/coverage/default/25.sram_ctrl_stress_all.1024202091
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1450127860
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1589438127
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2326988657
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3779952116
/workspace/coverage/default/26.sram_ctrl_alert_test.1355590753
/workspace/coverage/default/26.sram_ctrl_bijection.3279392012
/workspace/coverage/default/26.sram_ctrl_executable.1778146909
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3643017422
/workspace/coverage/default/26.sram_ctrl_max_throughput.944506229
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.87892711
/workspace/coverage/default/26.sram_ctrl_mem_walk.1038704015
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2810811402
/workspace/coverage/default/26.sram_ctrl_partial_access.3116132501
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3457738140
/workspace/coverage/default/26.sram_ctrl_ram_cfg.857928852
/workspace/coverage/default/26.sram_ctrl_regwen.6671834
/workspace/coverage/default/26.sram_ctrl_smoke.3326594558
/workspace/coverage/default/26.sram_ctrl_stress_all.1454556928
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2147408579
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.826562246
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3093886598
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1381209379
/workspace/coverage/default/27.sram_ctrl_alert_test.1355826544
/workspace/coverage/default/27.sram_ctrl_bijection.2444196494
/workspace/coverage/default/27.sram_ctrl_executable.3875583617
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1869973075
/workspace/coverage/default/27.sram_ctrl_max_throughput.3393571714
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2671686970
/workspace/coverage/default/27.sram_ctrl_mem_walk.2983567024
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4114505394
/workspace/coverage/default/27.sram_ctrl_partial_access.2684496139
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.201802215
/workspace/coverage/default/27.sram_ctrl_ram_cfg.148747948
/workspace/coverage/default/27.sram_ctrl_regwen.3184717466
/workspace/coverage/default/27.sram_ctrl_smoke.537455378
/workspace/coverage/default/27.sram_ctrl_stress_all.3954110780
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.165623783
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2291843586
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.619366245
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.4190126941
/workspace/coverage/default/28.sram_ctrl_alert_test.671214786
/workspace/coverage/default/28.sram_ctrl_bijection.1069922359
/workspace/coverage/default/28.sram_ctrl_executable.3431790956
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2782630139
/workspace/coverage/default/28.sram_ctrl_max_throughput.805017683
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4001205253
/workspace/coverage/default/28.sram_ctrl_mem_walk.3849814087
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2473634909
/workspace/coverage/default/28.sram_ctrl_partial_access.557572534
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2374662675
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2132071060
/workspace/coverage/default/28.sram_ctrl_regwen.4072454944
/workspace/coverage/default/28.sram_ctrl_smoke.2684533595
/workspace/coverage/default/28.sram_ctrl_stress_all.2439168896
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.562678752
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.892601185
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.640761874
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3626166333
/workspace/coverage/default/29.sram_ctrl_alert_test.4128866366
/workspace/coverage/default/29.sram_ctrl_bijection.930872678
/workspace/coverage/default/29.sram_ctrl_executable.1722265022
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3763511382
/workspace/coverage/default/29.sram_ctrl_max_throughput.1595180871
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.929972173
/workspace/coverage/default/29.sram_ctrl_mem_walk.986108472
/workspace/coverage/default/29.sram_ctrl_multiple_keys.733389733
/workspace/coverage/default/29.sram_ctrl_partial_access.2944669548
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.743690363
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3620400112
/workspace/coverage/default/29.sram_ctrl_regwen.938854161
/workspace/coverage/default/29.sram_ctrl_smoke.525048221
/workspace/coverage/default/29.sram_ctrl_stress_all.2498769079
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1601508361
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3111991120
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.858930582
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.499808833
/workspace/coverage/default/3.sram_ctrl_alert_test.1669011844
/workspace/coverage/default/3.sram_ctrl_bijection.3855280698
/workspace/coverage/default/3.sram_ctrl_executable.2111734620
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2664803053
/workspace/coverage/default/3.sram_ctrl_max_throughput.3217457581
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3105886575
/workspace/coverage/default/3.sram_ctrl_mem_walk.1219324287
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1822155436
/workspace/coverage/default/3.sram_ctrl_partial_access.1510262396
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1547096937
/workspace/coverage/default/3.sram_ctrl_ram_cfg.4190398722
/workspace/coverage/default/3.sram_ctrl_regwen.4134587691
/workspace/coverage/default/3.sram_ctrl_sec_cm.2033720048
/workspace/coverage/default/3.sram_ctrl_smoke.2530132590
/workspace/coverage/default/3.sram_ctrl_stress_all.161291059
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2145135561
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2958926138
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3279595447
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1086889518
/workspace/coverage/default/30.sram_ctrl_alert_test.688579022
/workspace/coverage/default/30.sram_ctrl_bijection.851347073
/workspace/coverage/default/30.sram_ctrl_executable.1903977217
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3273648231
/workspace/coverage/default/30.sram_ctrl_max_throughput.495369175
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2494595344
/workspace/coverage/default/30.sram_ctrl_mem_walk.188522669
/workspace/coverage/default/30.sram_ctrl_multiple_keys.4181467336
/workspace/coverage/default/30.sram_ctrl_partial_access.442047860
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2621329672
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3799457216
/workspace/coverage/default/30.sram_ctrl_regwen.2845774696
/workspace/coverage/default/30.sram_ctrl_smoke.2942870793
/workspace/coverage/default/30.sram_ctrl_stress_all.486345002
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.966046095
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1200404031
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.940720320
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1339780279
/workspace/coverage/default/31.sram_ctrl_alert_test.870208743
/workspace/coverage/default/31.sram_ctrl_bijection.3421520144
/workspace/coverage/default/31.sram_ctrl_executable.3345923142
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2289554470
/workspace/coverage/default/31.sram_ctrl_max_throughput.2924442117
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3646764038
/workspace/coverage/default/31.sram_ctrl_mem_walk.2404511032
/workspace/coverage/default/31.sram_ctrl_multiple_keys.4241476962
/workspace/coverage/default/31.sram_ctrl_partial_access.2535269736
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2849559086
/workspace/coverage/default/31.sram_ctrl_ram_cfg.783489356
/workspace/coverage/default/31.sram_ctrl_regwen.2073887732
/workspace/coverage/default/31.sram_ctrl_smoke.3482325011
/workspace/coverage/default/31.sram_ctrl_stress_all.4183251599
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3791897327
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2582563040
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2980045164
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3357328666
/workspace/coverage/default/32.sram_ctrl_alert_test.1303206520
/workspace/coverage/default/32.sram_ctrl_bijection.135433974
/workspace/coverage/default/32.sram_ctrl_executable.3191375293
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1014543140
/workspace/coverage/default/32.sram_ctrl_max_throughput.1437111168
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2091193816
/workspace/coverage/default/32.sram_ctrl_mem_walk.2998538777
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3037842970
/workspace/coverage/default/32.sram_ctrl_partial_access.1473183317
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2534553032
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2601771381
/workspace/coverage/default/32.sram_ctrl_regwen.964805166
/workspace/coverage/default/32.sram_ctrl_smoke.3200497063
/workspace/coverage/default/32.sram_ctrl_stress_all.3570377580
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.244066900
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2330693158
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3686509954
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.814101559
/workspace/coverage/default/33.sram_ctrl_alert_test.2600863905
/workspace/coverage/default/33.sram_ctrl_bijection.1828419753
/workspace/coverage/default/33.sram_ctrl_executable.674805260
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1390948989
/workspace/coverage/default/33.sram_ctrl_max_throughput.2429250686
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3368034239
/workspace/coverage/default/33.sram_ctrl_mem_walk.3106551737
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1570190690
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2102502840
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2089345075
/workspace/coverage/default/33.sram_ctrl_regwen.343603265
/workspace/coverage/default/33.sram_ctrl_smoke.752234294
/workspace/coverage/default/33.sram_ctrl_stress_all.3216512151
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3461369303
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3335195028
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1296052297
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1273948160
/workspace/coverage/default/34.sram_ctrl_alert_test.2265534063
/workspace/coverage/default/34.sram_ctrl_bijection.3925264963
/workspace/coverage/default/34.sram_ctrl_executable.2070060275
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1933271757
/workspace/coverage/default/34.sram_ctrl_max_throughput.2730569379
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3424231298
/workspace/coverage/default/34.sram_ctrl_mem_walk.1367849977
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3704384152
/workspace/coverage/default/34.sram_ctrl_partial_access.2427316381
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.833460744
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3258954383
/workspace/coverage/default/34.sram_ctrl_regwen.4024127179
/workspace/coverage/default/34.sram_ctrl_smoke.1816796454
/workspace/coverage/default/34.sram_ctrl_stress_all.1565265678
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.4285675589
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3983627338
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2846016757
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1775768307
/workspace/coverage/default/35.sram_ctrl_alert_test.253921050
/workspace/coverage/default/35.sram_ctrl_bijection.151620216
/workspace/coverage/default/35.sram_ctrl_executable.1625230654
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3951663092
/workspace/coverage/default/35.sram_ctrl_max_throughput.20539977
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2486762897
/workspace/coverage/default/35.sram_ctrl_mem_walk.2947687357
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3129086051
/workspace/coverage/default/35.sram_ctrl_partial_access.3646420072
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.971413760
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1712310075
/workspace/coverage/default/35.sram_ctrl_regwen.3259759878
/workspace/coverage/default/35.sram_ctrl_smoke.4233033802
/workspace/coverage/default/35.sram_ctrl_stress_all.1218909597
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.832788649
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1612726471
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.963719217
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3891284610
/workspace/coverage/default/36.sram_ctrl_alert_test.2179139028
/workspace/coverage/default/36.sram_ctrl_bijection.312282818
/workspace/coverage/default/36.sram_ctrl_executable.4229441275
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2295148510
/workspace/coverage/default/36.sram_ctrl_max_throughput.2285742284
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.905714924
/workspace/coverage/default/36.sram_ctrl_mem_walk.1799150973
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2389023007
/workspace/coverage/default/36.sram_ctrl_partial_access.3225343711
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1709539852
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3138755549
/workspace/coverage/default/36.sram_ctrl_regwen.3591028304
/workspace/coverage/default/36.sram_ctrl_smoke.2821901128
/workspace/coverage/default/36.sram_ctrl_stress_all.1913003967
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2499471120
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.803579631
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3019331110
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2812627812
/workspace/coverage/default/37.sram_ctrl_alert_test.562417875
/workspace/coverage/default/37.sram_ctrl_bijection.1653079589
/workspace/coverage/default/37.sram_ctrl_executable.4154244130
/workspace/coverage/default/37.sram_ctrl_max_throughput.350314683
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.525872993
/workspace/coverage/default/37.sram_ctrl_mem_walk.4005562960
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2190918552
/workspace/coverage/default/37.sram_ctrl_partial_access.654694048
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.85033769
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1108999925
/workspace/coverage/default/37.sram_ctrl_regwen.3259337840
/workspace/coverage/default/37.sram_ctrl_smoke.2635699503
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4038319510
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.693505090
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1002752834
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2570417953
/workspace/coverage/default/38.sram_ctrl_alert_test.3910529358
/workspace/coverage/default/38.sram_ctrl_bijection.3704970209
/workspace/coverage/default/38.sram_ctrl_executable.2853795824
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2367789036
/workspace/coverage/default/38.sram_ctrl_max_throughput.3610790855
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.606925627
/workspace/coverage/default/38.sram_ctrl_mem_walk.746837618
/workspace/coverage/default/38.sram_ctrl_multiple_keys.600165332
/workspace/coverage/default/38.sram_ctrl_partial_access.1153709453
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3348780831
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3197336797
/workspace/coverage/default/38.sram_ctrl_regwen.2184640606
/workspace/coverage/default/38.sram_ctrl_smoke.4051543386
/workspace/coverage/default/38.sram_ctrl_stress_all.1070607545
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.599921967
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3813219854
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2446921780
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2233935257
/workspace/coverage/default/39.sram_ctrl_alert_test.2584286799
/workspace/coverage/default/39.sram_ctrl_bijection.1471615522
/workspace/coverage/default/39.sram_ctrl_executable.1392286933
/workspace/coverage/default/39.sram_ctrl_lc_escalation.4026662740
/workspace/coverage/default/39.sram_ctrl_max_throughput.3284579715
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2605600182
/workspace/coverage/default/39.sram_ctrl_mem_walk.64294516
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1256871242
/workspace/coverage/default/39.sram_ctrl_partial_access.1302834433
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4233791850
/workspace/coverage/default/39.sram_ctrl_ram_cfg.4188500665
/workspace/coverage/default/39.sram_ctrl_regwen.517067257
/workspace/coverage/default/39.sram_ctrl_smoke.460944141
/workspace/coverage/default/39.sram_ctrl_stress_all.2681540766
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1988028600
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3182413295
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1548052711
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3597190051
/workspace/coverage/default/4.sram_ctrl_alert_test.429817846
/workspace/coverage/default/4.sram_ctrl_bijection.2821796921
/workspace/coverage/default/4.sram_ctrl_executable.2711772128
/workspace/coverage/default/4.sram_ctrl_lc_escalation.305008948
/workspace/coverage/default/4.sram_ctrl_max_throughput.1591790658
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.4000304124
/workspace/coverage/default/4.sram_ctrl_mem_walk.2578776376
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3262625816
/workspace/coverage/default/4.sram_ctrl_partial_access.1509395256
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.182951168
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3639674725
/workspace/coverage/default/4.sram_ctrl_regwen.1125762036
/workspace/coverage/default/4.sram_ctrl_sec_cm.433809972
/workspace/coverage/default/4.sram_ctrl_smoke.2651938280
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4142119210
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3674358603
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.77016327
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3934324332
/workspace/coverage/default/40.sram_ctrl_alert_test.3203684678
/workspace/coverage/default/40.sram_ctrl_bijection.41352639
/workspace/coverage/default/40.sram_ctrl_executable.2659911660
/workspace/coverage/default/40.sram_ctrl_lc_escalation.681424307
/workspace/coverage/default/40.sram_ctrl_max_throughput.2843956923
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2081904822
/workspace/coverage/default/40.sram_ctrl_mem_walk.79918783
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2238692402
/workspace/coverage/default/40.sram_ctrl_partial_access.2296040890
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1428476109
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2933378516
/workspace/coverage/default/40.sram_ctrl_regwen.3171687999
/workspace/coverage/default/40.sram_ctrl_smoke.1611307666
/workspace/coverage/default/40.sram_ctrl_stress_all.3441502530
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.893333519
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2947612273
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3061394513
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1851166884
/workspace/coverage/default/41.sram_ctrl_alert_test.3439631609
/workspace/coverage/default/41.sram_ctrl_bijection.917626847
/workspace/coverage/default/41.sram_ctrl_executable.2123289129
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1502100572
/workspace/coverage/default/41.sram_ctrl_max_throughput.707957917
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.642698400
/workspace/coverage/default/41.sram_ctrl_mem_walk.14032359
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1342153967
/workspace/coverage/default/41.sram_ctrl_partial_access.3563840477
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.951887185
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3647555570
/workspace/coverage/default/41.sram_ctrl_regwen.1728504116
/workspace/coverage/default/41.sram_ctrl_smoke.903447016
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2585426840
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2780256880
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.382401086
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2279826126
/workspace/coverage/default/42.sram_ctrl_alert_test.1706938834
/workspace/coverage/default/42.sram_ctrl_bijection.2224133522
/workspace/coverage/default/42.sram_ctrl_executable.3177081895
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1015686107
/workspace/coverage/default/42.sram_ctrl_max_throughput.1239321929
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2262615044
/workspace/coverage/default/42.sram_ctrl_mem_walk.2244447338
/workspace/coverage/default/42.sram_ctrl_multiple_keys.515818248
/workspace/coverage/default/42.sram_ctrl_partial_access.2658325080
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1981729268
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3586708058
/workspace/coverage/default/42.sram_ctrl_regwen.329627962
/workspace/coverage/default/42.sram_ctrl_smoke.2720388979
/workspace/coverage/default/42.sram_ctrl_stress_all.3492813898
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3361144144
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3789915464
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2220651420
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.743169031
/workspace/coverage/default/43.sram_ctrl_alert_test.1190284062
/workspace/coverage/default/43.sram_ctrl_bijection.1555274752
/workspace/coverage/default/43.sram_ctrl_executable.1300549825
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3431736538
/workspace/coverage/default/43.sram_ctrl_max_throughput.2181104129
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1690303767
/workspace/coverage/default/43.sram_ctrl_mem_walk.2552383684
/workspace/coverage/default/43.sram_ctrl_multiple_keys.529904278
/workspace/coverage/default/43.sram_ctrl_partial_access.1606152013
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3413428846
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1339388303
/workspace/coverage/default/43.sram_ctrl_regwen.1499765614
/workspace/coverage/default/43.sram_ctrl_smoke.3140233170
/workspace/coverage/default/43.sram_ctrl_stress_all.3607956627
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2092922263
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2533642206
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1081490877
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3997080576
/workspace/coverage/default/44.sram_ctrl_alert_test.2502461822
/workspace/coverage/default/44.sram_ctrl_bijection.2076190554
/workspace/coverage/default/44.sram_ctrl_executable.3005914945
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1205892212
/workspace/coverage/default/44.sram_ctrl_max_throughput.2596402265
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2915222743
/workspace/coverage/default/44.sram_ctrl_mem_walk.3892420970
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2268759879
/workspace/coverage/default/44.sram_ctrl_partial_access.1714382976
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2855309509
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2495401809
/workspace/coverage/default/44.sram_ctrl_regwen.662474240
/workspace/coverage/default/44.sram_ctrl_smoke.3625539878
/workspace/coverage/default/44.sram_ctrl_stress_all.3757548342
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2597427873
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.4116955568
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2171413552
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.535765756
/workspace/coverage/default/45.sram_ctrl_alert_test.1458547322
/workspace/coverage/default/45.sram_ctrl_bijection.394236927
/workspace/coverage/default/45.sram_ctrl_executable.829666055
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1465316635
/workspace/coverage/default/45.sram_ctrl_max_throughput.2929322852
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1034544872
/workspace/coverage/default/45.sram_ctrl_mem_walk.201142411
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1635127278
/workspace/coverage/default/45.sram_ctrl_partial_access.3650831253
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3000079288
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2469711266
/workspace/coverage/default/45.sram_ctrl_regwen.3816793057
/workspace/coverage/default/45.sram_ctrl_smoke.3162233441
/workspace/coverage/default/45.sram_ctrl_stress_all.415874548
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3200849572
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2715947742
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1874495341
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1847599228
/workspace/coverage/default/46.sram_ctrl_alert_test.2016340354
/workspace/coverage/default/46.sram_ctrl_bijection.3439322632
/workspace/coverage/default/46.sram_ctrl_executable.898672727
/workspace/coverage/default/46.sram_ctrl_lc_escalation.465382262
/workspace/coverage/default/46.sram_ctrl_max_throughput.2646580661
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.127775580
/workspace/coverage/default/46.sram_ctrl_mem_walk.809735504
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3572801013
/workspace/coverage/default/46.sram_ctrl_partial_access.478336688
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3577036621
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2980920230
/workspace/coverage/default/46.sram_ctrl_regwen.2012969400
/workspace/coverage/default/46.sram_ctrl_smoke.93130432
/workspace/coverage/default/46.sram_ctrl_stress_all.711571534
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2862549514
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1236218745
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2964217436
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1308628246
/workspace/coverage/default/47.sram_ctrl_alert_test.3516422264
/workspace/coverage/default/47.sram_ctrl_bijection.3936232123
/workspace/coverage/default/47.sram_ctrl_executable.3583584649
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4279724682
/workspace/coverage/default/47.sram_ctrl_max_throughput.3193766274
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2415826978
/workspace/coverage/default/47.sram_ctrl_mem_walk.2316359666
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4143789005
/workspace/coverage/default/47.sram_ctrl_partial_access.521421411
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3574531532
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2463570012
/workspace/coverage/default/47.sram_ctrl_regwen.2278388468
/workspace/coverage/default/47.sram_ctrl_smoke.1142253933
/workspace/coverage/default/47.sram_ctrl_stress_all.2526865268
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.891629247
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4129817636
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4110775422
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.628024584
/workspace/coverage/default/48.sram_ctrl_alert_test.3453382873
/workspace/coverage/default/48.sram_ctrl_bijection.27403393
/workspace/coverage/default/48.sram_ctrl_executable.3796001829
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1412038505
/workspace/coverage/default/48.sram_ctrl_max_throughput.1783587076
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4205978543
/workspace/coverage/default/48.sram_ctrl_mem_walk.3097866129
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1693520010
/workspace/coverage/default/48.sram_ctrl_partial_access.2998445721
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4115730205
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2790656529
/workspace/coverage/default/48.sram_ctrl_regwen.4019759576
/workspace/coverage/default/48.sram_ctrl_smoke.73229907
/workspace/coverage/default/48.sram_ctrl_stress_all.3839277109
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2511036658
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2318182791
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2925150305
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2262353193
/workspace/coverage/default/49.sram_ctrl_alert_test.1475672899
/workspace/coverage/default/49.sram_ctrl_bijection.2656946724
/workspace/coverage/default/49.sram_ctrl_executable.437984438
/workspace/coverage/default/49.sram_ctrl_max_throughput.272223672
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2866977346
/workspace/coverage/default/49.sram_ctrl_mem_walk.1282806099
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1288828570
/workspace/coverage/default/49.sram_ctrl_partial_access.1778897769
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1291823666
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3508699116
/workspace/coverage/default/49.sram_ctrl_regwen.2366862164
/workspace/coverage/default/49.sram_ctrl_smoke.1246206417
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1374439252
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1872487819
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3970082275
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1705247730
/workspace/coverage/default/5.sram_ctrl_alert_test.2714588376
/workspace/coverage/default/5.sram_ctrl_bijection.390643054
/workspace/coverage/default/5.sram_ctrl_executable.2971304718
/workspace/coverage/default/5.sram_ctrl_max_throughput.4288343102
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1401122488
/workspace/coverage/default/5.sram_ctrl_mem_walk.3662277971
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2415500777
/workspace/coverage/default/5.sram_ctrl_partial_access.3465277843
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1046132799
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3044791604
/workspace/coverage/default/5.sram_ctrl_regwen.1663106791
/workspace/coverage/default/5.sram_ctrl_smoke.1737100454
/workspace/coverage/default/5.sram_ctrl_stress_all.3643292646
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1224373252
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1677652454
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1038339044
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.206794666
/workspace/coverage/default/6.sram_ctrl_alert_test.2065872948
/workspace/coverage/default/6.sram_ctrl_bijection.2810713613
/workspace/coverage/default/6.sram_ctrl_executable.608344890
/workspace/coverage/default/6.sram_ctrl_lc_escalation.156406539
/workspace/coverage/default/6.sram_ctrl_max_throughput.3415605744
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.883450375
/workspace/coverage/default/6.sram_ctrl_mem_walk.1473732177
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3971460910
/workspace/coverage/default/6.sram_ctrl_partial_access.3152671993
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.569669385
/workspace/coverage/default/6.sram_ctrl_ram_cfg.189655007
/workspace/coverage/default/6.sram_ctrl_regwen.391897431
/workspace/coverage/default/6.sram_ctrl_smoke.1796006761
/workspace/coverage/default/6.sram_ctrl_stress_all.3934058984
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.390982351
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1617699864
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2632912997
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1687599318
/workspace/coverage/default/7.sram_ctrl_alert_test.3344855191
/workspace/coverage/default/7.sram_ctrl_bijection.2743114305
/workspace/coverage/default/7.sram_ctrl_executable.2120522851
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2146985111
/workspace/coverage/default/7.sram_ctrl_max_throughput.2134490369
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4127288749
/workspace/coverage/default/7.sram_ctrl_mem_walk.1647336532
/workspace/coverage/default/7.sram_ctrl_multiple_keys.352993953
/workspace/coverage/default/7.sram_ctrl_partial_access.3508100532
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.706358982
/workspace/coverage/default/7.sram_ctrl_ram_cfg.603305109
/workspace/coverage/default/7.sram_ctrl_regwen.3418995999
/workspace/coverage/default/7.sram_ctrl_smoke.1381734286
/workspace/coverage/default/7.sram_ctrl_stress_all.1271503163
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1779843887
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3945064644
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4264614193
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.388037648
/workspace/coverage/default/8.sram_ctrl_alert_test.42448929
/workspace/coverage/default/8.sram_ctrl_bijection.264139644
/workspace/coverage/default/8.sram_ctrl_executable.4288765783
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2757372189
/workspace/coverage/default/8.sram_ctrl_max_throughput.1704620038
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.170241353
/workspace/coverage/default/8.sram_ctrl_mem_walk.4128646863
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1714238253
/workspace/coverage/default/8.sram_ctrl_partial_access.2457111022
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1587605130
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2729703666
/workspace/coverage/default/8.sram_ctrl_regwen.584135295
/workspace/coverage/default/8.sram_ctrl_smoke.4246342417
/workspace/coverage/default/8.sram_ctrl_stress_all.2957292106
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2453442404
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2493793366
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2517476872
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3990881784
/workspace/coverage/default/9.sram_ctrl_alert_test.1770633948
/workspace/coverage/default/9.sram_ctrl_bijection.3529326241
/workspace/coverage/default/9.sram_ctrl_executable.2882176936
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3263075635
/workspace/coverage/default/9.sram_ctrl_max_throughput.3163091644
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4116709455
/workspace/coverage/default/9.sram_ctrl_mem_walk.42662712
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4078377960
/workspace/coverage/default/9.sram_ctrl_partial_access.2415349217
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.228326119
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1702216885
/workspace/coverage/default/9.sram_ctrl_regwen.2315907823
/workspace/coverage/default/9.sram_ctrl_smoke.567556538
/workspace/coverage/default/9.sram_ctrl_stress_all.2429745948
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3962641121
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3270555132
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.406130538



Total test records in report: 1029
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2790656529 Dec 24 12:37:19 PM PST 23 Dec 24 12:37:31 PM PST 23 32029749 ps
T2 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1559839033 Dec 24 12:35:21 PM PST 23 Dec 24 12:35:50 PM PST 23 33407221 ps
T3 /workspace/coverage/default/15.sram_ctrl_stress_all.3347731329 Dec 24 12:36:04 PM PST 23 Dec 24 01:44:45 PM PST 23 14359929491 ps
T4 /workspace/coverage/default/42.sram_ctrl_multiple_keys.515818248 Dec 24 12:36:58 PM PST 23 Dec 24 12:43:15 PM PST 23 1346470885 ps
T5 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1326008427 Dec 24 12:35:42 PM PST 23 Dec 24 12:43:58 PM PST 23 21701913184 ps
T6 /workspace/coverage/default/18.sram_ctrl_lc_escalation.3877230498 Dec 24 12:35:32 PM PST 23 Dec 24 12:36:08 PM PST 23 929526688 ps
T7 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2081904822 Dec 24 12:36:59 PM PST 23 Dec 24 12:37:20 PM PST 23 691611652 ps
T9 /workspace/coverage/default/41.sram_ctrl_partial_access.3563840477 Dec 24 12:37:08 PM PST 23 Dec 24 12:38:35 PM PST 23 2372801009 ps
T10 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2557377444 Dec 24 12:36:15 PM PST 23 Dec 24 12:39:22 PM PST 23 2957550777 ps
T11 /workspace/coverage/default/3.sram_ctrl_mem_walk.1219324287 Dec 24 12:35:16 PM PST 23 Dec 24 12:35:55 PM PST 23 2718544992 ps
T12 /workspace/coverage/default/27.sram_ctrl_partial_access.2684496139 Dec 24 12:36:17 PM PST 23 Dec 24 12:36:52 PM PST 23 1806935188 ps
T13 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2582563040 Dec 24 12:36:30 PM PST 23 Dec 24 12:40:34 PM PST 23 10557071927 ps
T14 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.883450375 Dec 24 12:35:30 PM PST 23 Dec 24 12:35:58 PM PST 23 211251299 ps
T8 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2757372189 Dec 24 12:35:21 PM PST 23 Dec 24 12:35:53 PM PST 23 987999440 ps
T81 /workspace/coverage/default/43.sram_ctrl_mem_walk.2552383684 Dec 24 12:37:07 PM PST 23 Dec 24 12:37:26 PM PST 23 148807645 ps
T82 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2421154749 Dec 24 12:35:49 PM PST 23 Dec 24 12:41:38 PM PST 23 13365922239 ps
T30 /workspace/coverage/default/20.sram_ctrl_multiple_keys.3304468129 Dec 24 12:35:39 PM PST 23 Dec 24 12:43:02 PM PST 23 30821065767 ps
T110 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1020399665 Dec 24 12:36:00 PM PST 23 Dec 24 12:37:14 PM PST 23 116239811 ps
T34 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2980920230 Dec 24 12:37:21 PM PST 23 Dec 24 12:37:34 PM PST 23 30079318 ps
T27 /workspace/coverage/default/44.sram_ctrl_stress_all.3757548342 Dec 24 12:37:14 PM PST 23 Dec 24 01:20:42 PM PST 23 34371013683 ps
T19 /workspace/coverage/default/19.sram_ctrl_alert_test.2699490057 Dec 24 12:36:37 PM PST 23 Dec 24 12:36:54 PM PST 23 23062990 ps
T86 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.170241353 Dec 24 12:35:16 PM PST 23 Dec 24 12:35:50 PM PST 23 118566902 ps
T129 /workspace/coverage/default/43.sram_ctrl_smoke.3140233170 Dec 24 12:37:37 PM PST 23 Dec 24 12:37:46 PM PST 23 124742915 ps
T15 /workspace/coverage/default/31.sram_ctrl_executable.3345923142 Dec 24 12:36:25 PM PST 23 Dec 24 12:49:50 PM PST 23 49363762395 ps
T22 /workspace/coverage/default/2.sram_ctrl_sec_cm.2304564368 Dec 24 12:35:17 PM PST 23 Dec 24 12:35:48 PM PST 23 1218161459 ps
T37 /workspace/coverage/default/40.sram_ctrl_lc_escalation.681424307 Dec 24 12:36:59 PM PST 23 Dec 24 12:37:24 PM PST 23 2501775789 ps
T38 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2534553032 Dec 24 12:36:29 PM PST 23 Dec 24 12:43:44 PM PST 23 34027259980 ps
T39 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1709539852 Dec 24 12:36:25 PM PST 23 Dec 24 12:42:50 PM PST 23 4985590852 ps
T40 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.581540873 Dec 24 12:35:47 PM PST 23 Dec 24 12:40:13 PM PST 23 10131580048 ps
T41 /workspace/coverage/default/46.sram_ctrl_mem_walk.809735504 Dec 24 12:37:25 PM PST 23 Dec 24 12:37:45 PM PST 23 510925658 ps
T42 /workspace/coverage/default/29.sram_ctrl_lc_escalation.3763511382 Dec 24 12:36:23 PM PST 23 Dec 24 12:36:43 PM PST 23 229270073 ps
T43 /workspace/coverage/default/16.sram_ctrl_mem_walk.750828327 Dec 24 12:35:55 PM PST 23 Dec 24 12:36:21 PM PST 23 1510904534 ps
T44 /workspace/coverage/default/7.sram_ctrl_max_throughput.2134490369 Dec 24 12:35:19 PM PST 23 Dec 24 12:35:56 PM PST 23 219801771 ps
T45 /workspace/coverage/default/21.sram_ctrl_smoke.2575148792 Dec 24 12:36:14 PM PST 23 Dec 24 12:36:41 PM PST 23 746155612 ps
T16 /workspace/coverage/default/39.sram_ctrl_regwen.517067257 Dec 24 12:37:12 PM PST 23 Dec 24 12:46:22 PM PST 23 9259134492 ps
T104 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1700806915 Dec 24 12:35:39 PM PST 23 Dec 24 12:39:03 PM PST 23 3840677975 ps
T105 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1765240661 Dec 24 12:36:10 PM PST 23 Dec 24 12:40:00 PM PST 23 12794052281 ps
T17 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.535765756 Dec 24 12:37:17 PM PST 23 Dec 24 12:41:12 PM PST 23 1880163700 ps
T130 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1367036179 Dec 24 12:35:08 PM PST 23 Dec 24 12:41:13 PM PST 23 3392540810 ps
T128 /workspace/coverage/default/23.sram_ctrl_lc_escalation.671235674 Dec 24 12:35:59 PM PST 23 Dec 24 12:36:24 PM PST 23 2897199087 ps
T131 /workspace/coverage/default/7.sram_ctrl_multiple_keys.352993953 Dec 24 12:35:37 PM PST 23 Dec 24 12:50:45 PM PST 23 43175274226 ps
T87 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3878237630 Dec 24 12:35:06 PM PST 23 Dec 24 12:35:42 PM PST 23 96720980 ps
T120 /workspace/coverage/default/48.sram_ctrl_executable.3796001829 Dec 24 12:37:37 PM PST 23 Dec 24 12:52:02 PM PST 23 15510604195 ps
T132 /workspace/coverage/default/32.sram_ctrl_mem_walk.2998538777 Dec 24 12:36:42 PM PST 23 Dec 24 12:37:04 PM PST 23 582265515 ps
T25 /workspace/coverage/default/11.sram_ctrl_regwen.3195225190 Dec 24 12:35:25 PM PST 23 Dec 24 12:51:37 PM PST 23 54176642606 ps
T28 /workspace/coverage/default/2.sram_ctrl_stress_all.3249381872 Dec 24 12:35:06 PM PST 23 Dec 24 01:02:14 PM PST 23 118572921412 ps
T20 /workspace/coverage/default/16.sram_ctrl_alert_test.2046273712 Dec 24 12:36:01 PM PST 23 Dec 24 12:36:21 PM PST 23 22697706 ps
T18 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2262353193 Dec 24 12:37:53 PM PST 23 Dec 24 12:40:09 PM PST 23 275722096 ps
T31 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4142119210 Dec 24 12:35:36 PM PST 23 Dec 24 01:06:56 PM PST 23 594468146 ps
T58 /workspace/coverage/default/8.sram_ctrl_max_throughput.1704620038 Dec 24 12:35:31 PM PST 23 Dec 24 12:36:04 PM PST 23 208946969 ps
T59 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2291843586 Dec 24 12:36:14 PM PST 23 Dec 24 12:38:32 PM PST 23 1241218031 ps
T26 /workspace/coverage/default/7.sram_ctrl_regwen.3418995999 Dec 24 12:35:25 PM PST 23 Dec 24 12:43:33 PM PST 23 1378265273 ps
T60 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2866977346 Dec 24 12:37:53 PM PST 23 Dec 24 12:38:01 PM PST 23 252475828 ps
T61 /workspace/coverage/default/6.sram_ctrl_stress_all.3934058984 Dec 24 12:35:35 PM PST 23 Dec 24 01:26:04 PM PST 23 38932365869 ps
T62 /workspace/coverage/default/33.sram_ctrl_executable.674805260 Dec 24 12:36:27 PM PST 23 Dec 24 12:49:10 PM PST 23 3429384648 ps
T63 /workspace/coverage/default/44.sram_ctrl_ram_cfg.2495401809 Dec 24 12:37:00 PM PST 23 Dec 24 12:37:17 PM PST 23 79647558 ps
T64 /workspace/coverage/default/43.sram_ctrl_multiple_keys.529904278 Dec 24 12:37:33 PM PST 23 Dec 24 12:48:41 PM PST 23 6632475865 ps
T65 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1581505243 Dec 24 12:36:06 PM PST 23 Dec 24 12:36:28 PM PST 23 108857997 ps
T88 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3703058557 Dec 24 12:36:03 PM PST 23 Dec 24 12:48:40 PM PST 23 2429123869 ps
T29 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1502100572 Dec 24 12:36:58 PM PST 23 Dec 24 12:37:22 PM PST 23 645536141 ps
T133 /workspace/coverage/default/31.sram_ctrl_regwen.2073887732 Dec 24 12:36:31 PM PST 23 Dec 24 12:49:17 PM PST 23 8405177168 ps
T32 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3912074777 Dec 24 12:35:48 PM PST 23 Dec 24 01:41:52 PM PST 23 1875446912 ps
T134 /workspace/coverage/default/0.sram_ctrl_smoke.2593249272 Dec 24 12:35:11 PM PST 23 Dec 24 12:35:53 PM PST 23 183960175 ps
T135 /workspace/coverage/default/12.sram_ctrl_multiple_keys.2783372770 Dec 24 12:35:29 PM PST 23 Dec 24 12:48:52 PM PST 23 6449830595 ps
T136 /workspace/coverage/default/1.sram_ctrl_mem_walk.3410902350 Dec 24 12:35:05 PM PST 23 Dec 24 12:35:43 PM PST 23 82615573 ps
T137 /workspace/coverage/default/17.sram_ctrl_smoke.1477598388 Dec 24 12:36:01 PM PST 23 Dec 24 12:37:02 PM PST 23 907764377 ps
T138 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2486762897 Dec 24 12:36:45 PM PST 23 Dec 24 12:37:04 PM PST 23 92476401 ps
T139 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2715947742 Dec 24 12:37:37 PM PST 23 Dec 24 12:39:57 PM PST 23 7861690873 ps
T140 /workspace/coverage/default/30.sram_ctrl_multiple_keys.4181467336 Dec 24 12:36:27 PM PST 23 Dec 24 12:38:42 PM PST 23 10916328056 ps
T141 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1108999925 Dec 24 12:37:12 PM PST 23 Dec 24 12:37:27 PM PST 23 28051243 ps
T142 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2253994752 Dec 24 12:35:58 PM PST 23 Dec 24 12:56:47 PM PST 23 6434654932 ps
T127 /workspace/coverage/default/14.sram_ctrl_partial_access.1029128787 Dec 24 12:35:20 PM PST 23 Dec 24 12:35:54 PM PST 23 701167508 ps
T143 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1984821175 Dec 24 12:35:05 PM PST 23 Dec 24 12:37:38 PM PST 23 303762185 ps
T144 /workspace/coverage/default/30.sram_ctrl_partial_access.442047860 Dec 24 12:36:53 PM PST 23 Dec 24 12:39:18 PM PST 23 2615050573 ps
T145 /workspace/coverage/default/10.sram_ctrl_regwen.319990738 Dec 24 12:35:33 PM PST 23 Dec 24 12:49:49 PM PST 23 2850601038 ps
T146 /workspace/coverage/default/29.sram_ctrl_mem_walk.986108472 Dec 24 12:36:16 PM PST 23 Dec 24 12:36:44 PM PST 23 436869713 ps
T147 /workspace/coverage/default/25.sram_ctrl_regwen.702106274 Dec 24 12:36:22 PM PST 23 Dec 24 12:38:32 PM PST 23 3792068305 ps
T148 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3878371624 Dec 24 12:35:45 PM PST 23 Dec 24 12:47:44 PM PST 23 5491817006 ps
T149 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3933504624 Dec 24 12:35:41 PM PST 23 Dec 24 12:36:12 PM PST 23 221127449 ps
T150 /workspace/coverage/default/45.sram_ctrl_mem_walk.201142411 Dec 24 12:37:12 PM PST 23 Dec 24 12:37:35 PM PST 23 540027429 ps
T151 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1034544872 Dec 24 12:37:33 PM PST 23 Dec 24 12:37:44 PM PST 23 161648939 ps
T33 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4038319510 Dec 24 12:36:59 PM PST 23 Dec 24 01:46:41 PM PST 23 7456175348 ps
T152 /workspace/coverage/default/32.sram_ctrl_executable.3191375293 Dec 24 12:36:16 PM PST 23 Dec 24 12:40:05 PM PST 23 1606476996 ps
T153 /workspace/coverage/default/17.sram_ctrl_mem_walk.221088875 Dec 24 12:36:00 PM PST 23 Dec 24 12:36:25 PM PST 23 235874195 ps
T154 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3221747687 Dec 24 12:36:11 PM PST 23 Dec 24 12:48:45 PM PST 23 3440017101 ps
T122 /workspace/coverage/default/32.sram_ctrl_regwen.964805166 Dec 24 12:36:51 PM PST 23 Dec 24 12:49:05 PM PST 23 9120862374 ps
T155 /workspace/coverage/default/48.sram_ctrl_smoke.73229907 Dec 24 12:37:35 PM PST 23 Dec 24 12:37:57 PM PST 23 2190901575 ps
T156 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3289507926 Dec 24 12:35:59 PM PST 23 Dec 24 12:50:07 PM PST 23 24062481380 ps
T157 /workspace/coverage/default/6.sram_ctrl_ram_cfg.189655007 Dec 24 12:35:21 PM PST 23 Dec 24 12:35:50 PM PST 23 26468494 ps
T125 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1046132799 Dec 24 12:35:11 PM PST 23 Dec 24 12:42:48 PM PST 23 17170631334 ps
T158 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2533642206 Dec 24 12:37:29 PM PST 23 Dec 24 12:41:52 PM PST 23 36122228511 ps
T159 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3408356059 Dec 24 12:35:26 PM PST 23 Dec 24 12:59:22 PM PST 23 18813650713 ps
T160 /workspace/coverage/default/31.sram_ctrl_max_throughput.2924442117 Dec 24 12:36:31 PM PST 23 Dec 24 12:39:13 PM PST 23 144776821 ps
T49 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3827657942 Dec 24 12:35:23 PM PST 23 Dec 24 12:52:13 PM PST 23 6435810441 ps
T46 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.621209526 Dec 24 12:26:59 PM PST 23 Dec 24 12:27:09 PM PST 23 2134215101 ps
T47 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1973596856 Dec 24 12:29:32 PM PST 23 Dec 24 12:29:46 PM PST 23 83967347 ps
T50 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2194469497 Dec 24 12:30:08 PM PST 23 Dec 24 12:30:35 PM PST 23 30645557 ps
T70 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.952683518 Dec 24 12:27:58 PM PST 23 Dec 24 12:28:12 PM PST 23 13453309 ps
T71 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4270093599 Dec 24 12:28:42 PM PST 23 Dec 24 12:28:58 PM PST 23 1573947933 ps
T72 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342363909 Dec 24 12:27:38 PM PST 23 Dec 24 12:27:40 PM PST 23 16739550 ps
T103 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2661607395 Dec 24 12:27:26 PM PST 23 Dec 24 12:27:30 PM PST 23 37202225 ps
T73 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4007235579 Dec 24 12:26:54 PM PST 23 Dec 24 12:26:59 PM PST 23 955326946 ps
T51 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2610709881 Dec 24 12:27:15 PM PST 23 Dec 24 12:27:21 PM PST 23 88888031 ps
T52 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3554058035 Dec 24 12:27:50 PM PST 23 Dec 24 12:28:00 PM PST 23 35054058 ps
T74 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2399493865 Dec 24 12:27:58 PM PST 23 Dec 24 12:28:12 PM PST 23 31456596 ps
T75 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.591400349 Dec 24 12:28:15 PM PST 23 Dec 24 12:28:28 PM PST 23 136892915 ps
T53 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2439186078 Dec 24 12:28:46 PM PST 23 Dec 24 12:28:56 PM PST 23 41635053 ps
T48 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3503289552 Dec 24 12:28:12 PM PST 23 Dec 24 12:28:28 PM PST 23 191899230 ps
T54 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1739898379 Dec 24 12:28:07 PM PST 23 Dec 24 12:28:22 PM PST 23 258682320 ps
T55 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.112379345 Dec 24 12:27:42 PM PST 23 Dec 24 12:27:47 PM PST 23 349607651 ps
T76 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3332129117 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:16 PM PST 23 88008504 ps
T83 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3365182937 Dec 24 12:27:51 PM PST 23 Dec 24 12:28:09 PM PST 23 11712687 ps
T77 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1203932152 Dec 24 12:27:52 PM PST 23 Dec 24 12:28:00 PM PST 23 115603608 ps
T84 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.365909852 Dec 24 12:27:16 PM PST 23 Dec 24 12:27:21 PM PST 23 23512715 ps
T56 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2307405209 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:12 PM PST 23 364542142 ps
T85 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2434219654 Dec 24 12:28:36 PM PST 23 Dec 24 12:28:43 PM PST 23 63758354 ps
T78 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2281932335 Dec 24 12:28:05 PM PST 23 Dec 24 12:28:18 PM PST 23 62933701 ps
T67 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1876105982 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:17 PM PST 23 35752813 ps
T66 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.838259504 Dec 24 12:29:37 PM PST 23 Dec 24 12:29:58 PM PST 23 167120116 ps
T161 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2876095590 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:00 PM PST 23 35844751 ps
T106 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.865214650 Dec 24 12:29:33 PM PST 23 Dec 24 12:29:47 PM PST 23 25691401 ps
T107 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3489721562 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:16 PM PST 23 16850723 ps
T162 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1096343486 Dec 24 12:28:07 PM PST 23 Dec 24 12:28:23 PM PST 23 38194150 ps
T108 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3849180449 Dec 24 12:27:14 PM PST 23 Dec 24 12:27:17 PM PST 23 145014782 ps
T109 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3771793648 Dec 24 12:28:03 PM PST 23 Dec 24 12:28:16 PM PST 23 46150704 ps
T113 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1084618898 Dec 24 12:27:58 PM PST 23 Dec 24 12:28:13 PM PST 23 268087392 ps
T79 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.72304167 Dec 24 12:28:33 PM PST 23 Dec 24 12:28:50 PM PST 23 759413492 ps
T57 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2165630135 Dec 24 12:29:52 PM PST 23 Dec 24 12:30:20 PM PST 23 174186134 ps
T68 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1431968491 Dec 24 12:26:59 PM PST 23 Dec 24 12:27:07 PM PST 23 641480863 ps
T94 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3708011872 Dec 24 12:27:58 PM PST 23 Dec 24 12:28:26 PM PST 23 759999811 ps
T69 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2888329081 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:12 PM PST 23 36927958 ps
T95 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.435943048 Dec 24 12:29:33 PM PST 23 Dec 24 12:29:57 PM PST 23 61828930 ps
T96 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3902161499 Dec 24 12:26:56 PM PST 23 Dec 24 12:27:01 PM PST 23 102268996 ps
T97 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.645268614 Dec 24 12:31:19 PM PST 23 Dec 24 12:31:45 PM PST 23 63775603 ps
T163 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2893628200 Dec 24 12:30:05 PM PST 23 Dec 24 12:30:31 PM PST 23 28354056 ps
T118 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.489207592 Dec 24 12:27:15 PM PST 23 Dec 24 12:27:19 PM PST 23 196198090 ps
T164 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3100008096 Dec 24 12:27:58 PM PST 23 Dec 24 12:28:12 PM PST 23 25731336 ps
T165 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3174724593 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:12 PM PST 23 42855780 ps
T80 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1096285673 Dec 24 12:29:29 PM PST 23 Dec 24 12:29:43 PM PST 23 231662625 ps
T166 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1964241361 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:16 PM PST 23 39600137 ps
T167 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1139543278 Dec 24 12:27:13 PM PST 23 Dec 24 12:27:16 PM PST 23 39287170 ps
T168 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2096562733 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:11 PM PST 23 28132505 ps
T111 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3693381155 Dec 24 12:28:03 PM PST 23 Dec 24 12:28:18 PM PST 23 224005883 ps
T169 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1069605576 Dec 24 12:28:42 PM PST 23 Dec 24 12:28:49 PM PST 23 154313116 ps
T170 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.658232560 Dec 24 12:29:28 PM PST 23 Dec 24 12:29:39 PM PST 23 30647556 ps
T171 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4240295269 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:21 PM PST 23 1561554389 ps
T89 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.576729590 Dec 24 12:28:08 PM PST 23 Dec 24 12:28:24 PM PST 23 441797589 ps
T172 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2807490891 Dec 24 12:27:13 PM PST 23 Dec 24 12:27:18 PM PST 23 1947303904 ps
T173 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3855639383 Dec 24 12:28:44 PM PST 23 Dec 24 12:28:52 PM PST 23 60691264 ps
T112 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4049767996 Dec 24 12:27:55 PM PST 23 Dec 24 12:28:09 PM PST 23 673357532 ps
T174 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2379556785 Dec 24 12:30:04 PM PST 23 Dec 24 12:30:33 PM PST 23 392628905 ps
T119 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3638449577 Dec 24 12:27:10 PM PST 23 Dec 24 12:27:15 PM PST 23 113257751 ps
T90 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3627285419 Dec 24 12:27:13 PM PST 23 Dec 24 12:27:27 PM PST 23 1479294766 ps
T175 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.291737391 Dec 24 12:29:20 PM PST 23 Dec 24 12:29:31 PM PST 23 57412000 ps
T176 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2624491391 Dec 24 12:27:21 PM PST 23 Dec 24 12:27:26 PM PST 23 466288909 ps
T177 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1089526852 Dec 24 12:27:50 PM PST 23 Dec 24 12:28:00 PM PST 23 17457216 ps
T91 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1279453237 Dec 24 12:26:59 PM PST 23 Dec 24 12:27:07 PM PST 23 716889289 ps
T178 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4179624844 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:18 PM PST 23 31560153 ps
T116 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.645666084 Dec 24 12:27:05 PM PST 23 Dec 24 12:27:11 PM PST 23 601741659 ps
T179 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1875269662 Dec 24 12:27:52 PM PST 23 Dec 24 12:28:09 PM PST 23 118049607 ps
T92 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3419429238 Dec 24 12:28:49 PM PST 23 Dec 24 12:29:01 PM PST 23 16950305 ps
T180 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2223631721 Dec 24 12:27:54 PM PST 23 Dec 24 12:28:02 PM PST 23 25996301 ps
T181 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4291156823 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:14 PM PST 23 112931473 ps
T182 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2890380132 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:29 PM PST 23 505679213 ps
T93 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2247409301 Dec 24 12:27:16 PM PST 23 Dec 24 12:27:25 PM PST 23 3222203012 ps
T183 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2374725580 Dec 24 12:27:02 PM PST 23 Dec 24 12:27:09 PM PST 23 160427661 ps
T184 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4050198624 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:21 PM PST 23 26410380 ps
T185 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.607131666 Dec 24 12:27:55 PM PST 23 Dec 24 12:28:08 PM PST 23 42497227 ps
T186 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3534980451 Dec 24 12:27:24 PM PST 23 Dec 24 12:27:33 PM PST 23 249537600 ps
T102 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3374024187 Dec 24 12:29:54 PM PST 23 Dec 24 12:30:22 PM PST 23 218127882 ps
T187 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2505525573 Dec 24 12:27:01 PM PST 23 Dec 24 12:27:09 PM PST 23 38217213 ps
T188 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4098905315 Dec 24 12:28:48 PM PST 23 Dec 24 12:28:58 PM PST 23 15229746 ps
T189 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2809136158 Dec 24 12:27:04 PM PST 23 Dec 24 12:27:12 PM PST 23 114097251 ps
T190 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1943769654 Dec 24 12:27:13 PM PST 23 Dec 24 12:27:18 PM PST 23 847719312 ps
T191 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3791446267 Dec 24 12:28:35 PM PST 23 Dec 24 12:28:45 PM PST 23 170228282 ps
T192 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2697339950 Dec 24 12:27:56 PM PST 23 Dec 24 12:28:15 PM PST 23 14263182 ps
T117 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1362213540 Dec 24 12:28:16 PM PST 23 Dec 24 12:28:30 PM PST 23 231216292 ps
T98 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1266661343 Dec 24 12:28:32 PM PST 23 Dec 24 12:28:43 PM PST 23 1644264412 ps
T193 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.870912768 Dec 24 12:26:57 PM PST 23 Dec 24 12:27:01 PM PST 23 45765487 ps
T194 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.104690453 Dec 24 12:29:15 PM PST 23 Dec 24 12:29:20 PM PST 23 63451793 ps
T195 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3608274564 Dec 24 12:27:31 PM PST 23 Dec 24 12:27:33 PM PST 23 49634717 ps
T196 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3687307436 Dec 24 12:27:19 PM PST 23 Dec 24 12:27:24 PM PST 23 70359750 ps
T197 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3570705769 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:17 PM PST 23 100168062 ps
T198 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4133927703 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:00 PM PST 23 22924819 ps
T199 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2604815515 Dec 24 12:27:30 PM PST 23 Dec 24 12:27:34 PM PST 23 29791142 ps
T200 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2626626395 Dec 24 12:29:33 PM PST 23 Dec 24 12:29:47 PM PST 23 11370055 ps
T201 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.177027208 Dec 24 12:29:40 PM PST 23 Dec 24 12:30:07 PM PST 23 826466397 ps
T202 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.395340794 Dec 24 12:29:25 PM PST 23 Dec 24 12:29:35 PM PST 23 474084141 ps
T203 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2195326560 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:24 PM PST 23 35059600 ps
T204 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.997844039 Dec 24 12:27:09 PM PST 23 Dec 24 12:27:13 PM PST 23 82653431 ps
T205 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1049559636 Dec 24 12:27:01 PM PST 23 Dec 24 12:27:07 PM PST 23 23002161 ps
T206 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2849997666 Dec 24 12:27:00 PM PST 23 Dec 24 12:27:06 PM PST 23 25789732 ps
T207 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3198195208 Dec 24 12:29:36 PM PST 23 Dec 24 12:29:51 PM PST 23 15936243 ps
T208 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.906185428 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:13 PM PST 23 37096256 ps
T209 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.656079532 Dec 24 12:27:52 PM PST 23 Dec 24 12:28:00 PM PST 23 97220617 ps
T210 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.713558044 Dec 24 12:27:16 PM PST 23 Dec 24 12:27:20 PM PST 23 52628924 ps
T211 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.598238915 Dec 24 12:28:08 PM PST 23 Dec 24 12:28:22 PM PST 23 74646338 ps
T212 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2381721877 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:19 PM PST 23 36265259 ps
T213 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3465005 Dec 24 12:27:11 PM PST 23 Dec 24 12:27:15 PM PST 23 32365004 ps
T214 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4242329390 Dec 24 12:27:06 PM PST 23 Dec 24 12:27:21 PM PST 23 466820698 ps
T215 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.266399782 Dec 24 12:27:14 PM PST 23 Dec 24 12:27:18 PM PST 23 79855696 ps
T216 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1546002766 Dec 24 12:29:14 PM PST 23 Dec 24 12:29:21 PM PST 23 908919850 ps
T99 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.502204 Dec 24 12:27:24 PM PST 23 Dec 24 12:27:31 PM PST 23 999414890 ps
T217 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.874716019 Dec 24 12:29:32 PM PST 23 Dec 24 12:29:49 PM PST 23 207393138 ps
T218 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.112062435 Dec 24 12:27:02 PM PST 23 Dec 24 12:27:08 PM PST 23 77854243 ps
T100 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3977726456 Dec 24 12:31:33 PM PST 23 Dec 24 12:32:11 PM PST 23 561403507 ps
T219 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2142622437 Dec 24 12:27:32 PM PST 23 Dec 24 12:27:35 PM PST 23 19837169 ps
T220 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1032002929 Dec 24 12:27:10 PM PST 23 Dec 24 12:27:15 PM PST 23 16734191 ps
T221 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4157508339 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:04 PM PST 23 1006707846 ps
T222 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3555716740 Dec 24 12:27:06 PM PST 23 Dec 24 12:27:13 PM PST 23 76090165 ps
T114 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3074426997 Dec 24 12:27:15 PM PST 23 Dec 24 12:27:20 PM PST 23 158280773 ps
T101 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3705230816 Dec 24 12:28:05 PM PST 23 Dec 24 12:28:22 PM PST 23 5499759530 ps
T115 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4182489861 Dec 24 12:29:45 PM PST 23 Dec 24 12:30:08 PM PST 23 322908729 ps
T223 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.77681292 Dec 24 12:27:02 PM PST 23 Dec 24 12:27:08 PM PST 23 44635181 ps
T224 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3039900190 Dec 24 12:29:18 PM PST 23 Dec 24 12:29:27 PM PST 23 82391172 ps
T225 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1940924361 Dec 24 12:27:02 PM PST 23 Dec 24 12:27:07 PM PST 23 13657891 ps
T226 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.70773584 Dec 24 12:28:07 PM PST 23 Dec 24 12:28:23 PM PST 23 122906728 ps
T227 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3636304731 Dec 24 12:27:39 PM PST 23 Dec 24 12:27:41 PM PST 23 35905912 ps
T228 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2444446538 Dec 24 12:27:36 PM PST 23 Dec 24 12:27:40 PM PST 23 71287656 ps
T229 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2132430553 Dec 24 12:28:10 PM PST 23 Dec 24 12:28:27 PM PST 23 60256137 ps
T230 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3063948616 Dec 24 12:28:02 PM PST 23 Dec 24 12:28:16 PM PST 23 23815100 ps
T231 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.81792611 Dec 24 12:28:30 PM PST 23 Dec 24 12:28:40 PM PST 23 220584264 ps
T232 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3885073589 Dec 24 12:29:45 PM PST 23 Dec 24 12:30:09 PM PST 23 273586091 ps
T233 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.633051866 Dec 24 12:28:44 PM PST 23 Dec 24 12:28:51 PM PST 23 69141471 ps
T234 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3603879660 Dec 24 12:27:52 PM PST 23 Dec 24 12:28:00 PM PST 23 56045036 ps
T235 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1421156525 Dec 24 12:27:11 PM PST 23 Dec 24 12:27:16 PM PST 23 296550128 ps
T236 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3430795378 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:17 PM PST 23 109124562 ps
T237 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1821381266 Dec 24 12:27:15 PM PST 23 Dec 24 12:27:30 PM PST 23 447089585 ps
T238 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1880112551 Dec 24 12:29:35 PM PST 23 Dec 24 12:29:51 PM PST 23 282436488 ps
T239 /workspace/coverage/default/3.sram_ctrl_ram_cfg.4190398722 Dec 24 12:35:09 PM PST 23 Dec 24 12:35:42 PM PST 23 94338932 ps
T240 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2958926138 Dec 24 12:35:06 PM PST 23 Dec 24 12:41:38 PM PST 23 3916718350 ps
T241 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4110775422 Dec 24 12:37:50 PM PST 23 Dec 24 12:38:23 PM PST 23 108497091 ps
T242 /workspace/coverage/default/27.sram_ctrl_bijection.2444196494 Dec 24 12:36:23 PM PST 23 Dec 24 12:37:17 PM PST 23 569794144 ps
T243 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2980045164 Dec 24 12:36:26 PM PST 23 Dec 24 12:36:50 PM PST 23 222404522 ps
T244 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3704384152 Dec 24 12:36:53 PM PST 23 Dec 24 12:45:26 PM PST 23 10738150781 ps
T126 /workspace/coverage/default/24.sram_ctrl_stress_all.1178159752 Dec 24 12:36:12 PM PST 23 Dec 24 01:08:10 PM PST 23 28086800613 ps
T245 /workspace/coverage/default/27.sram_ctrl_executable.3875583617 Dec 24 12:36:07 PM PST 23 Dec 24 12:54:08 PM PST 23 12928430163 ps
T246 /workspace/coverage/default/4.sram_ctrl_partial_access.1509395256 Dec 24 12:35:12 PM PST 23 Dec 24 12:36:26 PM PST 23 695876519 ps
T247 /workspace/coverage/default/12.sram_ctrl_partial_access.1194293373 Dec 24 12:35:20 PM PST 23 Dec 24 12:35:49 PM PST 23 76663320 ps
T248 /workspace/coverage/default/18.sram_ctrl_bijection.4266232182 Dec 24 12:35:51 PM PST 23 Dec 24 12:37:01 PM PST 23 765747186 ps
T249 /workspace/coverage/default/20.sram_ctrl_lc_escalation.1571262447 Dec 24 12:36:19 PM PST 23 Dec 24 12:36:44 PM PST 23 3688943703 ps
T123 /workspace/coverage/default/22.sram_ctrl_stress_all.4055233580 Dec 24 12:36:12 PM PST 23 Dec 24 01:32:18 PM PST 23 91703203861 ps
T124 /workspace/coverage/default/45.sram_ctrl_executable.829666055 Dec 24 12:37:34 PM PST 23 Dec 24 12:57:00 PM PST 23 9459041013 ps
T250 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1712310075 Dec 24 12:37:01 PM PST 23 Dec 24 12:37:18 PM PST 23 49275136 ps
T251 /workspace/coverage/default/12.sram_ctrl_smoke.4085867504 Dec 24 12:35:37 PM PST 23 Dec 24 12:37:24 PM PST 23 3009800591 ps
T252 /workspace/coverage/default/24.sram_ctrl_partial_access.3219673844 Dec 24 12:36:21 PM PST 23 Dec 24 12:36:45 PM PST 23 1711497251 ps
T253 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2621329672 Dec 24 12:36:35 PM PST 23 Dec 24 12:41:51 PM PST 23 11399809129 ps
T254 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.4190126941 Dec 24 12:36:41 PM PST 23 Dec 24 12:42:08 PM PST 23 1189594606 ps
T255 /workspace/coverage/default/24.sram_ctrl_max_throughput.3535015660 Dec 24 12:36:17 PM PST 23 Dec 24 12:38:51 PM PST 23 146847766 ps
T256 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3258954383 Dec 24 12:36:40 PM PST 23 Dec 24 12:36:57 PM PST 23 28871949 ps
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