Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44618121	1			T3	401514		T4	74027		T5	49413
triple_byte_access	2495680	1			T3	7285		T4	1416		T5	44758
halfword_access	3747420	1			T3	10931		T4	2169		T5	66871
byte_access	5007482	1			T3	14481		T4	2917		T5	89287
zero_access	1258853	1			T3	3523		T4	736		T5	22500

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28502164

1

T3

219026

T4

40549

T5

136517

auto[1]

28625392

1

T3

218708

T4

40716

T5

136312

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22252928	1			T3	200757		T4	36894		T5	24852
auto[0]	triple_byte_access	1243220	1			T3	3663		T4	703		T5	22443
auto[0]	halfword_access	1871110	1			T3	5529		T4	1089		T5	33412
auto[0]	byte_access	2501724	1			T3	7301		T4	1472		T5	44598
auto[0]	zero_access	633182	1			T3	1776		T4	391		T5	11212
auto[1]	word_access	22365193	1			T3	200757		T4	37133		T5	24561
auto[1]	triple_byte_access	1252460	1			T3	3622		T4	713		T5	22315
auto[1]	halfword_access	1876310	1			T3	5402		T4	1080		T5	33459
auto[1]	byte_access	2505758	1			T3	7180		T4	1445		T5	44689
auto[1]	zero_access	625671	1			T3	1747		T4	345		T5	11288