Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	127114169	1			T1	3892		T2	2500		T3	445060
instr_valid_dis	99409186	1			T1	3892		T2	2500		T3	445060
instr_en	17948246	1			T14	50362		T15	15988		T113	45230

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9247667	1			T14	165822		T19	70410		T15	25605
sram_ifetch_valid_disable	98204890	1			T1	3892		T2	2500		T3	445060
sram_ifetch_enable	19661612	1			T14	209912		T19	4774		T15	7065

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	127114169	1			T1	3892		T2	2500		T3	445060
hw_debug_en_valid_off	97943639	1			T1	3892		T2	2500		T3	445060
hw_debug_en_on	19162927	1			T14	185816		T19	4774		T15	15988

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	98204890	1			T1	3892		T2	2500		T3	445060
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	86834299	1			T1	3892		T2	2500		T3	445060
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7604381	1			T113	17640		T112	152078		T111	55914
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4272776	1			T14	82866		T19	40474		T9	13782
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1909760	1			T19	40474		T9	6104		T30	75214
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1400596	1			T14	50362		T9	7678		T30	7454
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3499425	1			T14	82956		T15	8923		T59	107042
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1469661	1			T59	107042		T124	356		T114	57308
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1188188	1			T15	8923		T37	92		T30	13074
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7846173	1			T14	14872		T59	47420		T112	162836
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3514949	1			T59	47420		T112	18204		T37	54816
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2838399	1			T112	130890		T111	17692		T37	74430

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7247006	1			T15	7065		T113	27590		T59	55828
lc_exec_en	7817329	1			T14	87988		T19	4774		T15	7065
valid_exec_dis	94760601	1			T1	3892		T2	2500		T3	445060
invalid_exec_dis	28909279	1			T14	375734		T19	75184		T15	32670