| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2230381657 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3122286259 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.74404709 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1737957900 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3042386443 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3512453980 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1172084851 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2911532892 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3925753796 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2295337229 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.302328971 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.50880245 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3852121063 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.850451521 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3321546465 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2235257773 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1429828265 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3783186930 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2186844031 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2557553233 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3484876981 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4267703376 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3304046050 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3467181007 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3652708791 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3768501880 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2141481708 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2957846524 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.581828237 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2726435815 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1484221626 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1633075164 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1830177212 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4075276130 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3118396025 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.895947800 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2998515390 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.533482156 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.338284133 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.188286675 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3173575463 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4257980413 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2665223408 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.986390895 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.816179333 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.547089991 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1565208896 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3889683316 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.407320925 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1853270344 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4118456678 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1206428362 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3869855022 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.633339388 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2887343855 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2443830959 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2102470674 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.26129126 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3244714099 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3247473742 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2791859140 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3546026756 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1384892910 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3577595129 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1702906519 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1333359256 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3869464095 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3398383696 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.339958210 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.60283774 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3726533813 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2755019350 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.302087950 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3706434009 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.615969264 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1836455790 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2552612504 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2500690128 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1661046728 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3370139286 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3999122193 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2724351030 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.368075106 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3575550680 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4045930709 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1713128326 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2025803482 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.216455615 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.256689453 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.747861372 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1720816448 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3398282987 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1005253387 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3159636258 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2797447449 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1978241586 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2046556247 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.221281956 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.991055269 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2460369720 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.179371644 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3189867081 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3647730267 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1678341932 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1098830865 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1350844634 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.627262061 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3121061874 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3223755567 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.272631897 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3414184368 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.767877438 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2167627383 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.221261605 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1558497699 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3625575126 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2645629908 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3111365744 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.52168535 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1989997639 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3311462442 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3788253105 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1575468724 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2519784892 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3814821880 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3334071096 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1758861696 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2827089319 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1041033423 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1367946063 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.159579650 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1642206627 |
| /workspace/coverage/default/0.sram_ctrl_executable.82002156 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.1525736540 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1916892592 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.1155029313 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1966614891 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2427801340 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2372715898 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.2840333741 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3537985760 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2388772502 |
| /workspace/coverage/default/0.sram_ctrl_smoke.1000792387 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.882137392 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2856020054 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2670162818 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2929532687 |
| /workspace/coverage/default/1.sram_ctrl_bijection.980265039 |
| /workspace/coverage/default/1.sram_ctrl_executable.3510742673 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1630881212 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3517898838 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1634448829 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3079009344 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.60806749 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3685155164 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.93701407 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2594714624 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3629353683 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.4292333092 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2898281171 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2779941782 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.640194804 |
| /workspace/coverage/default/10.sram_ctrl_bijection.3205704778 |
| /workspace/coverage/default/10.sram_ctrl_executable.2079012638 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.127670029 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3751017585 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2887032512 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3009403530 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.4116125977 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.1274169952 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2181098672 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1113184735 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3780548426 |
| /workspace/coverage/default/10.sram_ctrl_smoke.1853954450 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.934807318 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1211053392 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4152736960 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2459476931 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.3072758978 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2139374918 |
| /workspace/coverage/default/11.sram_ctrl_executable.1976804260 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.3656645983 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2340977641 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.249175881 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.767197773 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1059508869 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2439664136 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2920622888 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.3741776783 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2461069068 |
| /workspace/coverage/default/11.sram_ctrl_smoke.486909441 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.434902016 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1566003951 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3607333584 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2592946121 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.4211100053 |
| /workspace/coverage/default/12.sram_ctrl_bijection.357851183 |
| /workspace/coverage/default/12.sram_ctrl_executable.3135641010 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.2941856330 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3109683206 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.150020753 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.1540469058 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3195450950 |
| /workspace/coverage/default/12.sram_ctrl_regwen.1069546430 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3370913511 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.4053616679 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2463370154 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1530783952 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1108976490 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2246751586 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.1035116072 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2226373337 |
| /workspace/coverage/default/13.sram_ctrl_executable.2827505436 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.4207114077 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.952531825 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2448864123 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3904850127 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.2659766756 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.4255604383 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.83600078 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.3197838449 |
| /workspace/coverage/default/13.sram_ctrl_regwen.517282352 |
| /workspace/coverage/default/13.sram_ctrl_smoke.4281181551 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2857653995 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2587493544 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1884948894 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.371794152 |
| /workspace/coverage/default/14.sram_ctrl_bijection.3630774666 |
| /workspace/coverage/default/14.sram_ctrl_executable.3075616112 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1525829346 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.3065821621 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4242917417 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1925453149 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.1394718584 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.4107462750 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.947211269 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.4206162798 |
| /workspace/coverage/default/14.sram_ctrl_regwen.392363745 |
| /workspace/coverage/default/14.sram_ctrl_smoke.2850626027 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.1012936926 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2933259940 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1740111257 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.268158920 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1513511767 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.3672952433 |
| /workspace/coverage/default/15.sram_ctrl_bijection.946440314 |
| /workspace/coverage/default/15.sram_ctrl_executable.1830378154 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.3058753575 |
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| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3000885149 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1217345407 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1327182702 |
| /workspace/coverage/default/48.sram_ctrl_executable.2182451092 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.3539419832 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.500826387 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.269715395 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.347263340 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.583099388 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3965375353 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.542424460 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2205081088 |
| /workspace/coverage/default/48.sram_ctrl_smoke.936452860 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.986046454 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1276138001 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3248821665 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.327841503 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3582198522 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1694993377 |
| /workspace/coverage/default/49.sram_ctrl_bijection.439204725 |
| /workspace/coverage/default/49.sram_ctrl_executable.981090954 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4096816135 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2121761106 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2224160181 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3823774537 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.1809700891 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.2654632247 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3828736259 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1816883328 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3251081914 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2760762849 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4074711735 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.406309021 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1747820904 |
| /workspace/coverage/default/5.sram_ctrl_executable.703135347 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.272928006 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2521162775 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3491678904 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2930525 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.4088804139 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2356427201 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2145159856 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2130580445 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3803252451 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1641554998 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.3873941815 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1249812887 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.765048553 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3948926452 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.394283625 |
| /workspace/coverage/default/6.sram_ctrl_bijection.2747324802 |
| /workspace/coverage/default/6.sram_ctrl_executable.2450283437 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2049134810 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.928246745 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1525427550 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.424959834 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1810884084 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2800391137 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3393459017 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.658050762 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3750116879 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3440528788 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2500521035 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.163370650 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.248483440 |
| /workspace/coverage/default/7.sram_ctrl_executable.562141915 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.3425936986 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2261970772 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.860290603 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.299344843 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.439955261 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.4009953617 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3294772265 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.950703795 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3885568700 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1004355598 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3476711582 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3408553173 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2609140742 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1531710506 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.2538964248 |
| /workspace/coverage/default/8.sram_ctrl_executable.1427842287 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.643739814 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1863111977 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.4054028076 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.796289779 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2918015520 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2363415871 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2294466863 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2591115619 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2396634901 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2722862076 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.3039559964 |
| /workspace/coverage/default/9.sram_ctrl_bijection.1612268537 |
| /workspace/coverage/default/9.sram_ctrl_executable.3146124160 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3558387645 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.1091764462 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.432590706 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3544930925 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.4269173552 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1237526367 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1033964752 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1490123259 |
| /workspace/coverage/default/9.sram_ctrl_regwen.997293620 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.48956588 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3441104378 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3732744454 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.1901451854 |
|
|
Dec 27 12:59:56 PM PST 23 |
Dec 27 01:00:02 PM PST 23 |
63774419 ps |
| T2 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.4230050257 |
|
|
Dec 27 01:00:27 PM PST 23 |
Dec 27 01:00:37 PM PST 23 |
256452246 ps |
| T3 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2880396405 |
|
|
Dec 27 01:00:39 PM PST 23 |
Dec 27 01:26:29 PM PST 23 |
27409497733 ps |
| T4 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2995364681 |
|
|
Dec 27 01:00:19 PM PST 23 |
Dec 27 01:18:43 PM PST 23 |
6524999931 ps |
| T5 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1493231537 |
|
|
Dec 27 12:59:04 PM PST 23 |
Dec 27 12:59:14 PM PST 23 |
870935968 ps |
| T6 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2705326735 |
|
|
Dec 27 12:59:13 PM PST 23 |
Dec 27 02:28:26 PM PST 23 |
2067627860 ps |
| T11 |
/workspace/coverage/default/11.sram_ctrl_smoke.486909441 |
|
|
Dec 27 12:59:43 PM PST 23 |
Dec 27 01:00:01 PM PST 23 |
249133667 ps |
| T7 |
/workspace/coverage/default/9.sram_ctrl_bijection.1612268537 |
|
|
Dec 27 12:59:33 PM PST 23 |
Dec 27 01:00:00 PM PST 23 |
314222587 ps |
| T12 |
/workspace/coverage/default/4.sram_ctrl_partial_access.675084280 |
|
|
Dec 27 12:59:05 PM PST 23 |
Dec 27 01:00:46 PM PST 23 |
1724329502 ps |
| T13 |
/workspace/coverage/default/1.sram_ctrl_smoke.3629353683 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 01:00:02 PM PST 23 |
1087956863 ps |
| T17 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2617314141 |
|
|
Dec 27 01:00:15 PM PST 23 |
Dec 27 01:00:20 PM PST 23 |
201774530 ps |
| T32 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.738440927 |
|
|
Dec 27 12:59:31 PM PST 23 |
Dec 27 12:59:39 PM PST 23 |
169844829 ps |
| T16 |
/workspace/coverage/default/32.sram_ctrl_bijection.539115953 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:02:04 PM PST 23 |
10394342918 ps |
| T18 |
/workspace/coverage/default/47.sram_ctrl_smoke.2711571837 |
|
|
Dec 27 01:00:40 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
307487719 ps |
| T14 |
/workspace/coverage/default/1.sram_ctrl_stress_all.4292333092 |
|
|
Dec 27 12:59:11 PM PST 23 |
Dec 27 01:15:52 PM PST 23 |
114786593061 ps |
| T92 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.4039336514 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:00:23 PM PST 23 |
39641993 ps |
| T19 |
/workspace/coverage/default/29.sram_ctrl_executable.1075661505 |
|
|
Dec 27 01:00:03 PM PST 23 |
Dec 27 01:01:59 PM PST 23 |
2608018976 ps |
| T57 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2918015520 |
|
|
Dec 27 12:59:34 PM PST 23 |
Dec 27 01:07:16 PM PST 23 |
18529178438 ps |
| T15 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1211053392 |
|
|
Dec 27 12:59:40 PM PST 23 |
Dec 27 01:47:36 PM PST 23 |
6376159315 ps |
| T94 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1945425097 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:02:28 PM PST 23 |
927678264 ps |
| T126 |
/workspace/coverage/default/14.sram_ctrl_bijection.3630774666 |
|
|
Dec 27 12:59:54 PM PST 23 |
Dec 27 01:00:31 PM PST 23 |
4435613105 ps |
| T33 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2363415871 |
|
|
Dec 27 12:59:42 PM PST 23 |
Dec 27 12:59:47 PM PST 23 |
96498796 ps |
| T113 |
/workspace/coverage/default/0.sram_ctrl_executable.82002156 |
|
|
Dec 27 12:59:03 PM PST 23 |
Dec 27 01:12:02 PM PST 23 |
4879203838 ps |
| T127 |
/workspace/coverage/default/15.sram_ctrl_bijection.946440314 |
|
|
Dec 27 01:00:02 PM PST 23 |
Dec 27 01:01:17 PM PST 23 |
3665184728 ps |
| T34 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3705523073 |
|
|
Dec 27 01:00:20 PM PST 23 |
Dec 27 01:00:24 PM PST 23 |
45897425 ps |
| T58 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2200923267 |
|
|
Dec 27 01:00:36 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
402714391 ps |
| T59 |
/workspace/coverage/default/21.sram_ctrl_executable.3901197438 |
|
|
Dec 27 01:00:20 PM PST 23 |
Dec 27 01:07:36 PM PST 23 |
30604206871 ps |
| T128 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3000885149 |
|
|
Dec 27 01:00:58 PM PST 23 |
Dec 27 01:03:15 PM PST 23 |
306171000 ps |
| T20 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3495642310 |
|
|
Dec 27 01:00:27 PM PST 23 |
Dec 27 01:10:51 PM PST 23 |
12926218728 ps |
| T21 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1118910528 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:00:36 PM PST 23 |
32849000 ps |
| T129 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.693135350 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:01:23 PM PST 23 |
210151731 ps |
| T130 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2298810866 |
|
|
Dec 27 01:00:42 PM PST 23 |
Dec 27 01:23:21 PM PST 23 |
13733019137 ps |
| T22 |
/workspace/coverage/default/34.sram_ctrl_alert_test.374564045 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:00:46 PM PST 23 |
21181004 ps |
| T23 |
/workspace/coverage/default/0.sram_ctrl_alert_test.159579650 |
|
|
Dec 27 12:59:11 PM PST 23 |
Dec 27 12:59:22 PM PST 23 |
81187960 ps |
| T131 |
/workspace/coverage/default/7.sram_ctrl_smoke.1004355598 |
|
|
Dec 27 12:59:19 PM PST 23 |
Dec 27 12:59:42 PM PST 23 |
220508810 ps |
| T119 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.4115878755 |
|
|
Dec 27 12:59:11 PM PST 23 |
Dec 27 01:13:47 PM PST 23 |
11521739727 ps |
| T83 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3350475270 |
|
|
Dec 27 01:02:16 PM PST 23 |
Dec 27 01:05:21 PM PST 23 |
2114324227 ps |
| T24 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3921484464 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:00:34 PM PST 23 |
15586076 ps |
| T8 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4042367563 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:00:53 PM PST 23 |
542550935 ps |
| T132 |
/workspace/coverage/default/10.sram_ctrl_alert_test.3737618633 |
|
|
Dec 27 12:59:37 PM PST 23 |
Dec 27 12:59:43 PM PST 23 |
19580171 ps |
| T112 |
/workspace/coverage/default/36.sram_ctrl_executable.759035557 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:13:29 PM PST 23 |
3966340371 ps |
| T111 |
/workspace/coverage/default/6.sram_ctrl_executable.2450283437 |
|
|
Dec 27 12:59:37 PM PST 23 |
Dec 27 01:07:47 PM PST 23 |
1529004380 ps |
| T37 |
/workspace/coverage/default/14.sram_ctrl_executable.3075616112 |
|
|
Dec 27 12:59:51 PM PST 23 |
Dec 27 01:17:10 PM PST 23 |
49687181960 ps |
| T63 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2018420613 |
|
|
Dec 27 01:00:08 PM PST 23 |
Dec 27 01:04:26 PM PST 23 |
1965607108 ps |
| T133 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1071226513 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:02:17 PM PST 23 |
288355996 ps |
| T9 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3330863752 |
|
|
Dec 27 01:00:44 PM PST 23 |
Dec 27 01:35:46 PM PST 23 |
7974432998 ps |
| T10 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3558387645 |
|
|
Dec 27 12:59:33 PM PST 23 |
Dec 27 12:59:47 PM PST 23 |
2179029417 ps |
| T134 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2356427201 |
|
|
Dec 27 12:59:22 PM PST 23 |
Dec 27 12:59:43 PM PST 23 |
190642850 ps |
| T135 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1139898344 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:00:35 PM PST 23 |
14631991 ps |
| T30 |
/workspace/coverage/default/36.sram_ctrl_stress_all.648453175 |
|
|
Dec 27 01:00:45 PM PST 23 |
Dec 27 01:47:04 PM PST 23 |
32492345303 ps |
| T136 |
/workspace/coverage/default/22.sram_ctrl_smoke.1360945513 |
|
|
Dec 27 01:00:50 PM PST 23 |
Dec 27 01:02:33 PM PST 23 |
153373288 ps |
| T137 |
/workspace/coverage/default/20.sram_ctrl_bijection.2619826912 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:01:28 PM PST 23 |
6121225837 ps |
| T138 |
/workspace/coverage/default/33.sram_ctrl_executable.1809849673 |
|
|
Dec 27 01:00:25 PM PST 23 |
Dec 27 01:01:04 PM PST 23 |
1076392652 ps |
| T139 |
/workspace/coverage/default/3.sram_ctrl_smoke.2317791105 |
|
|
Dec 27 12:59:21 PM PST 23 |
Dec 27 12:59:33 PM PST 23 |
141773938 ps |
| T140 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.643739814 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 12:59:43 PM PST 23 |
76419391 ps |
| T84 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.92814167 |
|
|
Dec 27 01:00:18 PM PST 23 |
Dec 27 01:04:27 PM PST 23 |
2611121468 ps |
| T141 |
/workspace/coverage/default/16.sram_ctrl_smoke.2741535345 |
|
|
Dec 27 12:59:45 PM PST 23 |
Dec 27 12:59:55 PM PST 23 |
149254297 ps |
| T142 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1950198494 |
|
|
Dec 27 01:00:46 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
80766536 ps |
| T85 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.374503944 |
|
|
Dec 27 12:59:47 PM PST 23 |
Dec 27 01:06:18 PM PST 23 |
5332977207 ps |
| T86 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.276650211 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:03:44 PM PST 23 |
2123500042 ps |
| T143 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4088804139 |
|
|
Dec 27 12:59:22 PM PST 23 |
Dec 27 01:12:30 PM PST 23 |
6904493096 ps |
| T144 |
/workspace/coverage/default/25.sram_ctrl_bijection.4065861110 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:01:33 PM PST 23 |
811019380 ps |
| T27 |
/workspace/coverage/default/19.sram_ctrl_regwen.2350434644 |
|
|
Dec 27 12:59:55 PM PST 23 |
Dec 27 01:23:57 PM PST 23 |
91819988040 ps |
| T145 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1914709173 |
|
|
Dec 27 01:00:40 PM PST 23 |
Dec 27 01:01:14 PM PST 23 |
1779025960 ps |
| T146 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.4191279553 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:00:45 PM PST 23 |
26422339 ps |
| T147 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3072758978 |
|
|
Dec 27 12:59:36 PM PST 23 |
Dec 27 12:59:42 PM PST 23 |
53745511 ps |
| T110 |
/workspace/coverage/default/48.sram_ctrl_regwen.2205081088 |
|
|
Dec 27 01:00:52 PM PST 23 |
Dec 27 01:23:59 PM PST 23 |
59810390264 ps |
| T148 |
/workspace/coverage/default/24.sram_ctrl_partial_access.939239373 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
893153838 ps |
| T149 |
/workspace/coverage/default/22.sram_ctrl_executable.3517475439 |
|
|
Dec 27 01:00:16 PM PST 23 |
Dec 27 01:01:19 PM PST 23 |
2248470169 ps |
| T31 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1178824523 |
|
|
Dec 27 01:00:01 PM PST 23 |
Dec 27 01:47:24 PM PST 23 |
1271977905 ps |
| T95 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.93701407 |
|
|
Dec 27 12:59:18 PM PST 23 |
Dec 27 12:59:29 PM PST 23 |
95376941 ps |
| T96 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1096437771 |
|
|
Dec 27 12:59:09 PM PST 23 |
Dec 27 01:00:26 PM PST 23 |
154886380 ps |
| T97 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.4229073898 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:00:50 PM PST 23 |
1333673896 ps |
| T98 |
/workspace/coverage/default/17.sram_ctrl_stress_all.4284255593 |
|
|
Dec 27 01:00:12 PM PST 23 |
Dec 27 02:01:51 PM PST 23 |
446055583454 ps |
| T40 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3476711582 |
|
|
Dec 27 12:59:40 PM PST 23 |
Dec 27 01:13:57 PM PST 23 |
272689380 ps |
| T99 |
/workspace/coverage/default/21.sram_ctrl_partial_access.184663317 |
|
|
Dec 27 01:00:15 PM PST 23 |
Dec 27 01:00:25 PM PST 23 |
115470130 ps |
| T41 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1969605863 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:31:01 PM PST 23 |
933547757 ps |
| T150 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2587678129 |
|
|
Dec 27 01:00:08 PM PST 23 |
Dec 27 01:00:10 PM PST 23 |
46455032 ps |
| T87 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1245373300 |
|
|
Dec 27 01:00:46 PM PST 23 |
Dec 27 01:04:54 PM PST 23 |
3333677548 ps |
| T151 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3112077520 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:23:19 PM PST 23 |
12998769049 ps |
| T42 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2626096144 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:54:28 PM PST 23 |
1164632785 ps |
| T124 |
/workspace/coverage/default/2.sram_ctrl_executable.3963577879 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 01:12:37 PM PST 23 |
1783003809 ps |
| T28 |
/workspace/coverage/default/12.sram_ctrl_regwen.1069546430 |
|
|
Dec 27 12:59:40 PM PST 23 |
Dec 27 01:07:31 PM PST 23 |
9773620331 ps |
| T152 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.269715395 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:00:47 PM PST 23 |
238159648 ps |
| T153 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3651428605 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:00:45 PM PST 23 |
403143771 ps |
| T88 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3867307886 |
|
|
Dec 27 01:00:08 PM PST 23 |
Dec 27 01:04:01 PM PST 23 |
2378452908 ps |
| T154 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2252040480 |
|
|
Dec 27 01:00:13 PM PST 23 |
Dec 27 01:01:00 PM PST 23 |
115298978 ps |
| T155 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1077675800 |
|
|
Dec 27 01:00:12 PM PST 23 |
Dec 27 01:00:22 PM PST 23 |
224929050 ps |
| T89 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3820866075 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:04:37 PM PST 23 |
5182174881 ps |
| T38 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3223747714 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
694238979 ps |
| T78 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2141481708 |
|
|
Dec 27 12:36:42 PM PST 23 |
Dec 27 12:37:12 PM PST 23 |
16159982 ps |
| T79 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2998515390 |
|
|
Dec 27 12:36:51 PM PST 23 |
Dec 27 12:37:18 PM PST 23 |
18923312 ps |
| T47 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2887343855 |
|
|
Dec 27 12:36:39 PM PST 23 |
Dec 27 12:37:09 PM PST 23 |
16774630 ps |
| T43 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1853270344 |
|
|
Dec 27 12:36:25 PM PST 23 |
Dec 27 12:36:49 PM PST 23 |
58737829 ps |
| T48 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3925753796 |
|
|
Dec 27 12:36:18 PM PST 23 |
Dec 27 12:36:52 PM PST 23 |
55140378 ps |
| T49 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.895947800 |
|
|
Dec 27 12:37:02 PM PST 23 |
Dec 27 12:37:30 PM PST 23 |
511637872 ps |
| T44 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2724351030 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:37:01 PM PST 23 |
139546537 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.221261605 |
|
|
Dec 27 12:36:45 PM PST 23 |
Dec 27 12:37:15 PM PST 23 |
23751277 ps |
| T39 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2911532892 |
|
|
Dec 27 12:36:26 PM PST 23 |
Dec 27 12:36:50 PM PST 23 |
258776656 ps |
| T45 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4267703376 |
|
|
Dec 27 12:36:34 PM PST 23 |
Dec 27 12:37:04 PM PST 23 |
271099364 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2046556247 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:48 PM PST 23 |
1807032302 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1678341932 |
|
|
Dec 27 12:36:52 PM PST 23 |
Dec 27 12:37:19 PM PST 23 |
63139142 ps |
| T46 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3814821880 |
|
|
Dec 27 12:39:01 PM PST 23 |
Dec 27 12:39:20 PM PST 23 |
33650326 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.627262061 |
|
|
Dec 27 12:36:26 PM PST 23 |
Dec 27 12:36:50 PM PST 23 |
122137924 ps |
| T50 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.922183762 |
|
|
Dec 27 12:36:13 PM PST 23 |
Dec 27 12:36:38 PM PST 23 |
404686379 ps |
| T51 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1702906519 |
|
|
Dec 27 12:36:19 PM PST 23 |
Dec 27 12:36:40 PM PST 23 |
11370841 ps |
| T52 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2025803482 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:44 PM PST 23 |
16552065 ps |
| T53 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1041033423 |
|
|
Dec 27 12:36:28 PM PST 23 |
Dec 27 12:36:54 PM PST 23 |
128835090 ps |
| T54 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2230381657 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:35 PM PST 23 |
39097887 ps |
| T55 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3042386443 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:38 PM PST 23 |
371493929 ps |
| T56 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3484876981 |
|
|
Dec 27 12:38:56 PM PST 23 |
Dec 27 12:39:11 PM PST 23 |
22597929 ps |
| T62 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1633075164 |
|
|
Dec 27 12:39:18 PM PST 23 |
Dec 27 12:39:45 PM PST 23 |
30515040 ps |
| T60 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.216455615 |
|
|
Dec 27 12:36:30 PM PST 23 |
Dec 27 12:37:01 PM PST 23 |
470405976 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.767877438 |
|
|
Dec 27 12:36:46 PM PST 23 |
Dec 27 12:37:16 PM PST 23 |
544258152 ps |
| T101 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1350844634 |
|
|
Dec 27 12:36:36 PM PST 23 |
Dec 27 12:37:06 PM PST 23 |
191184421 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2791859140 |
|
|
Dec 27 12:36:54 PM PST 23 |
Dec 27 12:37:20 PM PST 23 |
14968648 ps |
| T156 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.575803031 |
|
|
Dec 27 12:37:35 PM PST 23 |
Dec 27 12:37:50 PM PST 23 |
42230126 ps |
| T102 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.816179333 |
|
|
Dec 27 12:36:59 PM PST 23 |
Dec 27 12:37:26 PM PST 23 |
185801975 ps |
| T157 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.272631897 |
|
|
Dec 27 12:36:56 PM PST 23 |
Dec 27 12:37:22 PM PST 23 |
26813310 ps |
| T158 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1575468724 |
|
|
Dec 27 12:36:27 PM PST 23 |
Dec 27 12:36:52 PM PST 23 |
404956991 ps |
| T159 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2557553233 |
|
|
Dec 27 12:39:00 PM PST 23 |
Dec 27 12:39:27 PM PST 23 |
233571179 ps |
| T160 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1661046728 |
|
|
Dec 27 12:36:42 PM PST 23 |
Dec 27 12:37:16 PM PST 23 |
12359178 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3311462442 |
|
|
Dec 27 12:36:29 PM PST 23 |
Dec 27 12:36:56 PM PST 23 |
858276505 ps |
| T161 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.60283774 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
116127094 ps |
| T162 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4045930709 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:38 PM PST 23 |
25511827 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1144882841 |
|
|
Dec 27 12:37:12 PM PST 23 |
Dec 27 12:37:37 PM PST 23 |
1295542503 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2519784892 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:37:00 PM PST 23 |
303399493 ps |
| T65 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3247473742 |
|
|
Dec 27 12:36:57 PM PST 23 |
Dec 27 12:37:32 PM PST 23 |
1535358950 ps |
| T163 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1005253387 |
|
|
Dec 27 12:36:27 PM PST 23 |
Dec 27 12:36:51 PM PST 23 |
149442844 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3370139286 |
|
|
Dec 27 12:36:04 PM PST 23 |
Dec 27 12:36:27 PM PST 23 |
761218225 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4257980413 |
|
|
Dec 27 12:36:36 PM PST 23 |
Dec 27 12:37:18 PM PST 23 |
492098223 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.581828237 |
|
|
Dec 27 12:36:26 PM PST 23 |
Dec 27 12:36:50 PM PST 23 |
297415360 ps |
| T164 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.986390895 |
|
|
Dec 27 12:36:24 PM PST 23 |
Dec 27 12:36:48 PM PST 23 |
34562357 ps |
| T165 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1206428362 |
|
|
Dec 27 12:36:40 PM PST 23 |
Dec 27 12:37:11 PM PST 23 |
44376324 ps |
| T166 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.256689453 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
45523567 ps |
| T67 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3768501880 |
|
|
Dec 27 12:36:29 PM PST 23 |
Dec 27 12:37:03 PM PST 23 |
6029199726 ps |
| T167 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2235257773 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:37:02 PM PST 23 |
268694929 ps |
| T168 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3244714099 |
|
|
Dec 27 12:36:30 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
28486877 ps |
| T169 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.339958210 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:36 PM PST 23 |
26366852 ps |
| T170 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.26129126 |
|
|
Dec 27 12:36:35 PM PST 23 |
Dec 27 12:37:04 PM PST 23 |
67819170 ps |
| T171 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3999122193 |
|
|
Dec 27 12:36:20 PM PST 23 |
Dec 27 12:36:42 PM PST 23 |
48109317 ps |
| T172 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3852121063 |
|
|
Dec 27 12:37:15 PM PST 23 |
Dec 27 12:37:36 PM PST 23 |
12869374 ps |
| T173 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4118456678 |
|
|
Dec 27 12:37:03 PM PST 23 |
Dec 27 12:37:29 PM PST 23 |
117697638 ps |
| T174 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2827089319 |
|
|
Dec 27 12:36:29 PM PST 23 |
Dec 27 12:36:53 PM PST 23 |
61018366 ps |
| T175 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.615969264 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:44 PM PST 23 |
22702447 ps |
| T176 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3398383696 |
|
|
Dec 27 12:36:40 PM PST 23 |
Dec 27 12:37:14 PM PST 23 |
482539003 ps |
| T177 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1429828265 |
|
|
Dec 27 12:36:23 PM PST 23 |
Dec 27 12:36:46 PM PST 23 |
526842419 ps |
| T178 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1565208896 |
|
|
Dec 27 12:36:49 PM PST 23 |
Dec 27 12:37:17 PM PST 23 |
12642827 ps |
| T179 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3869464095 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:44 PM PST 23 |
51128930 ps |
| T180 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1830177212 |
|
|
Dec 27 12:36:16 PM PST 23 |
Dec 27 12:36:39 PM PST 23 |
318922903 ps |
| T181 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1098830865 |
|
|
Dec 27 12:36:19 PM PST 23 |
Dec 27 12:36:43 PM PST 23 |
2705151823 ps |
| T182 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.52168535 |
|
|
Dec 27 12:39:04 PM PST 23 |
Dec 27 12:39:21 PM PST 23 |
43154025 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3398282987 |
|
|
Dec 27 12:36:33 PM PST 23 |
Dec 27 12:37:00 PM PST 23 |
35324881 ps |
| T183 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.407320925 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:44 PM PST 23 |
18162960 ps |
| T184 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2552612504 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:38 PM PST 23 |
92501256 ps |
| T185 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3652708791 |
|
|
Dec 27 12:36:30 PM PST 23 |
Dec 27 12:36:54 PM PST 23 |
39095459 ps |
| T186 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1836455790 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:39 PM PST 23 |
175347323 ps |
| T187 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3159636258 |
|
|
Dec 27 12:36:51 PM PST 23 |
Dec 27 12:37:18 PM PST 23 |
13649532 ps |
| T188 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3783186930 |
|
|
Dec 27 12:36:26 PM PST 23 |
Dec 27 12:36:50 PM PST 23 |
28894855 ps |
| T189 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.221281956 |
|
|
Dec 27 12:36:50 PM PST 23 |
Dec 27 12:37:18 PM PST 23 |
22670133 ps |
| T190 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2755019350 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:57 PM PST 23 |
31510320 ps |
| T107 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3304046050 |
|
|
Dec 27 12:36:55 PM PST 23 |
Dec 27 12:37:23 PM PST 23 |
354282245 ps |
| T191 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1172084851 |
|
|
Dec 27 12:36:42 PM PST 23 |
Dec 27 12:37:14 PM PST 23 |
274417111 ps |
| T192 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3321546465 |
|
|
Dec 27 12:36:08 PM PST 23 |
Dec 27 12:36:30 PM PST 23 |
15850354 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.850451521 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:40 PM PST 23 |
824194819 ps |
| T74 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.302328971 |
|
|
Dec 27 12:37:12 PM PST 23 |
Dec 27 12:37:34 PM PST 23 |
82836096 ps |
| T193 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3512453980 |
|
|
Dec 27 12:37:02 PM PST 23 |
Dec 27 12:37:28 PM PST 23 |
16476038 ps |
| T194 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.50880245 |
|
|
Dec 27 12:36:08 PM PST 23 |
Dec 27 12:36:30 PM PST 23 |
38279456 ps |
| T195 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3467181007 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:38 PM PST 23 |
33047312 ps |
| T196 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.747861372 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:41 PM PST 23 |
118297833 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1978241586 |
|
|
Dec 27 12:36:44 PM PST 23 |
Dec 27 12:37:14 PM PST 23 |
41219270 ps |
| T197 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3575550680 |
|
|
Dec 27 12:36:08 PM PST 23 |
Dec 27 12:36:30 PM PST 23 |
443470459 ps |
| T198 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2443830959 |
|
|
Dec 27 12:36:50 PM PST 23 |
Dec 27 12:37:19 PM PST 23 |
113745277 ps |
| T199 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1713128326 |
|
|
Dec 27 12:36:29 PM PST 23 |
Dec 27 12:36:53 PM PST 23 |
28931994 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2360327123 |
|
|
Dec 27 12:36:25 PM PST 23 |
Dec 27 12:36:48 PM PST 23 |
171587741 ps |
| T200 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1989997639 |
|
|
Dec 27 12:36:05 PM PST 23 |
Dec 27 12:36:25 PM PST 23 |
16232309 ps |
| T201 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3173575463 |
|
|
Dec 27 12:36:25 PM PST 23 |
Dec 27 12:36:48 PM PST 23 |
13574485 ps |
| T202 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.533482156 |
|
|
Dec 27 12:36:17 PM PST 23 |
Dec 27 12:36:40 PM PST 23 |
102366724 ps |
| T203 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3334071096 |
|
|
Dec 27 12:38:58 PM PST 23 |
Dec 27 12:39:15 PM PST 23 |
72624270 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3111365744 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:46 PM PST 23 |
562921948 ps |
| T204 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3869855022 |
|
|
Dec 27 12:37:12 PM PST 23 |
Dec 27 12:37:34 PM PST 23 |
20420163 ps |
| T205 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3788253105 |
|
|
Dec 27 12:38:49 PM PST 23 |
Dec 27 12:39:00 PM PST 23 |
50421983 ps |
| T206 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.991055269 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:37:00 PM PST 23 |
451828641 ps |
| T207 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.179371644 |
|
|
Dec 27 12:36:14 PM PST 23 |
Dec 27 12:36:37 PM PST 23 |
89262061 ps |
| T208 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2460369720 |
|
|
Dec 27 12:36:23 PM PST 23 |
Dec 27 12:36:47 PM PST 23 |
74892827 ps |
| T209 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2186844031 |
|
|
Dec 27 12:36:41 PM PST 23 |
Dec 27 12:37:11 PM PST 23 |
21612152 ps |
| T210 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1737957900 |
|
|
Dec 27 12:36:24 PM PST 23 |
Dec 27 12:36:46 PM PST 23 |
17945043 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.368075106 |
|
|
Dec 27 12:36:36 PM PST 23 |
Dec 27 12:37:06 PM PST 23 |
16448901 ps |
| T211 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3223755567 |
|
|
Dec 27 12:36:35 PM PST 23 |
Dec 27 12:37:13 PM PST 23 |
1525624755 ps |
| T212 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.74404709 |
|
|
Dec 27 12:36:51 PM PST 23 |
Dec 27 12:37:18 PM PST 23 |
97428523 ps |
| T213 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3414184368 |
|
|
Dec 27 12:36:19 PM PST 23 |
Dec 27 12:36:42 PM PST 23 |
55584280 ps |
| T214 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1384892910 |
|
|
Dec 27 12:36:41 PM PST 23 |
Dec 27 12:37:11 PM PST 23 |
234100416 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1758861696 |
|
|
Dec 27 12:36:12 PM PST 23 |
Dec 27 12:36:36 PM PST 23 |
1101842615 ps |
| T215 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2957846524 |
|
|
Dec 27 12:36:53 PM PST 23 |
Dec 27 12:37:22 PM PST 23 |
146783081 ps |
| T216 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3889683316 |
|
|
Dec 27 12:36:37 PM PST 23 |
Dec 27 12:37:15 PM PST 23 |
446160738 ps |
| T217 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1333359256 |
|
|
Dec 27 12:36:21 PM PST 23 |
Dec 27 12:36:46 PM PST 23 |
260088655 ps |
| T218 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3706434009 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:59 PM PST 23 |
110222530 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1498748505 |
|
|
Dec 27 12:36:32 PM PST 23 |
Dec 27 12:37:01 PM PST 23 |
250208757 ps |
| T219 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1720816448 |
|
|
Dec 27 12:36:46 PM PST 23 |
Dec 27 12:37:16 PM PST 23 |
78756077 ps |
| T220 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2726435815 |
|
|
Dec 27 12:37:15 PM PST 23 |
Dec 27 12:37:38 PM PST 23 |
95238514 ps |
| T221 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3122286259 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:44 PM PST 23 |
35676222 ps |
| T222 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2500690128 |
|
|
Dec 27 12:36:35 PM PST 23 |
Dec 27 12:37:05 PM PST 23 |
30717866 ps |
| T223 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.338284133 |
|
|
Dec 27 12:37:04 PM PST 23 |
Dec 27 12:37:29 PM PST 23 |
306851129 ps |
| T224 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.633339388 |
|
|
Dec 27 12:36:32 PM PST 23 |
Dec 27 12:37:01 PM PST 23 |
842293713 ps |
| T225 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1558497699 |
|
|
Dec 27 12:36:57 PM PST 23 |
Dec 27 12:37:32 PM PST 23 |
439202262 ps |
| T226 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.547089991 |
|
|
Dec 27 12:37:07 PM PST 23 |
Dec 27 12:37:33 PM PST 23 |
66045663 ps |
| T227 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3647730267 |
|
|
Dec 27 12:36:35 PM PST 23 |
Dec 27 12:37:09 PM PST 23 |
1988574249 ps |
| T228 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2645629908 |
|
|
Dec 27 12:36:36 PM PST 23 |
Dec 27 12:37:10 PM PST 23 |
403437176 ps |
| T229 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3118396025 |
|
|
Dec 27 12:36:52 PM PST 23 |
Dec 27 12:37:19 PM PST 23 |
36006773 ps |
| T230 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4075276130 |
|
|
Dec 27 12:36:38 PM PST 23 |
Dec 27 12:37:09 PM PST 23 |
118727002 ps |
| T231 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3189867081 |
|
|
Dec 27 12:36:18 PM PST 23 |
Dec 27 12:36:39 PM PST 23 |
11189757 ps |
| T232 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3577595129 |
|
|
Dec 27 12:37:13 PM PST 23 |
Dec 27 12:37:36 PM PST 23 |
80054694 ps |
| T233 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2665223408 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
23661710 ps |
| T234 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3625575126 |
|
|
Dec 27 12:36:31 PM PST 23 |
Dec 27 12:36:58 PM PST 23 |
56188244 ps |
| T235 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1484221626 |
|
|
Dec 27 12:36:45 PM PST 23 |
Dec 27 12:37:14 PM PST 23 |
25457644 ps |
| T236 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2167627383 |
|
|
Dec 27 12:36:22 PM PST 23 |
Dec 27 12:36:46 PM PST 23 |
36539527 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2797447449 |
|
|
Dec 27 12:36:24 PM PST 23 |
Dec 27 12:36:47 PM PST 23 |
81138262 ps |
| T238 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3121061874 |
|
|
Dec 27 12:36:28 PM PST 23 |
Dec 27 12:36:52 PM PST 23 |
15579289 ps |
| T239 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3546026756 |
|
|
Dec 27 12:36:37 PM PST 23 |
Dec 27 12:37:10 PM PST 23 |
177200667 ps |
| T240 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2102470674 |
|
|
Dec 27 12:36:55 PM PST 23 |
Dec 27 12:37:23 PM PST 23 |
530728542 ps |
| T241 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.302087950 |
|
|
Dec 27 12:36:58 PM PST 23 |
Dec 27 12:37:26 PM PST 23 |
188621765 ps |
| T242 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2295337229 |
|
|
Dec 27 12:36:25 PM PST 23 |
Dec 27 12:36:49 PM PST 23 |
770645025 ps |
| T243 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.188286675 |
|
|
Dec 27 12:36:52 PM PST 23 |
Dec 27 12:37:19 PM PST 23 |
48644609 ps |
| T244 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3726533813 |
|
|
Dec 27 12:36:32 PM PST 23 |
Dec 27 12:37:04 PM PST 23 |
2086545562 ps |
| T90 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3393459017 |
|
|
Dec 27 12:59:11 PM PST 23 |
Dec 27 01:06:10 PM PST 23 |
23242633071 ps |
| T70 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3141080749 |
|
|
Dec 27 01:00:39 PM PST 23 |
Dec 27 01:04:40 PM PST 23 |
1385129538 ps |
| T245 |
/workspace/coverage/default/8.sram_ctrl_regwen.2294466863 |
|
|
Dec 27 12:59:32 PM PST 23 |
Dec 27 01:04:55 PM PST 23 |
4135381743 ps |
| T116 |
/workspace/coverage/default/32.sram_ctrl_regwen.1905481401 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:25:52 PM PST 23 |
17690164166 ps |
| T246 |
/workspace/coverage/default/6.sram_ctrl_smoke.3750116879 |
|
|
Dec 27 12:59:37 PM PST 23 |
Dec 27 01:00:07 PM PST 23 |
92175366 ps |
| T247 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1274169952 |
|
|
Dec 27 12:59:24 PM PST 23 |
Dec 27 01:01:17 PM PST 23 |
603514370 ps |
| T71 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1407758692 |
|
|
Dec 27 12:59:21 PM PST 23 |
Dec 27 01:15:44 PM PST 23 |
3294712543 ps |
| T248 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2511037075 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:00:28 PM PST 23 |
16953972 ps |
| T249 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.434902016 |
|
|
Dec 27 12:59:39 PM PST 23 |
Dec 27 01:20:03 PM PST 23 |
909455746 ps |
| T250 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1695761302 |
|
|
Dec 27 12:59:53 PM PST 23 |
Dec 27 01:15:03 PM PST 23 |
1237225696 ps |
| T100 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2901302141 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:00:53 PM PST 23 |
399079140 ps |
| T251 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4260031538 |
|
|
Dec 27 01:00:15 PM PST 23 |
Dec 27 01:00:18 PM PST 23 |
81335438 ps |
| T125 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3402989986 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
2096514800 ps |
| T252 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1733159966 |
|
|
Dec 27 12:59:44 PM PST 23 |
Dec 27 01:00:05 PM PST 23 |
7399424451 ps |
| T253 |
/workspace/coverage/default/36.sram_ctrl_partial_access.363023871 |
|
|
Dec 27 01:00:48 PM PST 23 |
Dec 27 01:01:10 PM PST 23 |
86750058 ps |
| T72 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3035514565 |
|
|
Dec 27 01:02:15 PM PST 23 |
Dec 27 01:02:22 PM PST 23 |
338328798 ps |
| T254 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3652733568 |
|
|
Dec 27 01:00:47 PM PST 23 |
Dec 27 01:04:14 PM PST 23 |
18404060905 ps |
| T255 |
/workspace/coverage/default/31.sram_ctrl_bijection.669317946 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
666627197 ps |
| T29 |
/workspace/coverage/default/0.sram_ctrl_regwen.3537985760 |
|
|
Dec 27 12:59:21 PM PST 23 |
Dec 27 01:07:29 PM PST 23 |
3602099063 ps |
| T256 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1490123259 |
|
|
Dec 27 12:59:32 PM PST 23 |
Dec 27 12:59:40 PM PST 23 |
35049028 ps |
| T257 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1505313214 |
|
|
Dec 27 01:00:20 PM PST 23 |
Dec 27 01:00:37 PM PST 23 |
290486356 ps |
| T258 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3622349447 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:04:28 PM PST 23 |
2660646482 ps |
| T259 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.658050762 |
|
|
Dec 27 12:59:22 PM PST 23 |
Dec 27 12:59:34 PM PST 23 |
180392129 ps |
| T260 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.159280357 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:06:13 PM PST 23 |
53708156304 ps |
| T261 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1683596090 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:01:58 PM PST 23 |
903623049 ps |
| T262 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2296860737 |
|
|
Dec 27 01:00:24 PM PST 23 |
Dec 27 01:00:52 PM PST 23 |
19394003793 ps |