Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	37125037	1			T1	114		T2	1250		T3	202339
triple_byte_access	2323922	1			T1	254		T3	4059		T4	3471
halfword_access	3486733	1			T1	444		T3	5976		T4	5033
byte_access	4657630	1			T1	720		T3	8126		T4	6975
zero_access	1171052	1			T1	414		T3	2030		T4	1650

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24334764

1

T1

838

T2

645

T3

111019

auto[1]

24429610

1

T1

1108

T2

605

T3

111511

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	18520524	1			T1	6		T2	645		T3	100947
auto[0]	triple_byte_access	1158467	1			T1	46		T3	2060		T4	1708
auto[0]	halfword_access	1739817	1			T1	126		T3	3022		T4	2493
auto[0]	byte_access	2327377	1			T1	347		T3	3952		T4	3480
auto[0]	zero_access	588579	1			T1	313		T3	1038		T4	803
auto[1]	word_access	18604513	1			T1	108		T2	605		T3	101392
auto[1]	triple_byte_access	1165455	1			T1	208		T3	1999		T4	1763
auto[1]	halfword_access	1746916	1			T1	318		T3	2954		T4	2540
auto[1]	byte_access	2330253	1			T1	373		T3	4174		T4	3495
auto[1]	zero_access	582473	1			T1	101		T3	992		T4	847