Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	141869010	1			T1	193648		T2	972136		T3	7152
instr_valid_dis	108283636	1			T2	940948		T3	7152		T7	669998
instr_en	23862149	1			T1	193648		T10	516488		T25	355468

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10151681	1			T1	102334		T2	302416		T10	64594
sram_ifetch_valid_disable	110417412	1			T1	80524		T2	367796		T3	7152
sram_ifetch_enable	21299917	1			T1	10790		T2	301924		T10	279462

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	141869010	1			T1	193648		T2	972136		T3	7152
hw_debug_en_valid_off	108316878	1			T1	77726		T2	286864		T3	7152
hw_debug_en_on	22034678	1			T1	94106		T2	484504		T10	194610

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110417412	1			T1	80524		T2	367796		T3	7152
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	96871736	1			T2	366202		T3	7152		T7	669998
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9597373	1			T1	80524		T10	172432		T25	208090
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4306232	1			T2	36728		T10	34848		T24	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1777792	1			T2	36728		T24	20000		T25	52918
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2061868	1			T10	34848		T25	16532		T67	178058
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3644266	1			T1	84316		T2	147256		T10	29746
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1265960	1			T2	147256		T25	45434		T42	2302
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1542354	1			T1	84316		T10	29746		T25	3528
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9558562	1			T1	2798		T2	137444		T10	52106
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4078401	1			T2	135850		T24	36126		T25	130892
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3894158	1			T1	2798		T10	52106		T25	60446

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9554646	1			T1	10790		T10	279462		T25	127318
lc_exec_en	8831850	1			T1	6992		T2	199804		T10	112758
valid_exec_dis	104003257	1			T1	77726		T2	445270		T3	7152
invalid_exec_dis	31451598	1			T1	113124		T2	604340		T10	344056