| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3588204671 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2829023554 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2724419795 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2823037004 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3392755584 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.541016010 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.674650616 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1312840109 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1910267834 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4043489605 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3488079778 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1812135033 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3050987150 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3140007067 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1674894688 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1074419557 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1099977191 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3597253668 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3975942118 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3450355673 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2515732193 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4036277924 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.748449485 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.969301239 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.240334738 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.993855239 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4066065804 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4180790500 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.479630120 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2938114980 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2722491855 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920586082 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3129303338 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.690198428 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1787190567 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1566149104 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2476707462 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1296085788 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2603324304 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3561141649 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3659863161 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4105466026 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2947925447 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3680631001 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1149756450 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1019853924 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3919535089 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3531652648 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.168685339 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3944985733 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3694459505 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.539431386 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1893117103 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2675408562 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4022102468 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.492331973 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1275262245 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1569873766 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2005465570 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3024387534 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.329050143 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2108630838 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.145352187 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4037541750 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2785595152 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2316166604 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4259003546 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.69606221 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3843702075 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.519739971 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.831299584 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1865040085 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.481195878 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.223126719 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1867249165 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1080324485 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2433694187 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3165833082 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1614302903 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.55977882 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.170173412 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.930008620 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.596845884 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2186139360 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.298805165 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3743472430 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4244428152 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1326890657 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1863992650 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2727530434 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3995693143 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.814616653 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.391556233 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1459471630 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1361027680 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1577173276 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2229218326 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3172853852 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3493559360 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1916259687 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3022756512 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.825318500 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3931937564 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4004724965 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2163562855 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.247609395 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2434325946 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3248991177 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2614583454 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2930174204 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4287674868 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.877293639 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4207087774 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2449111307 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1755059240 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3087420518 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1373131371 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3504181915 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2047000813 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2808820122 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.415862822 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2761696945 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2409288979 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3395350224 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.101185114 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2548046687 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2770576451 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1048563297 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.4293262957 |
| /workspace/coverage/default/0.sram_ctrl_bijection.3448969379 |
| /workspace/coverage/default/0.sram_ctrl_executable.1435293617 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.4229973046 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.660099182 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2293920660 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2650185854 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.4168844750 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2677777520 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1238158325 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1389646241 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4033011153 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3593149749 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.1006887066 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1040890572 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1388816872 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.473839597 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2549789558 |
| /workspace/coverage/default/1.sram_ctrl_bijection.1405813657 |
| /workspace/coverage/default/1.sram_ctrl_executable.3362856464 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.4161834270 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.3425288435 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.15618672 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.186007169 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.423202416 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2918583019 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.757039389 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.4162840941 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3511301313 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3435154900 |
| /workspace/coverage/default/1.sram_ctrl_smoke.2352603381 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.494724935 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2283333722 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2224825935 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2481217130 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3078210847 |
| /workspace/coverage/default/10.sram_ctrl_bijection.356561973 |
| /workspace/coverage/default/10.sram_ctrl_executable.2507833979 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.987354051 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.1376389751 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.596354225 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3826321342 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.233583276 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2702984877 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3326644068 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1929743386 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3657346978 |
| /workspace/coverage/default/10.sram_ctrl_smoke.191930690 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.453729626 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3599921417 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2268199406 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1985193415 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3732260799 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.156467639 |
| /workspace/coverage/default/11.sram_ctrl_bijection.775879939 |
| /workspace/coverage/default/11.sram_ctrl_executable.2197152282 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.879703162 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.4014866287 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1209369786 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.958471664 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.745052560 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3209310256 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984965878 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.506014243 |
| /workspace/coverage/default/11.sram_ctrl_regwen.442370164 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1658519114 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.3248402234 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2067481362 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1525322140 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3684938959 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2216341311 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1134446839 |
| /workspace/coverage/default/12.sram_ctrl_bijection.20502580 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.4178121583 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.362952677 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3573958537 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3605752032 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1191439822 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3483372712 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.340692291 |
| /workspace/coverage/default/12.sram_ctrl_regwen.4038600517 |
| /workspace/coverage/default/12.sram_ctrl_smoke.126349247 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3157032723 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1503297111 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.983686737 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1430563930 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1596180135 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.2171557168 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2662973184 |
| /workspace/coverage/default/13.sram_ctrl_executable.468635760 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.599144534 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1520219146 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2750691002 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.682680248 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.203776765 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.163010221 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1475469128 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1764852299 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2042260372 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1918965666 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.1946023500 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1621741809 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1794832807 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1477861940 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1063113892 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2128811229 |
| /workspace/coverage/default/14.sram_ctrl_bijection.502116547 |
| /workspace/coverage/default/14.sram_ctrl_executable.1275319957 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.1559893461 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3930298403 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3842787490 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.1583870076 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2351087259 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1208672567 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.807017757 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1239689306 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3076379482 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.1868296847 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2960941068 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2139093250 |
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| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3824128858 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3761433126 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1356584354 |
| /workspace/coverage/default/45.sram_ctrl_bijection.1202938567 |
| /workspace/coverage/default/45.sram_ctrl_executable.2709072097 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.201373674 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2513676800 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4039373600 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.1773823095 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.4261705864 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.2655772231 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3121123101 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2561776775 |
| /workspace/coverage/default/45.sram_ctrl_regwen.3883722766 |
| /workspace/coverage/default/45.sram_ctrl_smoke.256882565 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.230841145 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.440619912 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1170037777 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.624124285 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.4024635506 |
| /workspace/coverage/default/46.sram_ctrl_bijection.288673404 |
| /workspace/coverage/default/46.sram_ctrl_executable.2533681252 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1830628315 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1576321093 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.164797250 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.772993281 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3944815027 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.4102625355 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1611863829 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.251554250 |
| /workspace/coverage/default/46.sram_ctrl_regwen.470681480 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2372791144 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.219766180 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1279302739 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1475315521 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4029539358 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2830439415 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.634478104 |
| /workspace/coverage/default/47.sram_ctrl_bijection.583509510 |
| /workspace/coverage/default/47.sram_ctrl_executable.2191785577 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1619798781 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.427895424 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2020647531 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3614174433 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.1006409452 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3980505296 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3764037391 |
| /workspace/coverage/default/47.sram_ctrl_regwen.882916773 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2336320631 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.128168566 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2539527145 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.191750848 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1894487314 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.877290648 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.4096228691 |
| /workspace/coverage/default/48.sram_ctrl_bijection.80800893 |
| /workspace/coverage/default/48.sram_ctrl_executable.807176064 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2203586159 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1801431166 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.80978485 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.3940483916 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.497611157 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.4007442763 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3380666514 |
| /workspace/coverage/default/48.sram_ctrl_regwen.623398444 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1192927826 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.153626887 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1169996248 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1284775280 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.85822944 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2086849548 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1696193283 |
| /workspace/coverage/default/49.sram_ctrl_bijection.2301183738 |
| /workspace/coverage/default/49.sram_ctrl_executable.1817994580 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3804212943 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.367335262 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.139531283 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.870240028 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1414523064 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3853439717 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4010552114 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.4244349054 |
| /workspace/coverage/default/49.sram_ctrl_regwen.946769254 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1978246587 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.1034064294 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2403665649 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2624669784 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3565046141 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1604820393 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2822271907 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3282563570 |
| /workspace/coverage/default/5.sram_ctrl_executable.1205539552 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2905617834 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.3686877112 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3796684246 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.515919855 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.3867716749 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.3698922274 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.844817065 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1950783444 |
| /workspace/coverage/default/5.sram_ctrl_regwen.35482735 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1045810678 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1671965238 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.541051629 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.517277876 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4058253296 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3205014698 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.2057383829 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1539211477 |
| /workspace/coverage/default/6.sram_ctrl_executable.1255682211 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.1767700257 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.3543035812 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1702252283 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2486559714 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.4256970429 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.3798767563 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3604041687 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2383950132 |
| /workspace/coverage/default/6.sram_ctrl_regwen.192619728 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2703342506 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.2897790236 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2744747308 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3975898630 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3198217221 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.29946152 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.1414461645 |
| /workspace/coverage/default/7.sram_ctrl_bijection.637968566 |
| /workspace/coverage/default/7.sram_ctrl_executable.690518417 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2160795458 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3582488688 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3154488533 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3103444157 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3811178444 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.263517226 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2555781167 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1700319369 |
| /workspace/coverage/default/7.sram_ctrl_regwen.831150437 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3110754913 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.303641521 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3733616032 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1204693169 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2066687694 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.922506618 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2534182655 |
| /workspace/coverage/default/8.sram_ctrl_executable.3710453044 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.217005659 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.4061014589 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.439143892 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.623159783 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.200468374 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3775353300 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1820084117 |
| /workspace/coverage/default/8.sram_ctrl_regwen.3542879455 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3068215173 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.328164455 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2175093898 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3564283464 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.433267040 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1628944376 |
| /workspace/coverage/default/9.sram_ctrl_bijection.2444881663 |
| /workspace/coverage/default/9.sram_ctrl_executable.2025144509 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.1865712435 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2592058158 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2212354777 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.4000459824 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.4285538238 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3558051565 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3419953409 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2839654511 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1559221817 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1120409334 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3589887969 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.851762509 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3830589175 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/47.sram_ctrl_regwen.882916773 |
|
|
Jan 03 12:53:42 PM PST 24 |
Jan 03 12:59:07 PM PST 24 |
7453737363 ps |
| T2 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3407339284 |
|
|
Jan 03 12:53:15 PM PST 24 |
Jan 03 01:30:13 PM PST 24 |
147091739964 ps |
| T3 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3647987214 |
|
|
Jan 03 12:52:51 PM PST 24 |
Jan 03 12:54:31 PM PST 24 |
1720106598 ps |
| T7 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1368703467 |
|
|
Jan 03 12:53:09 PM PST 24 |
Jan 03 01:00:17 PM PST 24 |
4021638395 ps |
| T8 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.163111859 |
|
|
Jan 03 12:53:41 PM PST 24 |
Jan 03 12:54:50 PM PST 24 |
246847276 ps |
| T9 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4168844750 |
|
|
Jan 03 12:50:52 PM PST 24 |
Jan 03 12:56:49 PM PST 24 |
1637030754 ps |
| T10 |
/workspace/coverage/default/26.sram_ctrl_regwen.632727156 |
|
|
Jan 03 12:53:37 PM PST 24 |
Jan 03 01:14:45 PM PST 24 |
15925093984 ps |
| T4 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1204693169 |
|
|
Jan 03 12:51:43 PM PST 24 |
Jan 03 12:52:39 PM PST 24 |
301027519 ps |
| T11 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2286508364 |
|
|
Jan 03 12:52:49 PM PST 24 |
Jan 03 01:44:27 PM PST 24 |
2330259727 ps |
| T12 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4001321307 |
|
|
Jan 03 12:53:13 PM PST 24 |
Jan 03 12:54:30 PM PST 24 |
45085016 ps |
| T14 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.440619912 |
|
|
Jan 03 12:52:55 PM PST 24 |
Jan 03 12:58:12 PM PST 24 |
2497813505 ps |
| T52 |
/workspace/coverage/default/46.sram_ctrl_bijection.288673404 |
|
|
Jan 03 12:53:44 PM PST 24 |
Jan 03 12:55:48 PM PST 24 |
857975693 ps |
| T53 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.390457326 |
|
|
Jan 03 12:53:16 PM PST 24 |
Jan 03 01:00:10 PM PST 24 |
40630477577 ps |
| T13 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.552671115 |
|
|
Jan 03 12:53:13 PM PST 24 |
Jan 03 12:58:18 PM PST 24 |
25037747525 ps |
| T5 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2160795458 |
|
|
Jan 03 12:51:47 PM PST 24 |
Jan 03 12:52:02 PM PST 24 |
514172298 ps |
| T54 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1860299109 |
|
|
Jan 03 12:53:16 PM PST 24 |
Jan 03 12:54:14 PM PST 24 |
335100232 ps |
| T55 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1184047677 |
|
|
Jan 03 12:53:28 PM PST 24 |
Jan 03 12:55:43 PM PST 24 |
588543507 ps |
| T18 |
/workspace/coverage/default/31.sram_ctrl_alert_test.685509478 |
|
|
Jan 03 12:52:55 PM PST 24 |
Jan 03 12:54:02 PM PST 24 |
54822086 ps |
| T6 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3557387011 |
|
|
Jan 03 12:53:32 PM PST 24 |
Jan 03 12:54:36 PM PST 24 |
4275820687 ps |
| T27 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3272967324 |
|
|
Jan 03 12:52:52 PM PST 24 |
Jan 03 02:00:58 PM PST 24 |
874549034 ps |
| T116 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1170037777 |
|
|
Jan 03 12:53:00 PM PST 24 |
Jan 03 12:54:26 PM PST 24 |
115602284 ps |
| T117 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3550930770 |
|
|
Jan 03 12:52:04 PM PST 24 |
Jan 03 12:52:11 PM PST 24 |
76680170 ps |
| T118 |
/workspace/coverage/default/27.sram_ctrl_smoke.668398533 |
|
|
Jan 03 12:53:13 PM PST 24 |
Jan 03 12:54:31 PM PST 24 |
868468195 ps |
| T30 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.4283534312 |
|
|
Jan 03 12:53:03 PM PST 24 |
Jan 03 12:54:02 PM PST 24 |
35409682 ps |
| T66 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2370844715 |
|
|
Jan 03 12:53:17 PM PST 24 |
Jan 03 12:56:40 PM PST 24 |
6076109750 ps |
| T24 |
/workspace/coverage/default/5.sram_ctrl_regwen.35482735 |
|
|
Jan 03 12:51:54 PM PST 24 |
Jan 03 01:02:00 PM PST 24 |
17468336741 ps |
| T98 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.1273198676 |
|
|
Jan 03 12:53:29 PM PST 24 |
Jan 03 12:54:32 PM PST 24 |
2867336160 ps |
| T119 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.870240028 |
|
|
Jan 03 12:53:44 PM PST 24 |
Jan 03 12:54:53 PM PST 24 |
672398543 ps |
| T120 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3297118352 |
|
|
Jan 03 12:53:20 PM PST 24 |
Jan 03 12:54:28 PM PST 24 |
287308786 ps |
| T91 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3980505296 |
|
|
Jan 03 12:53:05 PM PST 24 |
Jan 03 12:59:39 PM PST 24 |
5026388776 ps |
| T121 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2802511638 |
|
|
Jan 03 12:52:56 PM PST 24 |
Jan 03 12:54:08 PM PST 24 |
479307547 ps |
| T25 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1653592832 |
|
|
Jan 03 12:53:36 PM PST 24 |
Jan 03 01:48:14 PM PST 24 |
21712133306 ps |
| T112 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3558051565 |
|
|
Jan 03 12:52:17 PM PST 24 |
Jan 03 12:52:59 PM PST 24 |
1847457282 ps |
| T26 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.599144534 |
|
|
Jan 03 12:51:56 PM PST 24 |
Jan 03 12:52:05 PM PST 24 |
322359509 ps |
| T122 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1298993182 |
|
|
Jan 03 12:52:46 PM PST 24 |
Jan 03 12:54:24 PM PST 24 |
2967535605 ps |
| T67 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2177170709 |
|
|
Jan 03 12:53:00 PM PST 24 |
Jan 03 01:55:21 PM PST 24 |
80888136461 ps |
| T123 |
/workspace/coverage/default/42.sram_ctrl_bijection.2053825645 |
|
|
Jan 03 12:53:51 PM PST 24 |
Jan 03 12:55:45 PM PST 24 |
1644271624 ps |
| T110 |
/workspace/coverage/default/42.sram_ctrl_regwen.1430258224 |
|
|
Jan 03 12:53:40 PM PST 24 |
Jan 03 12:54:58 PM PST 24 |
644151120 ps |
| T92 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.191750848 |
|
|
Jan 03 12:53:27 PM PST 24 |
Jan 03 12:57:47 PM PST 24 |
4521219875 ps |
| T124 |
/workspace/coverage/default/36.sram_ctrl_bijection.1339624670 |
|
|
Jan 03 12:53:16 PM PST 24 |
Jan 03 12:54:36 PM PST 24 |
5719521656 ps |
| T73 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.135638562 |
|
|
Jan 03 12:52:53 PM PST 24 |
Jan 03 12:54:23 PM PST 24 |
65692035 ps |
| T19 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2563850444 |
|
|
Jan 03 12:52:57 PM PST 24 |
Jan 03 12:54:09 PM PST 24 |
30543933 ps |
| T93 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3121123101 |
|
|
Jan 03 12:53:10 PM PST 24 |
Jan 03 12:58:30 PM PST 24 |
7267052295 ps |
| T125 |
/workspace/coverage/default/6.sram_ctrl_bijection.1539211477 |
|
|
Jan 03 12:52:10 PM PST 24 |
Jan 03 12:52:54 PM PST 24 |
1458453840 ps |
| T31 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1315823311 |
|
|
Jan 03 12:52:11 PM PST 24 |
Jan 03 12:52:31 PM PST 24 |
44902896 ps |
| T126 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.90321606 |
|
|
Jan 03 12:53:58 PM PST 24 |
Jan 03 12:55:36 PM PST 24 |
27321194 ps |
| T127 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.905714670 |
|
|
Jan 03 12:53:34 PM PST 24 |
Jan 03 12:55:10 PM PST 24 |
101732986 ps |
| T74 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.752952613 |
|
|
Jan 03 12:52:16 PM PST 24 |
Jan 03 12:52:45 PM PST 24 |
42783311 ps |
| T128 |
/workspace/coverage/default/38.sram_ctrl_executable.3103209037 |
|
|
Jan 03 12:53:48 PM PST 24 |
Jan 03 12:55:49 PM PST 24 |
118397995 ps |
| T113 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.4256970429 |
|
|
Jan 03 12:51:40 PM PST 24 |
Jan 03 01:06:08 PM PST 24 |
13390364525 ps |
| T129 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.766915155 |
|
|
Jan 03 12:53:00 PM PST 24 |
Jan 03 12:55:43 PM PST 24 |
610492208 ps |
| T28 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2403665649 |
|
|
Jan 03 12:53:43 PM PST 24 |
Jan 03 01:22:52 PM PST 24 |
422640028 ps |
| T130 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1820084117 |
|
|
Jan 03 12:51:36 PM PST 24 |
Jan 03 12:58:39 PM PST 24 |
23592625816 ps |
| T131 |
/workspace/coverage/default/12.sram_ctrl_bijection.20502580 |
|
|
Jan 03 12:52:13 PM PST 24 |
Jan 03 12:53:41 PM PST 24 |
12912823103 ps |
| T75 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3247710538 |
|
|
Jan 03 12:52:22 PM PST 24 |
Jan 03 12:53:28 PM PST 24 |
200422481 ps |
| T111 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984965878 |
|
|
Jan 03 12:52:10 PM PST 24 |
Jan 03 12:58:30 PM PST 24 |
34448629493 ps |
| T132 |
/workspace/coverage/default/20.sram_ctrl_executable.2344189694 |
|
|
Jan 03 12:52:25 PM PST 24 |
Jan 03 12:59:07 PM PST 24 |
2713041989 ps |
| T42 |
/workspace/coverage/default/36.sram_ctrl_regwen.2866864904 |
|
|
Jan 03 12:53:22 PM PST 24 |
Jan 03 01:04:18 PM PST 24 |
7357726541 ps |
| T29 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.748449485 |
|
|
Jan 03 12:23:46 PM PST 24 |
Jan 03 12:23:48 PM PST 24 |
113919720 ps |
| T58 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1459471630 |
|
|
Jan 03 12:30:10 PM PST 24 |
Jan 03 12:30:57 PM PST 24 |
35876336 ps |
| T45 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.492331973 |
|
|
Jan 03 12:30:44 PM PST 24 |
Jan 03 12:31:54 PM PST 24 |
533843460 ps |
| T59 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2108630838 |
|
|
Jan 03 12:29:32 PM PST 24 |
Jan 03 12:30:06 PM PST 24 |
28876847 ps |
| T46 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4287674868 |
|
|
Jan 03 12:22:44 PM PST 24 |
Jan 03 12:22:49 PM PST 24 |
43709672 ps |
| T60 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3395350224 |
|
|
Jan 03 12:28:42 PM PST 24 |
Jan 03 12:29:13 PM PST 24 |
5323205744 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3406833482 |
|
|
Jan 03 12:42:49 PM PST 24 |
Jan 03 12:44:27 PM PST 24 |
444703580 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2829023554 |
|
|
Jan 03 12:23:46 PM PST 24 |
Jan 03 12:23:48 PM PST 24 |
129163047 ps |
| T43 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.810881151 |
|
|
Jan 03 12:30:14 PM PST 24 |
Jan 03 12:31:04 PM PST 24 |
178387772 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1577173276 |
|
|
Jan 03 12:27:22 PM PST 24 |
Jan 03 12:27:28 PM PST 24 |
49424772 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3140007067 |
|
|
Jan 03 12:42:02 PM PST 24 |
Jan 03 12:43:38 PM PST 24 |
14973602 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.674650616 |
|
|
Jan 03 12:22:39 PM PST 24 |
Jan 03 12:22:40 PM PST 24 |
63143895 ps |
| T47 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2938114980 |
|
|
Jan 03 12:25:55 PM PST 24 |
Jan 03 12:25:57 PM PST 24 |
44093432 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1074419557 |
|
|
Jan 03 12:29:33 PM PST 24 |
Jan 03 12:30:09 PM PST 24 |
85836731 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3995693143 |
|
|
Jan 03 12:29:49 PM PST 24 |
Jan 03 12:30:33 PM PST 24 |
37198387 ps |
| T48 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2823037004 |
|
|
Jan 03 12:24:54 PM PST 24 |
Jan 03 12:24:56 PM PST 24 |
103441736 ps |
| T49 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1755059240 |
|
|
Jan 03 12:38:33 PM PST 24 |
Jan 03 12:39:46 PM PST 24 |
164984311 ps |
| T50 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2614583454 |
|
|
Jan 03 12:25:49 PM PST 24 |
Jan 03 12:25:53 PM PST 24 |
115945571 ps |
| T57 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1373131371 |
|
|
Jan 03 12:29:19 PM PST 24 |
Jan 03 12:29:49 PM PST 24 |
52134609 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3022756512 |
|
|
Jan 03 12:30:18 PM PST 24 |
Jan 03 12:31:19 PM PST 24 |
809032990 ps |
| T51 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4180790500 |
|
|
Jan 03 12:47:43 PM PST 24 |
Jan 03 12:48:28 PM PST 24 |
1022186894 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3743472430 |
|
|
Jan 03 12:30:38 PM PST 24 |
Jan 03 12:31:43 PM PST 24 |
212045156 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3919535089 |
|
|
Jan 03 12:41:30 PM PST 24 |
Jan 03 12:42:59 PM PST 24 |
69559566 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1569873766 |
|
|
Jan 03 12:25:07 PM PST 24 |
Jan 03 12:25:11 PM PST 24 |
14052497 ps |
| T133 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.391556233 |
|
|
Jan 03 12:32:05 PM PST 24 |
Jan 03 12:33:34 PM PST 24 |
37960208 ps |
| T71 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.993855239 |
|
|
Jan 03 12:32:32 PM PST 24 |
Jan 03 12:34:04 PM PST 24 |
824696556 ps |
| T56 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2785595152 |
|
|
Jan 03 12:29:32 PM PST 24 |
Jan 03 12:30:08 PM PST 24 |
570298463 ps |
| T134 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3659863161 |
|
|
Jan 03 12:22:41 PM PST 24 |
Jan 03 12:22:45 PM PST 24 |
68751904 ps |
| T135 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3931937564 |
|
|
Jan 03 12:23:02 PM PST 24 |
Jan 03 12:23:06 PM PST 24 |
186554119 ps |
| T72 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3248991177 |
|
|
Jan 03 12:35:06 PM PST 24 |
Jan 03 12:36:42 PM PST 24 |
99007268 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4244428152 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:15 PM PST 24 |
27276296 ps |
| T137 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.298805165 |
|
|
Jan 03 12:35:15 PM PST 24 |
Jan 03 12:36:58 PM PST 24 |
35036965 ps |
| T44 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1865040085 |
|
|
Jan 03 12:30:07 PM PST 24 |
Jan 03 12:30:54 PM PST 24 |
847191332 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1674894688 |
|
|
Jan 03 12:33:16 PM PST 24 |
Jan 03 12:34:29 PM PST 24 |
219445167 ps |
| T138 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3488079778 |
|
|
Jan 03 12:29:34 PM PST 24 |
Jan 03 12:30:09 PM PST 24 |
62851643 ps |
| T139 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.930008620 |
|
|
Jan 03 12:32:32 PM PST 24 |
Jan 03 12:33:59 PM PST 24 |
574510262 ps |
| T140 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1566149104 |
|
|
Jan 03 12:27:31 PM PST 24 |
Jan 03 12:27:36 PM PST 24 |
38320991 ps |
| T99 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3087420518 |
|
|
Jan 03 12:42:13 PM PST 24 |
Jan 03 12:43:49 PM PST 24 |
175743052 ps |
| T141 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4037541750 |
|
|
Jan 03 12:30:07 PM PST 24 |
Jan 03 12:30:54 PM PST 24 |
278887930 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3165833082 |
|
|
Jan 03 12:30:23 PM PST 24 |
Jan 03 12:31:22 PM PST 24 |
212020717 ps |
| T142 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2449111307 |
|
|
Jan 03 12:30:36 PM PST 24 |
Jan 03 12:31:38 PM PST 24 |
15804131 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.814616653 |
|
|
Jan 03 12:24:45 PM PST 24 |
Jan 03 12:24:48 PM PST 24 |
18461927 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3843702075 |
|
|
Jan 03 12:24:51 PM PST 24 |
Jan 03 12:25:03 PM PST 24 |
1321866033 ps |
| T143 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2808820122 |
|
|
Jan 03 12:45:59 PM PST 24 |
Jan 03 12:47:26 PM PST 24 |
41440695 ps |
| T144 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2603324304 |
|
|
Jan 03 12:27:25 PM PST 24 |
Jan 03 12:27:34 PM PST 24 |
37874654 ps |
| T145 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2727530434 |
|
|
Jan 03 12:25:21 PM PST 24 |
Jan 03 12:25:23 PM PST 24 |
19369018 ps |
| T146 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.247609395 |
|
|
Jan 03 12:27:31 PM PST 24 |
Jan 03 12:27:36 PM PST 24 |
18640100 ps |
| T147 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3597253668 |
|
|
Jan 03 12:44:26 PM PST 24 |
Jan 03 12:45:54 PM PST 24 |
36497048 ps |
| T148 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1893117103 |
|
|
Jan 03 12:29:27 PM PST 24 |
Jan 03 12:30:00 PM PST 24 |
31402150 ps |
| T149 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1812135033 |
|
|
Jan 03 12:23:52 PM PST 24 |
Jan 03 12:23:53 PM PST 24 |
41129390 ps |
| T102 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3307229013 |
|
|
Jan 03 12:30:26 PM PST 24 |
Jan 03 12:31:25 PM PST 24 |
191262814 ps |
| T150 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1019853924 |
|
|
Jan 03 12:27:30 PM PST 24 |
Jan 03 12:27:37 PM PST 24 |
238613140 ps |
| T151 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.877293639 |
|
|
Jan 03 12:30:13 PM PST 24 |
Jan 03 12:31:01 PM PST 24 |
20782105 ps |
| T152 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4259003546 |
|
|
Jan 03 12:29:59 PM PST 24 |
Jan 03 12:30:55 PM PST 24 |
56718603 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.596845884 |
|
|
Jan 03 12:42:06 PM PST 24 |
Jan 03 12:43:41 PM PST 24 |
107260088 ps |
| T153 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3493559360 |
|
|
Jan 03 12:27:24 PM PST 24 |
Jan 03 12:27:31 PM PST 24 |
57190997 ps |
| T154 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4022102468 |
|
|
Jan 03 12:30:47 PM PST 24 |
Jan 03 12:31:54 PM PST 24 |
44432658 ps |
| T155 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.223126719 |
|
|
Jan 03 12:30:24 PM PST 24 |
Jan 03 12:31:21 PM PST 24 |
521750141 ps |
| T156 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2722491855 |
|
|
Jan 03 12:27:23 PM PST 24 |
Jan 03 12:27:28 PM PST 24 |
21608138 ps |
| T157 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1614302903 |
|
|
Jan 03 12:29:34 PM PST 24 |
Jan 03 12:30:12 PM PST 24 |
273062833 ps |
| T158 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2005465570 |
|
|
Jan 03 12:28:42 PM PST 24 |
Jan 03 12:29:03 PM PST 24 |
58558887 ps |
| T159 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1080324485 |
|
|
Jan 03 12:33:44 PM PST 24 |
Jan 03 12:35:04 PM PST 24 |
51602060 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1910267834 |
|
|
Jan 03 12:30:18 PM PST 24 |
Jan 03 12:31:11 PM PST 24 |
653128026 ps |
| T160 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3944985733 |
|
|
Jan 03 12:30:38 PM PST 24 |
Jan 03 12:31:41 PM PST 24 |
47799723 ps |
| T161 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2409288979 |
|
|
Jan 03 12:24:14 PM PST 24 |
Jan 03 12:24:17 PM PST 24 |
23860646 ps |
| T162 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2434325946 |
|
|
Jan 03 12:27:51 PM PST 24 |
Jan 03 12:28:00 PM PST 24 |
384235426 ps |
| T163 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4066065804 |
|
|
Jan 03 12:28:53 PM PST 24 |
Jan 03 12:29:22 PM PST 24 |
19882910 ps |
| T164 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.541016010 |
|
|
Jan 03 12:30:18 PM PST 24 |
Jan 03 12:31:12 PM PST 24 |
281339327 ps |
| T165 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2229218326 |
|
|
Jan 03 12:32:31 PM PST 24 |
Jan 03 12:33:58 PM PST 24 |
106928088 ps |
| T166 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3588204671 |
|
|
Jan 03 12:29:47 PM PST 24 |
Jan 03 12:30:29 PM PST 24 |
36522318 ps |
| T167 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1916259687 |
|
|
Jan 03 12:29:17 PM PST 24 |
Jan 03 12:29:46 PM PST 24 |
42831216 ps |
| T168 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.101185114 |
|
|
Jan 03 12:44:15 PM PST 24 |
Jan 03 12:45:55 PM PST 24 |
13904711 ps |
| T169 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2047000813 |
|
|
Jan 03 12:44:15 PM PST 24 |
Jan 03 12:45:38 PM PST 24 |
17070765 ps |
| T103 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.539431386 |
|
|
Jan 03 12:24:45 PM PST 24 |
Jan 03 12:24:50 PM PST 24 |
429772774 ps |
| T88 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3450355673 |
|
|
Jan 03 12:23:47 PM PST 24 |
Jan 03 12:23:59 PM PST 24 |
1385339164 ps |
| T170 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1787190567 |
|
|
Jan 03 12:29:17 PM PST 24 |
Jan 03 12:29:46 PM PST 24 |
36460553 ps |
| T171 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2476707462 |
|
|
Jan 03 12:30:22 PM PST 24 |
Jan 03 12:31:21 PM PST 24 |
793659578 ps |
| T101 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3380791448 |
|
|
Jan 03 12:29:08 PM PST 24 |
Jan 03 12:29:36 PM PST 24 |
104946399 ps |
| T172 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1149756450 |
|
|
Jan 03 12:27:31 PM PST 24 |
Jan 03 12:27:40 PM PST 24 |
516189109 ps |
| T173 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2515732193 |
|
|
Jan 03 12:29:05 PM PST 24 |
Jan 03 12:29:33 PM PST 24 |
13784627 ps |
| T174 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2761696945 |
|
|
Jan 03 12:30:07 PM PST 24 |
Jan 03 12:30:56 PM PST 24 |
36516864 ps |
| T175 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3504181915 |
|
|
Jan 03 12:44:37 PM PST 24 |
Jan 03 12:46:01 PM PST 24 |
288050876 ps |
| T176 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.329050143 |
|
|
Jan 03 12:23:55 PM PST 24 |
Jan 03 12:23:58 PM PST 24 |
30352187 ps |
| T177 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3680631001 |
|
|
Jan 03 12:25:49 PM PST 24 |
Jan 03 12:25:51 PM PST 24 |
63221677 ps |
| T178 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.415862822 |
|
|
Jan 03 12:29:35 PM PST 24 |
Jan 03 12:30:11 PM PST 24 |
353313354 ps |
| T179 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1296085788 |
|
|
Jan 03 12:27:16 PM PST 24 |
Jan 03 12:27:19 PM PST 24 |
14586586 ps |
| T180 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3050987150 |
|
|
Jan 03 12:30:23 PM PST 24 |
Jan 03 12:31:19 PM PST 24 |
50335819 ps |
| T181 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2724419795 |
|
|
Jan 03 12:30:18 PM PST 24 |
Jan 03 12:31:10 PM PST 24 |
30120815 ps |
| T182 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1326890657 |
|
|
Jan 03 12:44:13 PM PST 24 |
Jan 03 12:45:37 PM PST 24 |
117074476 ps |
| T89 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.145352187 |
|
|
Jan 03 12:32:48 PM PST 24 |
Jan 03 12:34:58 PM PST 24 |
769475973 ps |
| T183 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3694459505 |
|
|
Jan 03 12:23:42 PM PST 24 |
Jan 03 12:23:46 PM PST 24 |
104593004 ps |
| T184 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4105466026 |
|
|
Jan 03 12:27:24 PM PST 24 |
Jan 03 12:27:30 PM PST 24 |
98759419 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2316166604 |
|
|
Jan 03 12:28:39 PM PST 24 |
Jan 03 12:28:58 PM PST 24 |
690802220 ps |
| T185 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.479630120 |
|
|
Jan 03 12:32:39 PM PST 24 |
Jan 03 12:34:13 PM PST 24 |
501521659 ps |
| T186 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.69606221 |
|
|
Jan 03 12:25:11 PM PST 24 |
Jan 03 12:25:16 PM PST 24 |
13220322 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.168685339 |
|
|
Jan 03 12:30:12 PM PST 24 |
Jan 03 12:31:10 PM PST 24 |
755548412 ps |
| T187 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4043489605 |
|
|
Jan 03 12:31:05 PM PST 24 |
Jan 03 12:32:13 PM PST 24 |
15131875 ps |
| T188 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3024387534 |
|
|
Jan 03 12:24:09 PM PST 24 |
Jan 03 12:24:15 PM PST 24 |
265692648 ps |
| T189 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2675408562 |
|
|
Jan 03 12:25:55 PM PST 24 |
Jan 03 12:25:58 PM PST 24 |
208582091 ps |
| T190 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920586082 |
|
|
Jan 03 12:30:00 PM PST 24 |
Jan 03 12:30:50 PM PST 24 |
405170171 ps |
| T191 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2186139360 |
|
|
Jan 03 12:45:37 PM PST 24 |
Jan 03 12:47:20 PM PST 24 |
52639475 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2930174204 |
|
|
Jan 03 12:23:35 PM PST 24 |
Jan 03 12:23:38 PM PST 24 |
1012060507 ps |
| T192 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1361027680 |
|
|
Jan 03 12:30:23 PM PST 24 |
Jan 03 12:31:21 PM PST 24 |
1059590985 ps |
| T193 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.825318500 |
|
|
Jan 03 12:27:30 PM PST 24 |
Jan 03 12:27:36 PM PST 24 |
18816389 ps |
| T194 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3129303338 |
|
|
Jan 03 12:30:06 PM PST 24 |
Jan 03 12:30:53 PM PST 24 |
21999632 ps |
| T195 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.240334738 |
|
|
Jan 03 12:29:45 PM PST 24 |
Jan 03 12:30:26 PM PST 24 |
13719324 ps |
| T196 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1099977191 |
|
|
Jan 03 12:29:57 PM PST 24 |
Jan 03 12:30:43 PM PST 24 |
29200035 ps |
| T197 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4004724965 |
|
|
Jan 03 12:24:14 PM PST 24 |
Jan 03 12:24:18 PM PST 24 |
359037145 ps |
| T198 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3392755584 |
|
|
Jan 03 12:30:17 PM PST 24 |
Jan 03 12:31:09 PM PST 24 |
16236128 ps |
| T199 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.170173412 |
|
|
Jan 03 12:42:12 PM PST 24 |
Jan 03 12:43:34 PM PST 24 |
43236474 ps |
| T200 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1867249165 |
|
|
Jan 03 12:30:23 PM PST 24 |
Jan 03 12:31:19 PM PST 24 |
12833523 ps |
| T201 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.519739971 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:36:01 PM PST 24 |
13865038 ps |
| T202 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2548046687 |
|
|
Jan 03 12:23:42 PM PST 24 |
Jan 03 12:23:46 PM PST 24 |
129173671 ps |
| T203 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2947925447 |
|
|
Jan 03 12:30:17 PM PST 24 |
Jan 03 12:31:11 PM PST 24 |
212787893 ps |
| T204 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1275262245 |
|
|
Jan 03 12:30:11 PM PST 24 |
Jan 03 12:30:59 PM PST 24 |
112364651 ps |
| T205 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4036277924 |
|
|
Jan 03 12:30:12 PM PST 24 |
Jan 03 12:31:00 PM PST 24 |
201230554 ps |
| T206 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3561141649 |
|
|
Jan 03 12:27:24 PM PST 24 |
Jan 03 12:27:30 PM PST 24 |
197326588 ps |
| T207 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.831299584 |
|
|
Jan 03 12:29:22 PM PST 24 |
Jan 03 12:29:55 PM PST 24 |
138875215 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2770576451 |
|
|
Jan 03 12:28:39 PM PST 24 |
Jan 03 12:28:58 PM PST 24 |
244134292 ps |
| T208 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3975942118 |
|
|
Jan 03 12:29:52 PM PST 24 |
Jan 03 12:30:35 PM PST 24 |
31518720 ps |
| T209 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2163562855 |
|
|
Jan 03 12:23:47 PM PST 24 |
Jan 03 12:23:50 PM PST 24 |
25974320 ps |
| T210 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.969301239 |
|
|
Jan 03 12:29:08 PM PST 24 |
Jan 03 12:29:35 PM PST 24 |
51729992 ps |
| T211 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2433694187 |
|
|
Jan 03 12:32:48 PM PST 24 |
Jan 03 12:34:13 PM PST 24 |
26156169 ps |
| T212 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4207087774 |
|
|
Jan 03 12:26:07 PM PST 24 |
Jan 03 12:26:13 PM PST 24 |
1566301988 ps |
| T213 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1312840109 |
|
|
Jan 03 12:27:30 PM PST 24 |
Jan 03 12:27:38 PM PST 24 |
98639431 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.481195878 |
|
|
Jan 03 12:28:15 PM PST 24 |
Jan 03 12:28:22 PM PST 24 |
17778823 ps |
| T214 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1863992650 |
|
|
Jan 03 12:24:45 PM PST 24 |
Jan 03 12:24:48 PM PST 24 |
182744762 ps |
| T215 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3531652648 |
|
|
Jan 03 12:34:12 PM PST 24 |
Jan 03 12:35:29 PM PST 24 |
20542272 ps |
| T216 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.690198428 |
|
|
Jan 03 12:22:45 PM PST 24 |
Jan 03 12:22:48 PM PST 24 |
49536278 ps |
| T217 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3172853852 |
|
|
Jan 03 12:30:01 PM PST 24 |
Jan 03 12:30:47 PM PST 24 |
161702604 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.55977882 |
|
|
Jan 03 12:33:37 PM PST 24 |
Jan 03 12:34:48 PM PST 24 |
270335501 ps |
| T114 |
/workspace/coverage/default/38.sram_ctrl_regwen.3203757022 |
|
|
Jan 03 12:53:38 PM PST 24 |
Jan 03 01:10:43 PM PST 24 |
20545336062 ps |
| T218 |
/workspace/coverage/default/6.sram_ctrl_smoke.2703342506 |
|
|
Jan 03 12:51:54 PM PST 24 |
Jan 03 12:52:11 PM PST 24 |
718439535 ps |
| T219 |
/workspace/coverage/default/16.sram_ctrl_regwen.510206807 |
|
|
Jan 03 12:52:11 PM PST 24 |
Jan 03 01:09:43 PM PST 24 |
97039519062 ps |
| T79 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3930298403 |
|
|
Jan 03 12:52:27 PM PST 24 |
Jan 03 12:53:30 PM PST 24 |
768269830 ps |
| T15 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2287220457 |
|
|
Jan 03 12:54:02 PM PST 24 |
Jan 03 01:02:37 PM PST 24 |
8158715562 ps |
| T16 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4180970225 |
|
|
Jan 03 12:53:42 PM PST 24 |
Jan 03 12:58:28 PM PST 24 |
423828568 ps |
| T220 |
/workspace/coverage/default/8.sram_ctrl_executable.3710453044 |
|
|
Jan 03 12:52:07 PM PST 24 |
Jan 03 01:02:30 PM PST 24 |
36338096222 ps |
| T20 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4024635506 |
|
|
Jan 03 12:53:50 PM PST 24 |
Jan 03 12:55:06 PM PST 24 |
15049359 ps |
| T221 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3898783751 |
|
|
Jan 03 12:53:33 PM PST 24 |
Jan 03 02:35:25 PM PST 24 |
2060508761 ps |
| T80 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.150671952 |
|
|
Jan 03 12:53:49 PM PST 24 |
Jan 03 12:55:20 PM PST 24 |
159167581 ps |
| T222 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1191439822 |
|
|
Jan 03 12:52:14 PM PST 24 |
Jan 03 12:52:46 PM PST 24 |
775418630 ps |
| T223 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1801156527 |
|
|
Jan 03 12:52:12 PM PST 24 |
Jan 03 12:52:41 PM PST 24 |
603151325 ps |
| T17 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3732260799 |
|
|
Jan 03 12:52:18 PM PST 24 |
Jan 03 01:04:35 PM PST 24 |
3143696133 ps |
| T224 |
/workspace/coverage/default/5.sram_ctrl_executable.1205539552 |
|
|
Jan 03 12:51:43 PM PST 24 |
Jan 03 01:04:06 PM PST 24 |
29277757982 ps |
| T225 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.473839597 |
|
|
Jan 03 12:51:08 PM PST 24 |
Jan 03 12:51:32 PM PST 24 |
57370406 ps |
| T226 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3033345462 |
|
|
Jan 03 12:53:21 PM PST 24 |
Jan 03 12:54:13 PM PST 24 |
1034572489 ps |
| T227 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3198986776 |
|
|
Jan 03 12:52:59 PM PST 24 |
Jan 03 12:54:30 PM PST 24 |
20220694 ps |
| T81 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3015697009 |
|
|
Jan 03 12:51:17 PM PST 24 |
Jan 03 12:51:38 PM PST 24 |
248044210 ps |
| T228 |
/workspace/coverage/default/3.sram_ctrl_regwen.1703041608 |
|
|
Jan 03 12:51:22 PM PST 24 |
Jan 03 01:07:13 PM PST 24 |
61811049578 ps |
| T229 |
/workspace/coverage/default/17.sram_ctrl_partial_access.4145520208 |
|
|
Jan 03 12:52:15 PM PST 24 |
Jan 03 12:52:50 PM PST 24 |
535497995 ps |
| T96 |
/workspace/coverage/default/3.sram_ctrl_stress_all.527524590 |
|
|
Jan 03 12:51:36 PM PST 24 |
Jan 03 01:04:10 PM PST 24 |
13731866327 ps |
| T230 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4066551524 |
|
|
Jan 03 12:53:48 PM PST 24 |
Jan 03 12:57:11 PM PST 24 |
2475060300 ps |
| T231 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.201373674 |
|
|
Jan 03 12:53:54 PM PST 24 |
Jan 03 12:55:28 PM PST 24 |
1872269226 ps |
| T232 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.624124285 |
|
|
Jan 03 12:53:02 PM PST 24 |
Jan 03 12:59:29 PM PST 24 |
4009658361 ps |
| T233 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4007442763 |
|
|
Jan 03 12:53:14 PM PST 24 |
Jan 03 12:54:11 PM PST 24 |
440018928 ps |
| T234 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1475315521 |
|
|
Jan 03 12:53:01 PM PST 24 |
Jan 03 12:58:53 PM PST 24 |
5647273575 ps |
| T235 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1556951241 |
|
|
Jan 03 12:52:45 PM PST 24 |
Jan 03 12:55:04 PM PST 24 |
453254352 ps |
| T236 |
/workspace/coverage/default/11.sram_ctrl_smoke.1658519114 |
|
|
Jan 03 12:52:18 PM PST 24 |
Jan 03 12:52:51 PM PST 24 |
163065718 ps |
| T237 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2561776775 |
|
|
Jan 03 12:52:57 PM PST 24 |
Jan 03 12:54:09 PM PST 24 |
174016425 ps |
| T238 |
/workspace/coverage/default/42.sram_ctrl_executable.1387560944 |
|
|
Jan 03 12:53:13 PM PST 24 |
Jan 03 01:08:55 PM PST 24 |
14836375389 ps |
| T239 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.4025461552 |
|
|
Jan 03 12:53:53 PM PST 24 |
Jan 03 12:56:29 PM PST 24 |
247014918 ps |
| T240 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1125046080 |
|
|
Jan 03 12:52:54 PM PST 24 |
Jan 03 12:54:21 PM PST 24 |
98275876 ps |
| T241 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3605752032 |
|
|
Jan 03 12:52:13 PM PST 24 |
Jan 03 01:14:29 PM PST 24 |
3803105687 ps |
| T242 |
/workspace/coverage/default/28.sram_ctrl_bijection.623932461 |
|
|
Jan 03 12:53:37 PM PST 24 |
Jan 03 12:54:55 PM PST 24 |
1042856234 ps |
| T243 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2141087766 |
|
|
Jan 03 12:52:15 PM PST 24 |
Jan 03 12:52:49 PM PST 24 |
64527558 ps |
| T244 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1894310328 |
|
|
Jan 03 12:53:13 PM PST 24 |
Jan 03 12:54:38 PM PST 24 |
448036227 ps |
| T245 |
/workspace/coverage/default/8.sram_ctrl_smoke.3068215173 |
|
|
Jan 03 12:51:33 PM PST 24 |
Jan 03 12:51:55 PM PST 24 |
188024366 ps |
| T246 |
/workspace/coverage/default/29.sram_ctrl_smoke.3442738293 |
|
|
Jan 03 12:52:45 PM PST 24 |
Jan 03 12:54:14 PM PST 24 |
349959103 ps |
| T247 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.439143892 |
|
|
Jan 03 12:52:19 PM PST 24 |
Jan 03 12:52:50 PM PST 24 |
457289480 ps |
| T248 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.86105484 |
|
|
Jan 03 12:52:12 PM PST 24 |
Jan 03 01:20:20 PM PST 24 |
11640973045 ps |
| T249 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3880917401 |
|
|
Jan 03 12:53:32 PM PST 24 |
Jan 03 12:54:24 PM PST 24 |
24456222 ps |
| T250 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3555300203 |
|
|
Jan 03 12:53:17 PM PST 24 |
Jan 03 12:54:27 PM PST 24 |
75639287 ps |
| T251 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.932233485 |
|
|
Jan 03 12:51:42 PM PST 24 |
Jan 03 01:04:03 PM PST 24 |
8695384633 ps |
| T252 |
/workspace/coverage/default/27.sram_ctrl_bijection.1324212600 |
|
|
Jan 03 12:53:08 PM PST 24 |
Jan 03 12:54:34 PM PST 24 |
540983583 ps |
| T253 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3484651322 |
|
|
Jan 03 12:52:53 PM PST 24 |
Jan 03 12:54:13 PM PST 24 |
322623076 ps |
| T254 |
/workspace/coverage/default/24.sram_ctrl_smoke.3426574915 |
|
|
Jan 03 12:52:55 PM PST 24 |
Jan 03 12:54:02 PM PST 24 |
93099565 ps |
| T255 |
/workspace/coverage/default/0.sram_ctrl_bijection.3448969379 |
|
|
Jan 03 12:51:08 PM PST 24 |
Jan 03 12:52:05 PM PST 24 |
2122642490 ps |
| T115 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.738011176 |
|
|
Jan 03 12:52:48 PM PST 24 |
Jan 03 01:01:03 PM PST 24 |
4944362066 ps |
| T256 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.63030385 |
|
|
Jan 03 12:52:59 PM PST 24 |
Jan 03 01:03:33 PM PST 24 |
55696035162 ps |
| T257 |
/workspace/coverage/default/5.sram_ctrl_bijection.3282563570 |
|
|
Jan 03 12:51:33 PM PST 24 |
Jan 03 12:52:54 PM PST 24 |
3442740344 ps |
| T258 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.39661381 |
|
|
Jan 03 12:53:01 PM PST 24 |
Jan 03 12:54:27 PM PST 24 |
175401206 ps |
| T259 |
/workspace/coverage/default/0.sram_ctrl_executable.1435293617 |
|
|
Jan 03 12:51:09 PM PST 24 |
Jan 03 01:06:57 PM PST 24 |
7933125835 ps |
| T260 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2859067206 |
|
|
Jan 03 12:53:32 PM PST 24 |
Jan 03 12:54:47 PM PST 24 |
1512351561 ps |
| T261 |
/workspace/coverage/default/31.sram_ctrl_bijection.4268607580 |
|
|
Jan 03 12:53:40 PM PST 24 |
Jan 03 12:55:54 PM PST 24 |
7688352125 ps |
| T97 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1298384014 |
|
|
Jan 03 12:52:19 PM PST 24 |
Jan 03 12:52:50 PM PST 24 |
1189422021 ps |
| T262 |
/workspace/coverage/default/13.sram_ctrl_executable.468635760 |
|
|
Jan 03 12:52:00 PM PST 24 |
Jan 03 01:00:44 PM PST 24 |
2395548931 ps |
| T263 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.4027868488 |
|
|
Jan 03 12:52:06 PM PST 24 |
Jan 03 12:59:51 PM PST 24 |
41494723792 ps |
| T264 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.958471664 |
|
|
Jan 03 12:52:11 PM PST 24 |
Jan 03 12:52:31 PM PST 24 |
7226788630 ps |
| T265 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3571836109 |
|
|
Jan 03 12:52:27 PM PST 24 |
Jan 03 01:01:11 PM PST 24 |
1376338329 ps |
| T266 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2066687694 |
|
|
Jan 03 12:52:09 PM PST 24 |
Jan 03 01:20:00 PM PST 24 |
16468584267 ps |
| T267 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3137867831 |
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Jan 03 12:53:09 PM PST 24 |
Jan 03 01:00:22 PM PST 24 |
4640317450 ps |