Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42847627	1			T1	35186		T2	211088		T3	1015
triple_byte_access	2262479	1			T1	679		T2	3267		T3	20
halfword_access	3394988	1			T1	1141		T2	4810		T3	28
byte_access	4533079	1			T1	1436		T2	6572		T3	45
zero_access	1143830	1			T1	347		T2	1615		T3	11

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27039863

1

T1

19475

T2

113539

T3

561

auto[1]

27142140

1

T1

19314

T2

113813

T3

558

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21377409	1			T1	17654		T2	105390		T3	507
auto[0]	triple_byte_access	1126850	1			T1	346		T2	1619		T3	9
auto[0]	halfword_access	1693003	1			T1	584		T2	2396		T3	13
auto[0]	byte_access	2266696	1			T1	715		T2	3297		T3	24
auto[0]	zero_access	575905	1			T1	176		T2	837		T3	8
auto[1]	word_access	21470218	1			T1	17532		T2	105698		T3	508
auto[1]	triple_byte_access	1135629	1			T1	333		T2	1648		T3	11
auto[1]	halfword_access	1701985	1			T1	557		T2	2414		T3	15
auto[1]	byte_access	2266383	1			T1	721		T2	3275		T3	21
auto[1]	zero_access	567925	1			T1	171		T2	778		T3	3