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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total test records in report: 989
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T755 /workspace/coverage/default/19.sram_ctrl_max_throughput.2505636416 Jan 03 12:52:21 PM PST 24 Jan 03 12:54:14 PM PST 24 100882500 ps
T756 /workspace/coverage/default/42.sram_ctrl_stress_all.2560307848 Jan 03 12:53:42 PM PST 24 Jan 03 01:50:49 PM PST 24 26061997693 ps
T757 /workspace/coverage/default/22.sram_ctrl_partial_access.2718446201 Jan 03 12:52:59 PM PST 24 Jan 03 12:54:26 PM PST 24 98438607 ps
T758 /workspace/coverage/default/26.sram_ctrl_partial_access.1189491918 Jan 03 12:52:56 PM PST 24 Jan 03 12:54:45 PM PST 24 854969364 ps
T759 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3564283464 Jan 03 12:51:36 PM PST 24 Jan 03 12:57:19 PM PST 24 3391938737 ps
T760 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2175093898 Jan 03 12:52:15 PM PST 24 Jan 03 01:58:10 PM PST 24 11046111371 ps
T761 /workspace/coverage/default/47.sram_ctrl_executable.2191785577 Jan 03 12:53:45 PM PST 24 Jan 03 01:01:19 PM PST 24 18341445133 ps
T762 /workspace/coverage/default/16.sram_ctrl_bijection.1723857968 Jan 03 12:51:55 PM PST 24 Jan 03 12:52:21 PM PST 24 1556752339 ps
T763 /workspace/coverage/default/7.sram_ctrl_alert_test.1414461645 Jan 03 12:51:42 PM PST 24 Jan 03 12:51:54 PM PST 24 31543848 ps
T764 /workspace/coverage/default/14.sram_ctrl_mem_walk.3842787490 Jan 03 12:52:14 PM PST 24 Jan 03 12:52:43 PM PST 24 963155898 ps
T765 /workspace/coverage/default/35.sram_ctrl_alert_test.3765680793 Jan 03 12:53:59 PM PST 24 Jan 03 12:55:29 PM PST 24 22428830 ps
T766 /workspace/coverage/default/3.sram_ctrl_smoke.3384962998 Jan 03 12:51:37 PM PST 24 Jan 03 12:51:53 PM PST 24 283999836 ps
T767 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4039373600 Jan 03 12:53:34 PM PST 24 Jan 03 12:54:32 PM PST 24 636985763 ps
T768 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1480014071 Jan 03 12:53:35 PM PST 24 Jan 03 01:00:03 PM PST 24 7075276977 ps
T23 /workspace/coverage/default/0.sram_ctrl_sec_cm.3496016575 Jan 03 12:50:50 PM PST 24 Jan 03 12:51:16 PM PST 24 442157472 ps
T769 /workspace/coverage/default/29.sram_ctrl_partial_access.670841624 Jan 03 12:52:46 PM PST 24 Jan 03 12:55:23 PM PST 24 2623440269 ps
T770 /workspace/coverage/default/21.sram_ctrl_max_throughput.2482379198 Jan 03 12:52:43 PM PST 24 Jan 03 12:54:20 PM PST 24 169361675 ps
T771 /workspace/coverage/default/49.sram_ctrl_stress_all.1034064294 Jan 03 12:53:36 PM PST 24 Jan 03 01:52:34 PM PST 24 210133910074 ps
T772 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1814160997 Jan 03 12:53:02 PM PST 24 Jan 03 12:55:09 PM PST 24 113527402 ps
T773 /workspace/coverage/default/39.sram_ctrl_bijection.1354406732 Jan 03 12:53:47 PM PST 24 Jan 03 12:56:09 PM PST 24 3231006783 ps
T774 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.143519798 Jan 03 12:51:10 PM PST 24 Jan 03 01:39:08 PM PST 24 1771746447 ps
T775 /workspace/coverage/default/11.sram_ctrl_bijection.775879939 Jan 03 12:52:09 PM PST 24 Jan 03 12:53:07 PM PST 24 3185732789 ps
T776 /workspace/coverage/default/17.sram_ctrl_mem_walk.1649167914 Jan 03 12:52:19 PM PST 24 Jan 03 12:52:51 PM PST 24 74717972 ps
T777 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3984282183 Jan 03 12:53:42 PM PST 24 Jan 03 12:59:59 PM PST 24 15310123808 ps
T778 /workspace/coverage/default/31.sram_ctrl_smoke.289719526 Jan 03 12:53:17 PM PST 24 Jan 03 12:54:30 PM PST 24 2032848360 ps
T779 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.757039389 Jan 03 12:51:04 PM PST 24 Jan 03 12:57:15 PM PST 24 107711403028 ps
T780 /workspace/coverage/default/10.sram_ctrl_regwen.3657346978 Jan 03 12:51:54 PM PST 24 Jan 03 12:54:22 PM PST 24 8022533746 ps
T781 /workspace/coverage/default/29.sram_ctrl_mem_walk.3602611993 Jan 03 12:52:52 PM PST 24 Jan 03 12:54:08 PM PST 24 333632395 ps
T782 /workspace/coverage/default/18.sram_ctrl_regwen.4274421814 Jan 03 12:51:55 PM PST 24 Jan 03 12:56:58 PM PST 24 13105252085 ps
T783 /workspace/coverage/default/24.sram_ctrl_mem_walk.2450196228 Jan 03 12:53:45 PM PST 24 Jan 03 12:55:14 PM PST 24 526117146 ps
T784 /workspace/coverage/default/30.sram_ctrl_alert_test.3430259386 Jan 03 12:53:14 PM PST 24 Jan 03 12:54:19 PM PST 24 168458906 ps
T785 /workspace/coverage/default/37.sram_ctrl_smoke.2645819105 Jan 03 12:53:03 PM PST 24 Jan 03 12:54:23 PM PST 24 161475739 ps
T786 /workspace/coverage/default/26.sram_ctrl_mem_walk.745269789 Jan 03 12:53:39 PM PST 24 Jan 03 12:54:50 PM PST 24 934174218 ps
T787 /workspace/coverage/default/14.sram_ctrl_alert_test.2128811229 Jan 03 12:52:20 PM PST 24 Jan 03 12:53:44 PM PST 24 21118572 ps
T788 /workspace/coverage/default/39.sram_ctrl_stress_all.3052061816 Jan 03 12:53:08 PM PST 24 Jan 03 01:30:26 PM PST 24 357491676671 ps
T789 /workspace/coverage/default/36.sram_ctrl_max_throughput.2776487337 Jan 03 12:53:52 PM PST 24 Jan 03 12:56:16 PM PST 24 457402087 ps
T790 /workspace/coverage/default/0.sram_ctrl_partial_access.2677777520 Jan 03 12:51:13 PM PST 24 Jan 03 12:51:45 PM PST 24 7319510656 ps
T791 /workspace/coverage/default/17.sram_ctrl_executable.1662636430 Jan 03 12:52:21 PM PST 24 Jan 03 01:02:00 PM PST 24 25523389647 ps
T792 /workspace/coverage/default/17.sram_ctrl_bijection.898235322 Jan 03 12:52:15 PM PST 24 Jan 03 12:53:09 PM PST 24 7319272183 ps
T793 /workspace/coverage/default/8.sram_ctrl_multiple_keys.200468374 Jan 03 12:51:43 PM PST 24 Jan 03 01:19:33 PM PST 24 43954627682 ps
T794 /workspace/coverage/default/18.sram_ctrl_ram_cfg.2672913732 Jan 03 12:52:08 PM PST 24 Jan 03 12:52:19 PM PST 24 31506103 ps
T795 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1281950290 Jan 03 12:52:52 PM PST 24 Jan 03 01:24:10 PM PST 24 395597592 ps
T796 /workspace/coverage/default/32.sram_ctrl_smoke.1643367817 Jan 03 12:52:46 PM PST 24 Jan 03 12:54:19 PM PST 24 73482271 ps
T797 /workspace/coverage/default/47.sram_ctrl_smoke.2336320631 Jan 03 12:53:01 PM PST 24 Jan 03 12:54:34 PM PST 24 2169794124 ps
T798 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1812688137 Jan 03 12:52:45 PM PST 24 Jan 03 01:57:23 PM PST 24 907704522 ps
T799 /workspace/coverage/default/46.sram_ctrl_smoke.2372791144 Jan 03 12:53:46 PM PST 24 Jan 03 12:56:30 PM PST 24 638560992 ps
T800 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3601285344 Jan 03 12:52:50 PM PST 24 Jan 03 01:30:07 PM PST 24 464886213 ps
T801 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1361234029 Jan 03 12:53:00 PM PST 24 Jan 03 12:59:46 PM PST 24 53421781752 ps
T802 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2110533865 Jan 03 12:53:35 PM PST 24 Jan 03 12:54:39 PM PST 24 973906834 ps
T803 /workspace/coverage/default/0.sram_ctrl_mem_walk.2650185854 Jan 03 12:51:06 PM PST 24 Jan 03 12:51:35 PM PST 24 2428355176 ps
T804 /workspace/coverage/default/30.sram_ctrl_smoke.2760161612 Jan 03 12:52:42 PM PST 24 Jan 03 12:53:48 PM PST 24 144616831 ps
T805 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.686761514 Jan 03 12:51:39 PM PST 24 Jan 03 12:51:56 PM PST 24 576169916 ps
T806 /workspace/coverage/default/15.sram_ctrl_bijection.4073549686 Jan 03 12:52:11 PM PST 24 Jan 03 12:52:52 PM PST 24 2066734173 ps
T807 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2996643383 Jan 03 12:52:08 PM PST 24 Jan 03 01:05:19 PM PST 24 8127401157 ps
T808 /workspace/coverage/default/10.sram_ctrl_stress_all.453729626 Jan 03 12:52:10 PM PST 24 Jan 03 01:37:20 PM PST 24 42057125072 ps
T809 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1004507584 Jan 03 12:53:00 PM PST 24 Jan 03 12:56:52 PM PST 24 11270724252 ps
T810 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3615035436 Jan 03 12:50:51 PM PST 24 Jan 03 12:57:33 PM PST 24 56704968056 ps
T811 /workspace/coverage/default/17.sram_ctrl_max_throughput.412824882 Jan 03 12:52:12 PM PST 24 Jan 03 12:53:51 PM PST 24 155645242 ps
T812 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3835420043 Jan 03 12:53:48 PM PST 24 Jan 03 01:04:03 PM PST 24 21039852420 ps
T813 /workspace/coverage/default/33.sram_ctrl_stress_all.2382231811 Jan 03 12:53:50 PM PST 24 Jan 03 01:33:29 PM PST 24 136582545100 ps
T814 /workspace/coverage/default/20.sram_ctrl_multiple_keys.1737790562 Jan 03 12:52:24 PM PST 24 Jan 03 01:07:12 PM PST 24 17946213908 ps
T815 /workspace/coverage/default/42.sram_ctrl_multiple_keys.3256587991 Jan 03 12:53:39 PM PST 24 Jan 03 01:08:45 PM PST 24 10403728095 ps
T816 /workspace/coverage/default/35.sram_ctrl_partial_access.3156145374 Jan 03 12:52:45 PM PST 24 Jan 03 12:54:18 PM PST 24 2513368299 ps
T817 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3235683753 Jan 03 12:53:06 PM PST 24 Jan 03 12:54:05 PM PST 24 215349663 ps
T818 /workspace/coverage/default/41.sram_ctrl_alert_test.762888156 Jan 03 12:53:52 PM PST 24 Jan 03 12:55:16 PM PST 24 28463105 ps
T819 /workspace/coverage/default/42.sram_ctrl_mem_walk.4166537589 Jan 03 12:53:21 PM PST 24 Jan 03 12:54:11 PM PST 24 137341282 ps
T820 /workspace/coverage/default/36.sram_ctrl_partial_access.751517082 Jan 03 12:52:49 PM PST 24 Jan 03 12:55:23 PM PST 24 235852586 ps
T821 /workspace/coverage/default/44.sram_ctrl_smoke.4149548023 Jan 03 12:52:46 PM PST 24 Jan 03 12:55:52 PM PST 24 3350666038 ps
T822 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.485215213 Jan 03 12:52:47 PM PST 24 Jan 03 01:14:24 PM PST 24 845655760 ps
T32 /workspace/coverage/default/2.sram_ctrl_sec_cm.3605642706 Jan 03 12:51:27 PM PST 24 Jan 03 12:51:43 PM PST 24 209947857 ps
T823 /workspace/coverage/default/25.sram_ctrl_multiple_keys.3995583241 Jan 03 12:53:34 PM PST 24 Jan 03 01:01:27 PM PST 24 5632682220 ps
T824 /workspace/coverage/default/26.sram_ctrl_bijection.294162693 Jan 03 12:52:53 PM PST 24 Jan 03 12:54:55 PM PST 24 13402966950 ps
T825 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1638955393 Jan 03 12:53:34 PM PST 24 Jan 03 12:54:48 PM PST 24 86876203 ps
T826 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1256901001 Jan 03 12:52:56 PM PST 24 Jan 03 12:59:49 PM PST 24 164417585010 ps
T827 /workspace/coverage/default/1.sram_ctrl_mem_walk.186007169 Jan 03 12:51:23 PM PST 24 Jan 03 12:51:43 PM PST 24 473362209 ps
T828 /workspace/coverage/default/25.sram_ctrl_regwen.1353114030 Jan 03 12:53:15 PM PST 24 Jan 03 12:56:08 PM PST 24 2185536246 ps
T829 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3617828506 Jan 03 12:53:07 PM PST 24 Jan 03 12:54:46 PM PST 24 3260811932 ps
T830 /workspace/coverage/default/5.sram_ctrl_max_throughput.3686877112 Jan 03 12:51:37 PM PST 24 Jan 03 12:51:54 PM PST 24 223834574 ps
T831 /workspace/coverage/default/11.sram_ctrl_lc_escalation.879703162 Jan 03 12:52:20 PM PST 24 Jan 03 12:53:09 PM PST 24 1610750146 ps
T832 /workspace/coverage/default/16.sram_ctrl_smoke.1913456248 Jan 03 12:52:00 PM PST 24 Jan 03 12:52:20 PM PST 24 4991764205 ps
T833 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3228184713 Jan 03 12:53:35 PM PST 24 Jan 03 12:54:32 PM PST 24 569467844 ps
T834 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2493885820 Jan 03 12:51:44 PM PST 24 Jan 03 12:51:57 PM PST 24 57078570 ps
T835 /workspace/coverage/default/28.sram_ctrl_mem_walk.1331625502 Jan 03 12:53:57 PM PST 24 Jan 03 12:55:30 PM PST 24 892783665 ps
T836 /workspace/coverage/default/29.sram_ctrl_bijection.4061801247 Jan 03 12:52:49 PM PST 24 Jan 03 12:55:28 PM PST 24 31791364058 ps
T837 /workspace/coverage/default/32.sram_ctrl_max_throughput.1017867662 Jan 03 12:52:55 PM PST 24 Jan 03 12:54:21 PM PST 24 169731698 ps
T838 /workspace/coverage/default/49.sram_ctrl_smoke.1978246587 Jan 03 12:53:42 PM PST 24 Jan 03 12:54:58 PM PST 24 809854006 ps
T839 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1063113892 Jan 03 12:52:02 PM PST 24 Jan 03 01:00:44 PM PST 24 8741583363 ps
T84 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3154488533 Jan 03 12:51:45 PM PST 24 Jan 03 12:51:57 PM PST 24 189864425 ps
T840 /workspace/coverage/default/43.sram_ctrl_lc_escalation.3445628598 Jan 03 12:52:53 PM PST 24 Jan 03 12:54:31 PM PST 24 79173806 ps
T841 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3410588271 Jan 03 12:53:12 PM PST 24 Jan 03 01:46:22 PM PST 24 3924317985 ps
T842 /workspace/coverage/default/36.sram_ctrl_alert_test.341383155 Jan 03 12:53:56 PM PST 24 Jan 03 12:55:37 PM PST 24 13794438 ps
T843 /workspace/coverage/default/38.sram_ctrl_max_throughput.3734278645 Jan 03 12:52:45 PM PST 24 Jan 03 12:55:14 PM PST 24 529036530 ps
T844 /workspace/coverage/default/0.sram_ctrl_max_throughput.660099182 Jan 03 12:51:01 PM PST 24 Jan 03 12:51:34 PM PST 24 572219918 ps
T845 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1405120796 Jan 03 12:51:36 PM PST 24 Jan 03 01:07:47 PM PST 24 6247188239 ps
T846 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2468712640 Jan 03 12:53:14 PM PST 24 Jan 03 01:00:00 PM PST 24 15658655728 ps
T847 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2539527145 Jan 03 12:53:39 PM PST 24 Jan 03 02:09:12 PM PST 24 1251017297 ps
T848 /workspace/coverage/default/26.sram_ctrl_stress_all.3139075312 Jan 03 12:53:13 PM PST 24 Jan 03 01:37:30 PM PST 24 54692648330 ps
T849 /workspace/coverage/default/23.sram_ctrl_multiple_keys.3948078211 Jan 03 12:53:03 PM PST 24 Jan 03 12:58:39 PM PST 24 1803055066 ps
T850 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3515012517 Jan 03 12:53:36 PM PST 24 Jan 03 01:05:37 PM PST 24 2458619737 ps
T851 /workspace/coverage/default/6.sram_ctrl_alert_test.2057383829 Jan 03 12:51:21 PM PST 24 Jan 03 12:51:38 PM PST 24 36890109 ps
T852 /workspace/coverage/default/41.sram_ctrl_partial_access.708362788 Jan 03 12:53:40 PM PST 24 Jan 03 12:54:46 PM PST 24 239381705 ps
T853 /workspace/coverage/default/31.sram_ctrl_mem_walk.3187257194 Jan 03 12:53:01 PM PST 24 Jan 03 12:54:29 PM PST 24 290695703 ps
T854 /workspace/coverage/default/26.sram_ctrl_smoke.3805186678 Jan 03 12:53:35 PM PST 24 Jan 03 12:54:43 PM PST 24 1016813502 ps
T855 /workspace/coverage/default/46.sram_ctrl_stress_all.219766180 Jan 03 12:53:44 PM PST 24 Jan 03 01:37:05 PM PST 24 87746095256 ps
T856 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4285075858 Jan 03 12:52:13 PM PST 24 Jan 03 01:15:16 PM PST 24 9495398183 ps
T857 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1621741809 Jan 03 12:52:02 PM PST 24 Jan 03 01:18:30 PM PST 24 950243190 ps
T858 /workspace/coverage/default/20.sram_ctrl_mem_walk.2651718658 Jan 03 12:52:19 PM PST 24 Jan 03 12:53:02 PM PST 24 233553853 ps
T859 /workspace/coverage/default/24.sram_ctrl_multiple_keys.188652143 Jan 03 12:53:13 PM PST 24 Jan 03 12:56:03 PM PST 24 553556666 ps
T860 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.541051629 Jan 03 12:52:06 PM PST 24 Jan 03 01:18:05 PM PST 24 280805658 ps
T861 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2688961322 Jan 03 12:52:53 PM PST 24 Jan 03 12:54:15 PM PST 24 42711279 ps
T862 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1894487314 Jan 03 12:53:49 PM PST 24 Jan 03 12:56:51 PM PST 24 159902427 ps
T863 /workspace/coverage/default/38.sram_ctrl_ram_cfg.3083281420 Jan 03 12:52:57 PM PST 24 Jan 03 12:54:10 PM PST 24 79711470 ps
T864 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1611863829 Jan 03 12:53:50 PM PST 24 Jan 03 12:59:55 PM PST 24 22873258447 ps
T865 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1383156369 Jan 03 12:52:45 PM PST 24 Jan 03 12:54:22 PM PST 24 2381967839 ps
T866 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.630738782 Jan 03 12:53:38 PM PST 24 Jan 03 12:59:25 PM PST 24 7612083645 ps
T867 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2830439415 Jan 03 12:53:51 PM PST 24 Jan 03 01:08:56 PM PST 24 4587848184 ps
T868 /workspace/coverage/default/4.sram_ctrl_max_throughput.2319325762 Jan 03 12:51:31 PM PST 24 Jan 03 12:53:01 PM PST 24 473243865 ps
T869 /workspace/coverage/default/14.sram_ctrl_ram_cfg.807017757 Jan 03 12:52:07 PM PST 24 Jan 03 12:52:15 PM PST 24 119125577 ps
T870 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2948023141 Jan 03 12:50:46 PM PST 24 Jan 03 01:04:28 PM PST 24 5901979216 ps
T871 /workspace/coverage/default/45.sram_ctrl_regwen.3883722766 Jan 03 12:53:35 PM PST 24 Jan 03 01:01:46 PM PST 24 13427248974 ps
T872 /workspace/coverage/default/11.sram_ctrl_executable.2197152282 Jan 03 12:52:15 PM PST 24 Jan 03 01:02:02 PM PST 24 44725481615 ps
T873 /workspace/coverage/default/10.sram_ctrl_alert_test.3078210847 Jan 03 12:52:04 PM PST 24 Jan 03 12:52:10 PM PST 24 14033197 ps
T874 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3874331779 Jan 03 12:53:40 PM PST 24 Jan 03 12:56:21 PM PST 24 572477595 ps
T875 /workspace/coverage/default/24.sram_ctrl_alert_test.395205935 Jan 03 12:53:34 PM PST 24 Jan 03 12:54:30 PM PST 24 76742203 ps
T876 /workspace/coverage/default/14.sram_ctrl_regwen.1239689306 Jan 03 12:52:27 PM PST 24 Jan 03 01:00:42 PM PST 24 15617455700 ps
T877 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.230564261 Jan 03 12:52:27 PM PST 24 Jan 03 12:54:49 PM PST 24 155645645 ps
T878 /workspace/coverage/default/30.sram_ctrl_bijection.595794883 Jan 03 12:52:58 PM PST 24 Jan 03 12:54:56 PM PST 24 1876533352 ps
T879 /workspace/coverage/default/33.sram_ctrl_partial_access.4210129866 Jan 03 12:53:09 PM PST 24 Jan 03 12:54:02 PM PST 24 60432318 ps
T880 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1279302739 Jan 03 12:53:37 PM PST 24 Jan 03 01:24:38 PM PST 24 4375456356 ps
T881 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3995969527 Jan 03 12:52:44 PM PST 24 Jan 03 01:19:03 PM PST 24 19123492114 ps
T882 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1583870076 Jan 03 12:52:20 PM PST 24 Jan 03 01:01:41 PM PST 24 8543106405 ps
T883 /workspace/coverage/default/46.sram_ctrl_regwen.470681480 Jan 03 12:53:08 PM PST 24 Jan 03 12:57:20 PM PST 24 1015276841 ps
T884 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.517277876 Jan 03 12:51:35 PM PST 24 Jan 03 12:55:09 PM PST 24 8014031905 ps
T885 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3912828548 Jan 03 12:52:54 PM PST 24 Jan 03 12:54:11 PM PST 24 1026837751 ps
T886 /workspace/coverage/default/29.sram_ctrl_executable.1857690665 Jan 03 12:52:48 PM PST 24 Jan 03 01:07:54 PM PST 24 86222993552 ps
T887 /workspace/coverage/default/19.sram_ctrl_alert_test.1792734078 Jan 03 12:52:19 PM PST 24 Jan 03 12:52:47 PM PST 24 16681744 ps
T888 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.435554227 Jan 03 12:52:08 PM PST 24 Jan 03 12:52:22 PM PST 24 125879628 ps
T889 /workspace/coverage/default/20.sram_ctrl_alert_test.4129745784 Jan 03 12:52:17 PM PST 24 Jan 03 12:52:44 PM PST 24 13582460 ps
T890 /workspace/coverage/default/20.sram_ctrl_bijection.4065730257 Jan 03 12:52:04 PM PST 24 Jan 03 12:53:00 PM PST 24 761809763 ps
T891 /workspace/coverage/default/27.sram_ctrl_executable.2542908336 Jan 03 12:53:13 PM PST 24 Jan 03 01:06:59 PM PST 24 13287477316 ps
T892 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3483372712 Jan 03 12:52:14 PM PST 24 Jan 03 12:59:51 PM PST 24 16661063400 ps
T893 /workspace/coverage/default/22.sram_ctrl_multiple_keys.4128342080 Jan 03 12:53:14 PM PST 24 Jan 03 12:55:10 PM PST 24 7804074307 ps
T894 /workspace/coverage/default/49.sram_ctrl_regwen.946769254 Jan 03 12:53:44 PM PST 24 Jan 03 01:01:23 PM PST 24 8972291489 ps
T895 /workspace/coverage/default/25.sram_ctrl_partial_access.1297433411 Jan 03 12:53:34 PM PST 24 Jan 03 12:55:45 PM PST 24 992018471 ps
T896 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2014020017 Jan 03 12:52:52 PM PST 24 Jan 03 12:55:15 PM PST 24 137722160 ps
T897 /workspace/coverage/default/41.sram_ctrl_bijection.2367859192 Jan 03 12:52:54 PM PST 24 Jan 03 12:54:47 PM PST 24 12085152918 ps
T898 /workspace/coverage/default/39.sram_ctrl_partial_access.3697278422 Jan 03 12:53:14 PM PST 24 Jan 03 12:54:48 PM PST 24 2114745527 ps
T899 /workspace/coverage/default/33.sram_ctrl_regwen.595668310 Jan 03 12:53:28 PM PST 24 Jan 03 01:07:56 PM PST 24 10849276902 ps
T900 /workspace/coverage/default/2.sram_ctrl_alert_test.1172192594 Jan 03 12:51:06 PM PST 24 Jan 03 12:51:25 PM PST 24 13752349 ps
T901 /workspace/coverage/default/22.sram_ctrl_mem_walk.2210150619 Jan 03 12:53:04 PM PST 24 Jan 03 12:54:08 PM PST 24 135627163 ps
T902 /workspace/coverage/default/48.sram_ctrl_smoke.1192927826 Jan 03 12:53:38 PM PST 24 Jan 03 12:54:46 PM PST 24 997448463 ps
T903 /workspace/coverage/default/45.sram_ctrl_alert_test.1356584354 Jan 03 12:53:20 PM PST 24 Jan 03 12:54:21 PM PST 24 34759020 ps
T904 /workspace/coverage/default/44.sram_ctrl_multiple_keys.2648911128 Jan 03 12:53:10 PM PST 24 Jan 03 01:02:46 PM PST 24 16130412576 ps
T905 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2128650152 Jan 03 12:52:05 PM PST 24 Jan 03 12:55:52 PM PST 24 3061020669 ps
T906 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3761433126 Jan 03 12:53:09 PM PST 24 Jan 03 01:07:49 PM PST 24 17686130445 ps
T907 /workspace/coverage/default/42.sram_ctrl_partial_access.1969248018 Jan 03 12:53:39 PM PST 24 Jan 03 12:55:32 PM PST 24 332161216 ps
T908 /workspace/coverage/default/23.sram_ctrl_alert_test.1165687638 Jan 03 12:52:43 PM PST 24 Jan 03 12:54:15 PM PST 24 13673006 ps
T909 /workspace/coverage/default/2.sram_ctrl_regwen.84728837 Jan 03 12:51:10 PM PST 24 Jan 03 12:53:25 PM PST 24 1184412639 ps
T910 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3684938959 Jan 03 12:52:19 PM PST 24 Jan 03 12:53:02 PM PST 24 55324545 ps
T911 /workspace/coverage/default/24.sram_ctrl_regwen.332556490 Jan 03 12:53:00 PM PST 24 Jan 03 01:07:50 PM PST 24 53968350606 ps
T912 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.836174623 Jan 03 12:52:54 PM PST 24 Jan 03 12:54:18 PM PST 24 176508229 ps
T913 /workspace/coverage/default/31.sram_ctrl_partial_access.3168658067 Jan 03 12:53:39 PM PST 24 Jan 03 12:55:00 PM PST 24 189226751 ps
T914 /workspace/coverage/default/34.sram_ctrl_max_throughput.3476461548 Jan 03 12:53:45 PM PST 24 Jan 03 12:55:04 PM PST 24 687775001 ps
T915 /workspace/coverage/default/19.sram_ctrl_regwen.769366224 Jan 03 12:52:13 PM PST 24 Jan 03 01:08:16 PM PST 24 3645399405 ps
T916 /workspace/coverage/default/33.sram_ctrl_alert_test.1937719336 Jan 03 12:53:16 PM PST 24 Jan 03 12:54:01 PM PST 24 34673971 ps
T917 /workspace/coverage/default/11.sram_ctrl_multiple_keys.745052560 Jan 03 12:52:23 PM PST 24 Jan 03 01:09:35 PM PST 24 12674763006 ps
T918 /workspace/coverage/default/35.sram_ctrl_executable.3863993553 Jan 03 12:53:45 PM PST 24 Jan 03 01:04:48 PM PST 24 10545502561 ps
T919 /workspace/coverage/default/48.sram_ctrl_max_throughput.1801431166 Jan 03 12:53:36 PM PST 24 Jan 03 12:56:22 PM PST 24 472968514 ps
T920 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1278963744 Jan 03 12:52:54 PM PST 24 Jan 03 01:12:56 PM PST 24 3960543845 ps
T921 /workspace/coverage/default/28.sram_ctrl_lc_escalation.61052381 Jan 03 12:53:36 PM PST 24 Jan 03 12:54:43 PM PST 24 5000778747 ps
T922 /workspace/coverage/default/2.sram_ctrl_executable.2961862079 Jan 03 12:51:02 PM PST 24 Jan 03 12:53:17 PM PST 24 1628415005 ps
T923 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3921734220 Jan 03 12:53:19 PM PST 24 Jan 03 02:20:52 PM PST 24 7953345553 ps
T924 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3796684246 Jan 03 12:51:40 PM PST 24 Jan 03 12:51:56 PM PST 24 590050656 ps
T925 /workspace/coverage/default/3.sram_ctrl_lc_escalation.2379892669 Jan 03 12:51:36 PM PST 24 Jan 03 12:51:52 PM PST 24 1268587988 ps
T926 /workspace/coverage/default/1.sram_ctrl_ram_cfg.4162840941 Jan 03 12:50:47 PM PST 24 Jan 03 12:51:11 PM PST 24 124742056 ps
T927 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1237906569 Jan 03 12:52:06 PM PST 24 Jan 03 12:52:13 PM PST 24 90003122 ps
T928 /workspace/coverage/default/7.sram_ctrl_smoke.3110754913 Jan 03 12:51:37 PM PST 24 Jan 03 12:51:58 PM PST 24 161325599 ps
T929 /workspace/coverage/default/43.sram_ctrl_regwen.3222669953 Jan 03 12:53:00 PM PST 24 Jan 03 12:57:18 PM PST 24 2296076018 ps
T930 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1048563297 Jan 03 12:50:47 PM PST 24 Jan 03 01:00:48 PM PST 24 6102351298 ps
T931 /workspace/coverage/default/10.sram_ctrl_mem_walk.3826321342 Jan 03 12:51:59 PM PST 24 Jan 03 12:52:07 PM PST 24 283729449 ps
T932 /workspace/coverage/default/0.sram_ctrl_smoke.3593149749 Jan 03 12:51:13 PM PST 24 Jan 03 12:53:00 PM PST 24 2736570576 ps
T933 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3975898630 Jan 03 12:51:40 PM PST 24 Jan 03 12:56:00 PM PST 24 10902118360 ps
T934 /workspace/coverage/default/48.sram_ctrl_executable.807176064 Jan 03 12:53:18 PM PST 24 Jan 03 01:02:52 PM PST 24 36603988553 ps
T935 /workspace/coverage/default/10.sram_ctrl_ram_cfg.1929743386 Jan 03 12:52:11 PM PST 24 Jan 03 12:52:32 PM PST 24 41551954 ps
T33 /workspace/coverage/default/1.sram_ctrl_sec_cm.3435154900 Jan 03 12:51:00 PM PST 24 Jan 03 12:51:22 PM PST 24 399537821 ps
T936 /workspace/coverage/default/45.sram_ctrl_smoke.256882565 Jan 03 12:53:37 PM PST 24 Jan 03 12:54:34 PM PST 24 1328023380 ps
T937 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3351095734 Jan 03 12:53:32 PM PST 24 Jan 03 12:54:28 PM PST 24 63342790 ps
T938 /workspace/coverage/default/4.sram_ctrl_lc_escalation.3283249062 Jan 03 12:51:48 PM PST 24 Jan 03 12:52:04 PM PST 24 1104164629 ps
T939 /workspace/coverage/default/1.sram_ctrl_stress_all.494724935 Jan 03 12:51:00 PM PST 24 Jan 03 01:29:07 PM PST 24 278355564525 ps
T940 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2549789558 Jan 03 12:51:15 PM PST 24 Jan 03 01:00:38 PM PST 24 16708347273 ps
T941 /workspace/coverage/default/18.sram_ctrl_stress_all.3066387211 Jan 03 12:52:24 PM PST 24 Jan 03 01:43:50 PM PST 24 15810398897 ps
T942 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1525322140 Jan 03 12:52:05 PM PST 24 Jan 03 12:55:44 PM PST 24 2232998874 ps
T943 /workspace/coverage/default/16.sram_ctrl_alert_test.1619570419 Jan 03 12:52:05 PM PST 24 Jan 03 12:52:11 PM PST 24 110287546 ps
T944 /workspace/coverage/default/27.sram_ctrl_lc_escalation.3754865070 Jan 03 12:52:59 PM PST 24 Jan 03 12:54:13 PM PST 24 1480458571 ps
T945 /workspace/coverage/default/2.sram_ctrl_smoke.3577480110 Jan 03 12:51:13 PM PST 24 Jan 03 12:51:35 PM PST 24 230992112 ps
T946 /workspace/coverage/default/3.sram_ctrl_alert_test.23013931 Jan 03 12:51:43 PM PST 24 Jan 03 12:51:54 PM PST 24 35837630 ps
T947 /workspace/coverage/default/4.sram_ctrl_smoke.1225378363 Jan 03 12:51:26 PM PST 24 Jan 03 12:51:42 PM PST 24 94282264 ps
T948 /workspace/coverage/default/34.sram_ctrl_partial_access.3268148214 Jan 03 12:53:51 PM PST 24 Jan 03 12:55:22 PM PST 24 619346992 ps
T949 /workspace/coverage/default/13.sram_ctrl_stress_all.1946023500 Jan 03 12:52:05 PM PST 24 Jan 03 01:29:07 PM PST 24 31975710207 ps
T950 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4184690500 Jan 03 12:53:17 PM PST 24 Jan 03 12:54:10 PM PST 24 226904974 ps
T951 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1243880326 Jan 03 12:53:05 PM PST 24 Jan 03 12:54:08 PM PST 24 585833239 ps
T952 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2645467846 Jan 03 12:52:45 PM PST 24 Jan 03 01:06:17 PM PST 24 2816163168 ps
T953 /workspace/coverage/default/47.sram_ctrl_mem_walk.2020647531 Jan 03 12:53:36 PM PST 24 Jan 03 12:54:43 PM PST 24 1323979554 ps
T954 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2960941068 Jan 03 12:52:15 PM PST 24 Jan 03 01:50:21 PM PST 24 1006023307 ps
T955 /workspace/coverage/default/42.sram_ctrl_alert_test.2794600580 Jan 03 12:53:07 PM PST 24 Jan 03 12:54:30 PM PST 24 17437506 ps
T956 /workspace/coverage/default/19.sram_ctrl_mem_walk.2585889063 Jan 03 12:52:04 PM PST 24 Jan 03 12:52:17 PM PST 24 272719826 ps
T957 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2825487117 Jan 03 12:53:56 PM PST 24 Jan 03 12:56:33 PM PST 24 144745710 ps
T958 /workspace/coverage/default/40.sram_ctrl_smoke.529086852 Jan 03 12:52:53 PM PST 24 Jan 03 12:54:08 PM PST 24 179849223 ps
T959 /workspace/coverage/default/23.sram_ctrl_smoke.1506624609 Jan 03 12:52:48 PM PST 24 Jan 03 12:54:42 PM PST 24 1260089269 ps
T960 /workspace/coverage/default/9.sram_ctrl_lc_escalation.1865712435 Jan 03 12:52:11 PM PST 24 Jan 03 12:52:29 PM PST 24 1171666792 ps
T961 /workspace/coverage/default/23.sram_ctrl_executable.3804109736 Jan 03 12:53:32 PM PST 24 Jan 03 01:08:26 PM PST 24 8070045207 ps
T962 /workspace/coverage/default/35.sram_ctrl_smoke.3144209519 Jan 03 12:53:08 PM PST 24 Jan 03 12:54:14 PM PST 24 1195446076 ps
T963 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4139697091 Jan 03 12:52:19 PM PST 24 Jan 03 02:22:16 PM PST 24 1932724139 ps
T964 /workspace/coverage/default/45.sram_ctrl_max_throughput.2513676800 Jan 03 12:53:47 PM PST 24 Jan 03 12:55:10 PM PST 24 133249961 ps
T965 /workspace/coverage/default/5.sram_ctrl_mem_walk.515919855 Jan 03 12:51:35 PM PST 24 Jan 03 12:51:51 PM PST 24 308709176 ps
T966 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2841067547 Jan 03 12:52:57 PM PST 24 Jan 03 12:54:29 PM PST 24 172713576 ps
T967 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2915627763 Jan 03 12:52:52 PM PST 24 Jan 03 01:03:31 PM PST 24 3230319631 ps
T968 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3223181662 Jan 03 12:51:40 PM PST 24 Jan 03 12:56:46 PM PST 24 6289595718 ps
T969 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2067481362 Jan 03 12:52:16 PM PST 24 Jan 03 12:56:30 PM PST 24 1055391649 ps
T970 /workspace/coverage/default/15.sram_ctrl_executable.1408261516 Jan 03 12:52:17 PM PST 24 Jan 03 01:17:25 PM PST 24 63862670998 ps
T971 /workspace/coverage/default/9.sram_ctrl_smoke.1120409334 Jan 03 12:51:59 PM PST 24 Jan 03 12:52:58 PM PST 24 1907575097 ps
T972 /workspace/coverage/default/37.sram_ctrl_bijection.3476574101 Jan 03 12:53:13 PM PST 24 Jan 03 12:55:05 PM PST 24 24600722500 ps
T973 /workspace/coverage/default/15.sram_ctrl_multiple_keys.2582398615 Jan 03 12:52:11 PM PST 24 Jan 03 01:11:10 PM PST 24 74188420370 ps
T974 /workspace/coverage/default/4.sram_ctrl_stress_all.2837406127 Jan 03 12:51:50 PM PST 24 Jan 03 01:29:44 PM PST 24 71047731204 ps
T975 /workspace/coverage/default/25.sram_ctrl_smoke.1857373710 Jan 03 12:53:39 PM PST 24 Jan 03 12:55:11 PM PST 24 1601527171 ps
T976 /workspace/coverage/default/13.sram_ctrl_multiple_keys.203776765 Jan 03 12:52:17 PM PST 24 Jan 03 12:57:00 PM PST 24 27273317170 ps
T977 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1349517233 Jan 03 12:51:29 PM PST 24 Jan 03 12:58:23 PM PST 24 2350694531 ps
T978 /workspace/coverage/default/18.sram_ctrl_partial_access.3883964932 Jan 03 12:52:25 PM PST 24 Jan 03 12:53:31 PM PST 24 180363160 ps
T979 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2224825935 Jan 03 12:51:04 PM PST 24 Jan 03 12:55:32 PM PST 24 24123271011 ps
T980 /workspace/coverage/default/10.sram_ctrl_executable.2507833979 Jan 03 12:51:59 PM PST 24 Jan 03 01:02:29 PM PST 24 2851172266 ps
T981 /workspace/coverage/default/0.sram_ctrl_regwen.4033011153 Jan 03 12:51:01 PM PST 24 Jan 03 01:01:58 PM PST 24 15858715846 ps
T982 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.303641521 Jan 03 12:52:10 PM PST 24 Jan 03 01:18:59 PM PST 24 2268468944 ps
T983 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3396220301 Jan 03 12:51:13 PM PST 24 Jan 03 12:51:32 PM PST 24 31660257 ps
T984 /workspace/coverage/default/48.sram_ctrl_mem_walk.3940483916 Jan 03 12:53:44 PM PST 24 Jan 03 12:55:19 PM PST 24 5665381415 ps
T985 /workspace/coverage/default/5.sram_ctrl_alert_test.2822271907 Jan 03 12:51:48 PM PST 24 Jan 03 12:51:57 PM PST 24 13870747 ps
T986 /workspace/coverage/default/8.sram_ctrl_bijection.2534182655 Jan 03 12:51:36 PM PST 24 Jan 03 12:52:18 PM PST 24 8140800641 ps
T987 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2921562537 Jan 03 12:53:31 PM PST 24 Jan 03 12:54:27 PM PST 24 93306717 ps
T988 /workspace/coverage/default/2.sram_ctrl_mem_walk.1196433587 Jan 03 12:51:08 PM PST 24 Jan 03 12:51:32 PM PST 24 1320749202 ps
T989 /workspace/coverage/default/10.sram_ctrl_max_throughput.1376389751 Jan 03 12:52:00 PM PST 24 Jan 03 12:52:25 PM PST 24 497267022 ps

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2286508364
Short name T11
Test name
Test status
Simulation time 2330259727 ps
CPU time 3015.06 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 01:44:27 PM PST 24
Peak memory 427940 kb
Host smart-45187a8c-c82b-4649-9052-26ccfa009649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2286508364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2286508364
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1653592832
Short name T25
Test name
Test status
Simulation time 21712133306 ps
CPU time 3219.12 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 01:48:14 PM PST 24
Peak memory 375776 kb
Host smart-853ecb01-f0e1-4f80-8d58-26d3be63866a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653592832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1653592832
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.810881151
Short name T43
Test name
Test status
Simulation time 178387772 ps
CPU time 2.22 seconds
Started Jan 03 12:30:14 PM PST 24
Finished Jan 03 12:31:04 PM PST 24
Peak memory 201568 kb
Host smart-a6a67179-29df-4f67-bf9d-1f4651923177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810881151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.sram_ctrl_tl_intg_err.810881151
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.1184047677
Short name T55
Test name
Test status
Simulation time 588543507 ps
CPU time 81.4 seconds
Started Jan 03 12:53:28 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 339412 kb
Host smart-54377974-caff-47ce-b863-5ca0f66a1515
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184047677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.1184047677
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3496016575
Short name T23
Test name
Test status
Simulation time 442157472 ps
CPU time 3.4 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 221352 kb
Host smart-5868bd5c-025a-4f85-930e-e51676d1de56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496016575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3496016575
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3584572692
Short name T109
Test name
Test status
Simulation time 46693517338 ps
CPU time 2515.12 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 01:36:20 PM PST 24
Peak memory 376716 kb
Host smart-e0f10f4f-f722-407c-a96f-10fb4e8f68c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584572692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3584572692
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.163111859
Short name T8
Test name
Test status
Simulation time 246847276 ps
CPU time 4.53 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 215952 kb
Host smart-78252ade-5f3a-4d52-b189-e4237042785b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163111859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_mem_partial_access.163111859
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3406833482
Short name T61
Test name
Test status
Simulation time 444703580 ps
CPU time 2.72 seconds
Started Jan 03 12:42:49 PM PST 24
Finished Jan 03 12:44:27 PM PST 24
Peak memory 201564 kb
Host smart-284c1cb2-29cb-489b-8651-574358584922
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406833482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3406833482
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.552671115
Short name T13
Test name
Test status
Simulation time 25037747525 ps
CPU time 258.73 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:58:18 PM PST 24
Peak memory 202892 kb
Host smart-547d47b9-b161-4c25-a06c-d99f6cbc15cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552671115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.552671115
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.3407339284
Short name T2
Test name
Test status
Simulation time 147091739964 ps
CPU time 2164.17 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 01:30:13 PM PST 24
Peak memory 376844 kb
Host smart-a9085c3c-08bd-45ad-bf5e-8de71fe762b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407339284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.3407339284
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.4001321307
Short name T12
Test name
Test status
Simulation time 45085016 ps
CPU time 0.82 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202832 kb
Host smart-d73d3b1d-e8bb-4560-9546-e12d26a3446e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001321307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4001321307
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3380791448
Short name T101
Test name
Test status
Simulation time 104946399 ps
CPU time 1.37 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:36 PM PST 24
Peak memory 201548 kb
Host smart-9ca616e3-8219-4999-8e15-3f9efd538325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380791448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3380791448
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3307229013
Short name T102
Test name
Test status
Simulation time 191262814 ps
CPU time 2.02 seconds
Started Jan 03 12:30:26 PM PST 24
Finished Jan 03 12:31:25 PM PST 24
Peak memory 200808 kb
Host smart-14cbf5ea-a12e-403e-b4a8-088feed047d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307229013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3307229013
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3433227227
Short name T320
Test name
Test status
Simulation time 57792152 ps
CPU time 0.65 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 202688 kb
Host smart-d0395f04-a6f1-4415-954a-c7f4113db35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433227227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3433227227
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2027792638
Short name T338
Test name
Test status
Simulation time 1277660575 ps
CPU time 352.56 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:58:02 PM PST 24
Peak memory 371548 kb
Host smart-eaa96f58-7427-46b5-85dc-8919d5a18514
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027792638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2027792638
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3588204671
Short name T166
Test name
Test status
Simulation time 36522318 ps
CPU time 0.62 seconds
Started Jan 03 12:29:47 PM PST 24
Finished Jan 03 12:30:29 PM PST 24
Peak memory 200576 kb
Host smart-7087ea4e-3c43-4597-92a9-05825c73db9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588204671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.3588204671
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2829023554
Short name T62
Test name
Test status
Simulation time 129163047 ps
CPU time 1.7 seconds
Started Jan 03 12:23:46 PM PST 24
Finished Jan 03 12:23:48 PM PST 24
Peak memory 201784 kb
Host smart-1f511df9-df79-4ed9-9414-0d2d1f7b1f34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829023554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2829023554
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2724419795
Short name T181
Test name
Test status
Simulation time 30120815 ps
CPU time 0.63 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:10 PM PST 24
Peak memory 200892 kb
Host smart-d5a970bb-bb2a-4ff7-b577-7bec372a1efb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724419795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.2724419795
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2823037004
Short name T48
Test name
Test status
Simulation time 103441736 ps
CPU time 0.94 seconds
Started Jan 03 12:24:54 PM PST 24
Finished Jan 03 12:24:56 PM PST 24
Peak memory 201836 kb
Host smart-33a02d4c-3e97-4f61-a0f7-3d87119b04a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823037004 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2823037004
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3392755584
Short name T198
Test name
Test status
Simulation time 16236128 ps
CPU time 0.72 seconds
Started Jan 03 12:30:17 PM PST 24
Finished Jan 03 12:31:09 PM PST 24
Peak memory 200848 kb
Host smart-e78f7bd8-6b76-44ab-b95e-1ebac825d14a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392755584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3392755584
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.541016010
Short name T164
Test name
Test status
Simulation time 281339327 ps
CPU time 3.06 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:12 PM PST 24
Peak memory 201604 kb
Host smart-2e526212-e9dd-41e7-840d-de51eca0cccf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541016010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.541016010
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.674650616
Short name T65
Test name
Test status
Simulation time 63143895 ps
CPU time 0.7 seconds
Started Jan 03 12:22:39 PM PST 24
Finished Jan 03 12:22:40 PM PST 24
Peak memory 201744 kb
Host smart-3aec3dc4-9541-4d60-b801-f290f60d0e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674650616 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.674650616
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1312840109
Short name T213
Test name
Test status
Simulation time 98639431 ps
CPU time 3.08 seconds
Started Jan 03 12:27:30 PM PST 24
Finished Jan 03 12:27:38 PM PST 24
Peak memory 201068 kb
Host smart-a65bbefc-8a8d-40d0-b5c9-c348ad9a535d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312840109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.1312840109
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1910267834
Short name T100
Test name
Test status
Simulation time 653128026 ps
CPU time 2.26 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:11 PM PST 24
Peak memory 201416 kb
Host smart-d1361057-3663-4cb7-9832-68844451bbae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910267834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1910267834
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4043489605
Short name T187
Test name
Test status
Simulation time 15131875 ps
CPU time 0.64 seconds
Started Jan 03 12:31:05 PM PST 24
Finished Jan 03 12:32:13 PM PST 24
Peak memory 201124 kb
Host smart-d0903df0-2847-48f2-9d81-4bbb1d7c9f98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043489605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.4043489605
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3488079778
Short name T138
Test name
Test status
Simulation time 62851643 ps
CPU time 1.15 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 12:30:09 PM PST 24
Peak memory 201520 kb
Host smart-d5977b2a-50be-499f-a5f4-27c2475f5b33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488079778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3488079778
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1812135033
Short name T149
Test name
Test status
Simulation time 41129390 ps
CPU time 0.8 seconds
Started Jan 03 12:23:52 PM PST 24
Finished Jan 03 12:23:53 PM PST 24
Peak memory 201620 kb
Host smart-39e20db2-5926-43fc-b098-3c41550d1ea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812135033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1812135033
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3050987150
Short name T180
Test name
Test status
Simulation time 50335819 ps
CPU time 1.78 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 209892 kb
Host smart-6b98e61a-1f61-4bb4-be29-f1dcf40def7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050987150 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3050987150
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3140007067
Short name T64
Test name
Test status
Simulation time 14973602 ps
CPU time 0.63 seconds
Started Jan 03 12:42:02 PM PST 24
Finished Jan 03 12:43:38 PM PST 24
Peak memory 201364 kb
Host smart-3fc06278-c0d4-4fe3-9b76-8433b45f5cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140007067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3140007067
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1674894688
Short name T76
Test name
Test status
Simulation time 219445167 ps
CPU time 2.67 seconds
Started Jan 03 12:33:16 PM PST 24
Finished Jan 03 12:34:29 PM PST 24
Peak memory 200864 kb
Host smart-240e10aa-1d42-4ff9-89bf-9c8f3c89b37e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674894688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1674894688
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1074419557
Short name T87
Test name
Test status
Simulation time 85836731 ps
CPU time 0.75 seconds
Started Jan 03 12:29:33 PM PST 24
Finished Jan 03 12:30:09 PM PST 24
Peak memory 201328 kb
Host smart-3b766ee2-f4fd-444b-9fa6-8802a7ede73a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074419557 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1074419557
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1099977191
Short name T196
Test name
Test status
Simulation time 29200035 ps
CPU time 2.27 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 200828 kb
Host smart-706b5d89-a536-4d2e-9b65-54303b0af60b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099977191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.1099977191
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3597253668
Short name T147
Test name
Test status
Simulation time 36497048 ps
CPU time 2.61 seconds
Started Jan 03 12:44:26 PM PST 24
Finished Jan 03 12:45:54 PM PST 24
Peak memory 210368 kb
Host smart-facf05c3-ee6d-4622-96d1-3ec4ab8b2a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597253668 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3597253668
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3975942118
Short name T208
Test name
Test status
Simulation time 31518720 ps
CPU time 0.67 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:30:35 PM PST 24
Peak memory 200456 kb
Host smart-4fc47653-acfd-4992-b4d6-e43616ea4122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975942118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.3975942118
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3450355673
Short name T88
Test name
Test status
Simulation time 1385339164 ps
CPU time 10.35 seconds
Started Jan 03 12:23:47 PM PST 24
Finished Jan 03 12:23:59 PM PST 24
Peak memory 202072 kb
Host smart-31c2122d-c705-44da-9329-53eed37ea083
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450355673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3450355673
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2515732193
Short name T173
Test name
Test status
Simulation time 13784627 ps
CPU time 0.71 seconds
Started Jan 03 12:29:05 PM PST 24
Finished Jan 03 12:29:33 PM PST 24
Peak memory 200536 kb
Host smart-5cc1f671-00e9-4046-b645-904e93c5e9d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515732193 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2515732193
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4036277924
Short name T205
Test name
Test status
Simulation time 201230554 ps
CPU time 1.8 seconds
Started Jan 03 12:30:12 PM PST 24
Finished Jan 03 12:31:00 PM PST 24
Peak memory 201484 kb
Host smart-a1a8b1ac-52fc-46c3-8129-5fdd972b0d53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036277924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.4036277924
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.748449485
Short name T29
Test name
Test status
Simulation time 113919720 ps
CPU time 1.52 seconds
Started Jan 03 12:23:46 PM PST 24
Finished Jan 03 12:23:48 PM PST 24
Peak memory 201912 kb
Host smart-94f3df40-92a6-48a1-a0a9-8bc0ae976c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748449485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.sram_ctrl_tl_intg_err.748449485
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.969301239
Short name T210
Test name
Test status
Simulation time 51729992 ps
CPU time 1.04 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:35 PM PST 24
Peak memory 201384 kb
Host smart-b3f2f2a3-c1e9-447a-8fd1-61e456d07de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969301239 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.969301239
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.240334738
Short name T195
Test name
Test status
Simulation time 13719324 ps
CPU time 0.63 seconds
Started Jan 03 12:29:45 PM PST 24
Finished Jan 03 12:30:26 PM PST 24
Peak memory 200560 kb
Host smart-96f878a7-e73c-444f-9f16-df4833d04b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240334738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_csr_rw.240334738
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.993855239
Short name T71
Test name
Test status
Simulation time 824696556 ps
CPU time 3.22 seconds
Started Jan 03 12:32:32 PM PST 24
Finished Jan 03 12:34:04 PM PST 24
Peak memory 201728 kb
Host smart-eca7afff-2998-4d10-ac39-fb699dd434ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993855239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.993855239
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4066065804
Short name T163
Test name
Test status
Simulation time 19882910 ps
CPU time 0.77 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 200108 kb
Host smart-b43eae59-a36f-4fbf-a63c-1d50b51f9fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066065804 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.4066065804
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4180790500
Short name T51
Test name
Test status
Simulation time 1022186894 ps
CPU time 3.25 seconds
Started Jan 03 12:47:43 PM PST 24
Finished Jan 03 12:48:28 PM PST 24
Peak memory 201932 kb
Host smart-803b0749-64e4-48f6-84dc-a25dd81e9ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180790500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.4180790500
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.479630120
Short name T185
Test name
Test status
Simulation time 501521659 ps
CPU time 1.4 seconds
Started Jan 03 12:32:39 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 201660 kb
Host smart-f40ac40f-1595-4dc6-a4dd-ce7e36d2ba05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479630120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.479630120
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2938114980
Short name T47
Test name
Test status
Simulation time 44093432 ps
CPU time 1.47 seconds
Started Jan 03 12:25:55 PM PST 24
Finished Jan 03 12:25:57 PM PST 24
Peak memory 209156 kb
Host smart-d83f9758-db9e-43ac-a699-a0b6e7c36cc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938114980 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2938114980
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2722491855
Short name T156
Test name
Test status
Simulation time 21608138 ps
CPU time 0.63 seconds
Started Jan 03 12:27:23 PM PST 24
Finished Jan 03 12:27:28 PM PST 24
Peak memory 201236 kb
Host smart-5739fe35-09a2-460e-9a62-25aaeaa3b1f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722491855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2722491855
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920586082
Short name T190
Test name
Test status
Simulation time 405170171 ps
CPU time 5.26 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:30:50 PM PST 24
Peak memory 209876 kb
Host smart-bc5d2cc4-2d8e-436c-8bde-efef68ffceaa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920586082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1920586082
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3129303338
Short name T194
Test name
Test status
Simulation time 21999632 ps
CPU time 0.72 seconds
Started Jan 03 12:30:06 PM PST 24
Finished Jan 03 12:30:53 PM PST 24
Peak memory 201356 kb
Host smart-fc86465c-8db0-42c6-af01-21474641d2dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129303338 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3129303338
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.690198428
Short name T216
Test name
Test status
Simulation time 49536278 ps
CPU time 1.73 seconds
Started Jan 03 12:22:45 PM PST 24
Finished Jan 03 12:22:48 PM PST 24
Peak memory 201928 kb
Host smart-30f78b99-1473-47e5-9a60-9f0f98ecb730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690198428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_tl_errors.690198428
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1787190567
Short name T170
Test name
Test status
Simulation time 36460553 ps
CPU time 1.23 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 200672 kb
Host smart-8d3d0f4f-699b-409e-9fe2-5c79bc3098ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787190567 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1787190567
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1566149104
Short name T140
Test name
Test status
Simulation time 38320991 ps
CPU time 0.62 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:27:36 PM PST 24
Peak memory 201232 kb
Host smart-043393d1-4c0b-4dbf-83d9-d28f809215e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566149104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1566149104
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2476707462
Short name T171
Test name
Test status
Simulation time 793659578 ps
CPU time 5 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:31:21 PM PST 24
Peak memory 201720 kb
Host smart-90cd5f01-e3ae-4291-9537-7f50cbe1d013
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476707462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2476707462
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1296085788
Short name T179
Test name
Test status
Simulation time 14586586 ps
CPU time 0.72 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:19 PM PST 24
Peak memory 200616 kb
Host smart-5f87e79f-f270-40cc-a2ff-db21cba7cf7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296085788 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1296085788
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2603324304
Short name T144
Test name
Test status
Simulation time 37874654 ps
CPU time 3.6 seconds
Started Jan 03 12:27:25 PM PST 24
Finished Jan 03 12:27:34 PM PST 24
Peak memory 201632 kb
Host smart-1d602f5e-93ae-4e39-a8cd-f9844019f4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603324304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2603324304
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3561141649
Short name T206
Test name
Test status
Simulation time 197326588 ps
CPU time 1.35 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:27:30 PM PST 24
Peak memory 201052 kb
Host smart-5a31599a-7436-44fa-9ee0-856982d271e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561141649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3561141649
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3659863161
Short name T134
Test name
Test status
Simulation time 68751904 ps
CPU time 2.61 seconds
Started Jan 03 12:22:41 PM PST 24
Finished Jan 03 12:22:45 PM PST 24
Peak memory 210272 kb
Host smart-c3f1bfc6-ce63-45b6-a2a9-640683206011
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659863161 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3659863161
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4105466026
Short name T184
Test name
Test status
Simulation time 98759419 ps
CPU time 0.6 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:27:30 PM PST 24
Peak memory 201196 kb
Host smart-d05a4d1d-11d3-48ac-8fd3-a08497e64e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105466026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.4105466026
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2947925447
Short name T203
Test name
Test status
Simulation time 212787893 ps
CPU time 2.63 seconds
Started Jan 03 12:30:17 PM PST 24
Finished Jan 03 12:31:11 PM PST 24
Peak memory 201008 kb
Host smart-fa2b312a-aefe-430c-99ea-318564dd231b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947925447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2947925447
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3680631001
Short name T177
Test name
Test status
Simulation time 63221677 ps
CPU time 0.72 seconds
Started Jan 03 12:25:49 PM PST 24
Finished Jan 03 12:25:51 PM PST 24
Peak memory 201640 kb
Host smart-230f38a3-e668-4087-aabf-2eeb1f9e4508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680631001 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3680631001
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1149756450
Short name T172
Test name
Test status
Simulation time 516189109 ps
CPU time 4.02 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:27:40 PM PST 24
Peak memory 201576 kb
Host smart-617a7b73-e05e-4ed7-a19c-852d7ccdc3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149756450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.1149756450
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1019853924
Short name T150
Test name
Test status
Simulation time 238613140 ps
CPU time 1.22 seconds
Started Jan 03 12:27:30 PM PST 24
Finished Jan 03 12:27:37 PM PST 24
Peak memory 201464 kb
Host smart-00a98100-dd98-482c-a7f3-47fe244bc364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019853924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1019853924
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3919535089
Short name T95
Test name
Test status
Simulation time 69559566 ps
CPU time 1.2 seconds
Started Jan 03 12:41:30 PM PST 24
Finished Jan 03 12:42:59 PM PST 24
Peak memory 202148 kb
Host smart-cfef5988-06aa-4e0a-9127-763c2a1d10eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919535089 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3919535089
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3531652648
Short name T215
Test name
Test status
Simulation time 20542272 ps
CPU time 0.59 seconds
Started Jan 03 12:34:12 PM PST 24
Finished Jan 03 12:35:29 PM PST 24
Peak memory 201296 kb
Host smart-a26387ee-2d11-4b9e-bbc9-30981ce07331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531652648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3531652648
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.168685339
Short name T90
Test name
Test status
Simulation time 755548412 ps
CPU time 9.76 seconds
Started Jan 03 12:30:12 PM PST 24
Finished Jan 03 12:31:10 PM PST 24
Peak memory 201640 kb
Host smart-1cdb26aa-1af5-4e38-a212-c41aa4c0416e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168685339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.168685339
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3944985733
Short name T160
Test name
Test status
Simulation time 47799723 ps
CPU time 0.65 seconds
Started Jan 03 12:30:38 PM PST 24
Finished Jan 03 12:31:41 PM PST 24
Peak memory 201248 kb
Host smart-317f8e1d-a122-4f3c-9643-b74159091ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944985733 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3944985733
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3694459505
Short name T183
Test name
Test status
Simulation time 104593004 ps
CPU time 2.66 seconds
Started Jan 03 12:23:42 PM PST 24
Finished Jan 03 12:23:46 PM PST 24
Peak memory 201728 kb
Host smart-f82ce359-c55a-4867-bec4-48439fd32e27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694459505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3694459505
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.539431386
Short name T103
Test name
Test status
Simulation time 429772774 ps
CPU time 2.72 seconds
Started Jan 03 12:24:45 PM PST 24
Finished Jan 03 12:24:50 PM PST 24
Peak memory 201896 kb
Host smart-01e4629f-c2f0-45af-a243-bc1c573a922d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539431386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.sram_ctrl_tl_intg_err.539431386
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1893117103
Short name T148
Test name
Test status
Simulation time 31402150 ps
CPU time 0.59 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:30:00 PM PST 24
Peak memory 201184 kb
Host smart-d4c59fff-ee35-49d1-891a-f6f2fb328347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893117103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.1893117103
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2675408562
Short name T189
Test name
Test status
Simulation time 208582091 ps
CPU time 3.15 seconds
Started Jan 03 12:25:55 PM PST 24
Finished Jan 03 12:25:58 PM PST 24
Peak memory 201104 kb
Host smart-0514c71e-3335-4c82-9e55-5921db0d0857
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675408562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2675408562
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4022102468
Short name T154
Test name
Test status
Simulation time 44432658 ps
CPU time 0.65 seconds
Started Jan 03 12:30:47 PM PST 24
Finished Jan 03 12:31:54 PM PST 24
Peak memory 201372 kb
Host smart-e745ba1c-9097-4979-a421-29960c7f610a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022102468 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4022102468
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.492331973
Short name T45
Test name
Test status
Simulation time 533843460 ps
CPU time 4.43 seconds
Started Jan 03 12:30:44 PM PST 24
Finished Jan 03 12:31:54 PM PST 24
Peak memory 201672 kb
Host smart-d685ef7a-59a7-430b-96e6-b31fab12f560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492331973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.492331973
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1275262245
Short name T204
Test name
Test status
Simulation time 112364651 ps
CPU time 1.16 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 201032 kb
Host smart-39a26f6d-16d0-48ea-8489-86a0b5d94286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275262245 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1275262245
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1569873766
Short name T70
Test name
Test status
Simulation time 14052497 ps
CPU time 0.69 seconds
Started Jan 03 12:25:07 PM PST 24
Finished Jan 03 12:25:11 PM PST 24
Peak memory 201296 kb
Host smart-9b8c6b8f-06bf-4748-885b-5cbf714729f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569873766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.1569873766
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2005465570
Short name T158
Test name
Test status
Simulation time 58558887 ps
CPU time 0.65 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:03 PM PST 24
Peak memory 201584 kb
Host smart-755ec9d3-7067-44bc-8e9b-3c7299178838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005465570 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2005465570
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3024387534
Short name T188
Test name
Test status
Simulation time 265692648 ps
CPU time 1.4 seconds
Started Jan 03 12:24:09 PM PST 24
Finished Jan 03 12:24:15 PM PST 24
Peak memory 201844 kb
Host smart-1d4c7a1c-b16d-45f7-9e02-8b98fb2ae552
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024387534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.3024387534
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.329050143
Short name T176
Test name
Test status
Simulation time 30352187 ps
CPU time 2.1 seconds
Started Jan 03 12:23:55 PM PST 24
Finished Jan 03 12:23:58 PM PST 24
Peak memory 210344 kb
Host smart-b6843fd0-d1b5-4e4f-aebd-d9aa28d0a132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329050143 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.329050143
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2108630838
Short name T59
Test name
Test status
Simulation time 28876847 ps
CPU time 0.6 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:06 PM PST 24
Peak memory 201280 kb
Host smart-fdf1f2e5-ad9a-43e7-9413-07568bfc296e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108630838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.2108630838
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.145352187
Short name T89
Test name
Test status
Simulation time 769475973 ps
CPU time 9.45 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:58 PM PST 24
Peak memory 201136 kb
Host smart-e04e3c0c-c7b2-4bd8-9c6e-856b443be814
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145352187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.145352187
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4037541750
Short name T141
Test name
Test status
Simulation time 278887930 ps
CPU time 0.79 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 201272 kb
Host smart-0de86674-e61e-431f-afe4-55035e1fefac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037541750 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.4037541750
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2785595152
Short name T56
Test name
Test status
Simulation time 570298463 ps
CPU time 2.68 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:08 PM PST 24
Peak memory 201584 kb
Host smart-afadf74e-eac8-4e3a-8526-c29759fe454a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785595152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2785595152
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2316166604
Short name T107
Test name
Test status
Simulation time 690802220 ps
CPU time 2.35 seconds
Started Jan 03 12:28:39 PM PST 24
Finished Jan 03 12:28:58 PM PST 24
Peak memory 201860 kb
Host smart-ccef7827-1a04-4764-9d41-32a759e9873d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316166604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2316166604
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4259003546
Short name T152
Test name
Test status
Simulation time 56718603 ps
CPU time 1.4 seconds
Started Jan 03 12:29:59 PM PST 24
Finished Jan 03 12:30:55 PM PST 24
Peak memory 201880 kb
Host smart-b329f326-03bb-4583-a4e7-bd8efd2c344e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259003546 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.4259003546
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.69606221
Short name T186
Test name
Test status
Simulation time 13220322 ps
CPU time 0.67 seconds
Started Jan 03 12:25:11 PM PST 24
Finished Jan 03 12:25:16 PM PST 24
Peak memory 201600 kb
Host smart-eabc6600-2772-4f40-b037-88bbdcf59084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69606221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.sram_ctrl_csr_rw.69606221
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3843702075
Short name T85
Test name
Test status
Simulation time 1321866033 ps
CPU time 10.63 seconds
Started Jan 03 12:24:51 PM PST 24
Finished Jan 03 12:25:03 PM PST 24
Peak memory 201952 kb
Host smart-9f9275c9-2cc6-495d-9c90-caa5fa02df21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843702075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3843702075
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.519739971
Short name T201
Test name
Test status
Simulation time 13865038 ps
CPU time 0.79 seconds
Started Jan 03 12:34:45 PM PST 24
Finished Jan 03 12:36:01 PM PST 24
Peak memory 200992 kb
Host smart-beebea75-a961-488c-b88f-0f112f41b9ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519739971 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.519739971
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.831299584
Short name T207
Test name
Test status
Simulation time 138875215 ps
CPU time 2.76 seconds
Started Jan 03 12:29:22 PM PST 24
Finished Jan 03 12:29:55 PM PST 24
Peak memory 201712 kb
Host smart-5d7b1099-17ea-4174-a83e-fb5471ed41ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831299584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.831299584
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1865040085
Short name T44
Test name
Test status
Simulation time 847191332 ps
CPU time 1.31 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 201592 kb
Host smart-fe481ce8-c264-465d-bda1-2e3b09a7ac64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865040085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.1865040085
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.481195878
Short name T82
Test name
Test status
Simulation time 17778823 ps
CPU time 0.71 seconds
Started Jan 03 12:28:15 PM PST 24
Finished Jan 03 12:28:22 PM PST 24
Peak memory 200636 kb
Host smart-4ea10760-ab53-4a4d-8c58-197e6c7302c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481195878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.481195878
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.223126719
Short name T155
Test name
Test status
Simulation time 521750141 ps
CPU time 1.84 seconds
Started Jan 03 12:30:24 PM PST 24
Finished Jan 03 12:31:21 PM PST 24
Peak memory 201548 kb
Host smart-1f58717e-9378-40d3-9705-810ddcfecd9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223126719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_bit_bash.223126719
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1867249165
Short name T200
Test name
Test status
Simulation time 12833523 ps
CPU time 0.67 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 201344 kb
Host smart-16136afa-41ce-48a1-942d-ae7c9891274c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867249165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.1867249165
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1080324485
Short name T159
Test name
Test status
Simulation time 51602060 ps
CPU time 2.29 seconds
Started Jan 03 12:33:44 PM PST 24
Finished Jan 03 12:35:04 PM PST 24
Peak memory 201640 kb
Host smart-366ccecd-8393-4105-b6ae-e790350f9464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080324485 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1080324485
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2433694187
Short name T211
Test name
Test status
Simulation time 26156169 ps
CPU time 0.7 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 200292 kb
Host smart-27ca3648-20cd-4a3a-af6b-2fe1b2d64088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433694187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.2433694187
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3165833082
Short name T77
Test name
Test status
Simulation time 212020717 ps
CPU time 3.01 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:22 PM PST 24
Peak memory 201748 kb
Host smart-7b2eceb4-6498-4cbb-9b41-d2f948603a6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165833082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3165833082
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1614302903
Short name T157
Test name
Test status
Simulation time 273062833 ps
CPU time 2.29 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 12:30:12 PM PST 24
Peak memory 201648 kb
Host smart-0e64db72-d5c1-49eb-926f-1ab4f9d86b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614302903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1614302903
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.55977882
Short name T106
Test name
Test status
Simulation time 270335501 ps
CPU time 1.2 seconds
Started Jan 03 12:33:37 PM PST 24
Finished Jan 03 12:34:48 PM PST 24
Peak memory 201612 kb
Host smart-c3ad7a0f-af92-4774-8fad-2ac21ea82a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55977882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.sram_ctrl_tl_intg_err.55977882
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.170173412
Short name T199
Test name
Test status
Simulation time 43236474 ps
CPU time 0.63 seconds
Started Jan 03 12:42:12 PM PST 24
Finished Jan 03 12:43:34 PM PST 24
Peak memory 201700 kb
Host smart-109e5ba8-7afd-4339-baea-368f2a2a2211
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170173412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_aliasing.170173412
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.930008620
Short name T139
Test name
Test status
Simulation time 574510262 ps
CPU time 1.99 seconds
Started Jan 03 12:32:32 PM PST 24
Finished Jan 03 12:33:59 PM PST 24
Peak memory 201620 kb
Host smart-28663211-31e1-4686-8d5e-6ab49f7f0442
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930008620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_bit_bash.930008620
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.596845884
Short name T86
Test name
Test status
Simulation time 107260088 ps
CPU time 0.64 seconds
Started Jan 03 12:42:06 PM PST 24
Finished Jan 03 12:43:41 PM PST 24
Peak memory 201336 kb
Host smart-0908c5b2-9212-4e31-8ef7-5c5a63696a55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596845884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_hw_reset.596845884
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2186139360
Short name T191
Test name
Test status
Simulation time 52639475 ps
CPU time 2.13 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:20 PM PST 24
Peak memory 210228 kb
Host smart-b38c0972-136a-49aa-aaf9-a5fb6c0bca61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186139360 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2186139360
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.298805165
Short name T137
Test name
Test status
Simulation time 35036965 ps
CPU time 0.64 seconds
Started Jan 03 12:35:15 PM PST 24
Finished Jan 03 12:36:58 PM PST 24
Peak memory 201220 kb
Host smart-0aae90d3-a149-4401-81cf-5786c57acaf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298805165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_csr_rw.298805165
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3743472430
Short name T69
Test name
Test status
Simulation time 212045156 ps
CPU time 2.87 seconds
Started Jan 03 12:30:38 PM PST 24
Finished Jan 03 12:31:43 PM PST 24
Peak memory 201676 kb
Host smart-8c5d8a4a-1583-4123-bbe4-980c70a14458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743472430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3743472430
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4244428152
Short name T136
Test name
Test status
Simulation time 27276296 ps
CPU time 0.68 seconds
Started Jan 03 12:34:47 PM PST 24
Finished Jan 03 12:36:15 PM PST 24
Peak memory 201284 kb
Host smart-759e2abf-0a05-4530-a0da-ce4b83da7503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244428152 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.4244428152
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1326890657
Short name T182
Test name
Test status
Simulation time 117074476 ps
CPU time 3.51 seconds
Started Jan 03 12:44:13 PM PST 24
Finished Jan 03 12:45:37 PM PST 24
Peak memory 202084 kb
Host smart-5fc03d69-9b94-4dd7-8429-b529eec6c3b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326890657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1326890657
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1863992650
Short name T214
Test name
Test status
Simulation time 182744762 ps
CPU time 1.32 seconds
Started Jan 03 12:24:45 PM PST 24
Finished Jan 03 12:24:48 PM PST 24
Peak memory 201876 kb
Host smart-b1f23444-9d52-4a61-a9b1-2a8a85267ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863992650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1863992650
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2727530434
Short name T145
Test name
Test status
Simulation time 19369018 ps
CPU time 0.7 seconds
Started Jan 03 12:25:21 PM PST 24
Finished Jan 03 12:25:23 PM PST 24
Peak memory 201696 kb
Host smart-48bcd249-a228-40d8-ac3c-4a9bd37926b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727530434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.2727530434
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3995693143
Short name T94
Test name
Test status
Simulation time 37198387 ps
CPU time 1.55 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:30:33 PM PST 24
Peak memory 199936 kb
Host smart-9133bf28-65e5-4886-a649-a9b9cf0ef246
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995693143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3995693143
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.814616653
Short name T78
Test name
Test status
Simulation time 18461927 ps
CPU time 0.67 seconds
Started Jan 03 12:24:45 PM PST 24
Finished Jan 03 12:24:48 PM PST 24
Peak memory 201568 kb
Host smart-d268fca4-1c27-4842-a053-e89222b4a986
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814616653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_hw_reset.814616653
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.391556233
Short name T133
Test name
Test status
Simulation time 37960208 ps
CPU time 1.22 seconds
Started Jan 03 12:32:05 PM PST 24
Finished Jan 03 12:33:34 PM PST 24
Peak memory 201152 kb
Host smart-0aa34d75-b223-4f6d-8e2e-54d858694f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391556233 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.391556233
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1459471630
Short name T58
Test name
Test status
Simulation time 35876336 ps
CPU time 0.67 seconds
Started Jan 03 12:30:10 PM PST 24
Finished Jan 03 12:30:57 PM PST 24
Peak memory 200140 kb
Host smart-0f90f417-e12b-4998-8156-268d1ccb61a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459471630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1459471630
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1361027680
Short name T192
Test name
Test status
Simulation time 1059590985 ps
CPU time 2.8 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:21 PM PST 24
Peak memory 201648 kb
Host smart-ec2062b7-5cf9-4713-ae8e-67292274284f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361027680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1361027680
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1577173276
Short name T63
Test name
Test status
Simulation time 49424772 ps
CPU time 0.79 seconds
Started Jan 03 12:27:22 PM PST 24
Finished Jan 03 12:27:28 PM PST 24
Peak memory 199568 kb
Host smart-626c21ed-b795-40bb-a7e9-0a7653e186c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577173276 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1577173276
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2229218326
Short name T165
Test name
Test status
Simulation time 106928088 ps
CPU time 2.09 seconds
Started Jan 03 12:32:31 PM PST 24
Finished Jan 03 12:33:58 PM PST 24
Peak memory 201736 kb
Host smart-a6e5f04c-05c6-4906-b884-7cd5533ee9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229218326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2229218326
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3172853852
Short name T217
Test name
Test status
Simulation time 161702604 ps
CPU time 1.49 seconds
Started Jan 03 12:30:01 PM PST 24
Finished Jan 03 12:30:47 PM PST 24
Peak memory 201568 kb
Host smart-6e13e103-81a0-4d1d-a2f3-c850ca78d27a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172853852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3172853852
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3493559360
Short name T153
Test name
Test status
Simulation time 57190997 ps
CPU time 1.6 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:27:31 PM PST 24
Peak memory 209780 kb
Host smart-9e562c67-e5a9-4098-9958-5715c4f95363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493559360 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3493559360
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1916259687
Short name T167
Test name
Test status
Simulation time 42831216 ps
CPU time 0.67 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 200308 kb
Host smart-17bcc33f-1ff9-467d-b85c-bb165dc2a556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916259687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1916259687
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3022756512
Short name T68
Test name
Test status
Simulation time 809032990 ps
CPU time 10.22 seconds
Started Jan 03 12:30:18 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 201612 kb
Host smart-e3c39ec9-ca10-48a6-8315-784534d40150
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022756512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3022756512
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.825318500
Short name T193
Test name
Test status
Simulation time 18816389 ps
CPU time 0.72 seconds
Started Jan 03 12:27:30 PM PST 24
Finished Jan 03 12:27:36 PM PST 24
Peak memory 201180 kb
Host smart-52c1e207-811a-4125-8585-7d84321aa6e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825318500 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.825318500
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3931937564
Short name T135
Test name
Test status
Simulation time 186554119 ps
CPU time 3.82 seconds
Started Jan 03 12:23:02 PM PST 24
Finished Jan 03 12:23:06 PM PST 24
Peak memory 202168 kb
Host smart-43ed763f-c919-490b-a051-bdebe5f39613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931937564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3931937564
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4004724965
Short name T197
Test name
Test status
Simulation time 359037145 ps
CPU time 1.49 seconds
Started Jan 03 12:24:14 PM PST 24
Finished Jan 03 12:24:18 PM PST 24
Peak memory 201884 kb
Host smart-5eb69295-366f-4296-b116-9c657a584ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004724965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.4004724965
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2163562855
Short name T209
Test name
Test status
Simulation time 25974320 ps
CPU time 0.99 seconds
Started Jan 03 12:23:47 PM PST 24
Finished Jan 03 12:23:50 PM PST 24
Peak memory 201784 kb
Host smart-eac9264a-2b8b-4e70-a8c0-786430252572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163562855 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2163562855
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.247609395
Short name T146
Test name
Test status
Simulation time 18640100 ps
CPU time 0.63 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:27:36 PM PST 24
Peak memory 201180 kb
Host smart-3042bbbb-34fe-4737-9527-c0832a5034de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247609395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.247609395
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2434325946
Short name T162
Test name
Test status
Simulation time 384235426 ps
CPU time 5.1 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:28:00 PM PST 24
Peak memory 202024 kb
Host smart-9eee2e40-12bd-4ab3-8ade-126474ef4096
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434325946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2434325946
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3248991177
Short name T72
Test name
Test status
Simulation time 99007268 ps
CPU time 0.75 seconds
Started Jan 03 12:35:06 PM PST 24
Finished Jan 03 12:36:42 PM PST 24
Peak memory 201824 kb
Host smart-a83de980-a02e-42c8-b158-e2f5d3a42b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248991177 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3248991177
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2614583454
Short name T50
Test name
Test status
Simulation time 115945571 ps
CPU time 2.93 seconds
Started Jan 03 12:25:49 PM PST 24
Finished Jan 03 12:25:53 PM PST 24
Peak memory 201908 kb
Host smart-76c709bc-1fc0-4d0e-8a41-29b5dccdf362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614583454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2614583454
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2930174204
Short name T104
Test name
Test status
Simulation time 1012060507 ps
CPU time 2.75 seconds
Started Jan 03 12:23:35 PM PST 24
Finished Jan 03 12:23:38 PM PST 24
Peak memory 201852 kb
Host smart-4a148c18-3096-4ff0-a93e-42ed9708c07c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930174204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2930174204
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4287674868
Short name T46
Test name
Test status
Simulation time 43709672 ps
CPU time 3.28 seconds
Started Jan 03 12:22:44 PM PST 24
Finished Jan 03 12:22:49 PM PST 24
Peak memory 210132 kb
Host smart-eec63d8a-b7b1-412d-93a7-b761bcccf7eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287674868 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.4287674868
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.877293639
Short name T151
Test name
Test status
Simulation time 20782105 ps
CPU time 0.64 seconds
Started Jan 03 12:30:13 PM PST 24
Finished Jan 03 12:31:01 PM PST 24
Peak memory 200080 kb
Host smart-f933ca3c-81b8-4148-b63d-cd6bd0a88225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877293639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_csr_rw.877293639
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4207087774
Short name T212
Test name
Test status
Simulation time 1566301988 ps
CPU time 5.37 seconds
Started Jan 03 12:26:07 PM PST 24
Finished Jan 03 12:26:13 PM PST 24
Peak memory 201916 kb
Host smart-bf3bb5b3-caa8-4a22-b021-2080db3fedbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207087774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.4207087774
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2449111307
Short name T142
Test name
Test status
Simulation time 15804131 ps
CPU time 0.65 seconds
Started Jan 03 12:30:36 PM PST 24
Finished Jan 03 12:31:38 PM PST 24
Peak memory 201244 kb
Host smart-b8abf114-849d-4a7b-9d7d-059459cdd298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449111307 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2449111307
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1755059240
Short name T49
Test name
Test status
Simulation time 164984311 ps
CPU time 3.65 seconds
Started Jan 03 12:38:33 PM PST 24
Finished Jan 03 12:39:46 PM PST 24
Peak memory 201956 kb
Host smart-46883ade-f638-49c8-a496-89d758ee689c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755059240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1755059240
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3087420518
Short name T99
Test name
Test status
Simulation time 175743052 ps
CPU time 2.03 seconds
Started Jan 03 12:42:13 PM PST 24
Finished Jan 03 12:43:49 PM PST 24
Peak memory 202008 kb
Host smart-a7ca0b8b-fcfa-49c7-8c25-eddde0fcdc2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087420518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3087420518
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1373131371
Short name T57
Test name
Test status
Simulation time 52134609 ps
CPU time 1.85 seconds
Started Jan 03 12:29:19 PM PST 24
Finished Jan 03 12:29:49 PM PST 24
Peak memory 201104 kb
Host smart-8d617d93-65fe-460f-bb82-7ad9e4d31c66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373131371 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1373131371
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3504181915
Short name T175
Test name
Test status
Simulation time 288050876 ps
CPU time 2.84 seconds
Started Jan 03 12:44:37 PM PST 24
Finished Jan 03 12:46:01 PM PST 24
Peak memory 201980 kb
Host smart-85c0f773-0953-4204-9669-fdd6f5c68da5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504181915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3504181915
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2047000813
Short name T169
Test name
Test status
Simulation time 17070765 ps
CPU time 0.75 seconds
Started Jan 03 12:44:15 PM PST 24
Finished Jan 03 12:45:38 PM PST 24
Peak memory 201464 kb
Host smart-15b5e1bd-1cc3-4c7b-802f-c2a3ec356f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047000813 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2047000813
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2808820122
Short name T143
Test name
Test status
Simulation time 41440695 ps
CPU time 2.89 seconds
Started Jan 03 12:45:59 PM PST 24
Finished Jan 03 12:47:26 PM PST 24
Peak memory 202188 kb
Host smart-5164f705-170b-49cb-a708-5a928b357de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808820122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.2808820122
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.415862822
Short name T178
Test name
Test status
Simulation time 353313354 ps
CPU time 1.43 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:30:11 PM PST 24
Peak memory 201600 kb
Host smart-075aa693-c5f0-4319-bca5-5a53fc1d3158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415862822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.sram_ctrl_tl_intg_err.415862822
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2761696945
Short name T174
Test name
Test status
Simulation time 36516864 ps
CPU time 1.34 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:56 PM PST 24
Peak memory 201164 kb
Host smart-ee42a1d2-9cbc-4b65-9f55-787e697f8953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761696945 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2761696945
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2409288979
Short name T161
Test name
Test status
Simulation time 23860646 ps
CPU time 0.65 seconds
Started Jan 03 12:24:14 PM PST 24
Finished Jan 03 12:24:17 PM PST 24
Peak memory 201644 kb
Host smart-620fd5b4-dceb-4fba-946d-eaa6f9b7ff9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409288979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.2409288979
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3395350224
Short name T60
Test name
Test status
Simulation time 5323205744 ps
CPU time 9.76 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:13 PM PST 24
Peak memory 202072 kb
Host smart-be60b8c6-a283-4b4b-b9e5-d3e250c042f7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395350224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3395350224
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.101185114
Short name T168
Test name
Test status
Simulation time 13904711 ps
CPU time 0.66 seconds
Started Jan 03 12:44:15 PM PST 24
Finished Jan 03 12:45:55 PM PST 24
Peak memory 201584 kb
Host smart-956734b5-09eb-4bed-85d6-708ad09bc7b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101185114 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.101185114
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2548046687
Short name T202
Test name
Test status
Simulation time 129173671 ps
CPU time 3.02 seconds
Started Jan 03 12:23:42 PM PST 24
Finished Jan 03 12:23:46 PM PST 24
Peak memory 201588 kb
Host smart-eb6f4136-3978-4dca-bcf7-cd725de3e986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548046687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2548046687
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2770576451
Short name T105
Test name
Test status
Simulation time 244134292 ps
CPU time 2.31 seconds
Started Jan 03 12:28:39 PM PST 24
Finished Jan 03 12:28:58 PM PST 24
Peak memory 201888 kb
Host smart-7b1d6d0c-9aa6-4785-a4af-659a0bf183e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770576451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.2770576451
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1048563297
Short name T930
Test name
Test status
Simulation time 6102351298 ps
CPU time 577.36 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 373780 kb
Host smart-0139d155-cc6c-4305-a509-09a1dbe16fc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048563297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1048563297
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.4293262957
Short name T391
Test name
Test status
Simulation time 15928457 ps
CPU time 0.62 seconds
Started Jan 03 12:51:18 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 202712 kb
Host smart-26d89fe7-643a-4e95-a99b-4432db621bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293262957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.4293262957
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.3448969379
Short name T255
Test name
Test status
Simulation time 2122642490 ps
CPU time 38.73 seconds
Started Jan 03 12:51:08 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 202824 kb
Host smart-651d7621-f2a2-4dec-a6c1-f0169bf5256a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448969379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
3448969379
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.1435293617
Short name T259
Test name
Test status
Simulation time 7933125835 ps
CPU time 929.61 seconds
Started Jan 03 12:51:09 PM PST 24
Finished Jan 03 01:06:57 PM PST 24
Peak memory 375808 kb
Host smart-4187ff36-68ca-465e-a18e-4cc3d449e578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435293617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.1435293617
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.4229973046
Short name T702
Test name
Test status
Simulation time 2570303070 ps
CPU time 7.47 seconds
Started Jan 03 12:51:12 PM PST 24
Finished Jan 03 12:51:37 PM PST 24
Peak memory 203024 kb
Host smart-ad7a1aae-3842-47f4-a41a-487af89cb329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229973046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.4229973046
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.660099182
Short name T844
Test name
Test status
Simulation time 572219918 ps
CPU time 12.28 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 251984 kb
Host smart-fffc5151-9a1a-47c0-b4aa-58f6bb4ffb4a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660099182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.660099182
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2293920660
Short name T634
Test name
Test status
Simulation time 342757033 ps
CPU time 2.96 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 219240 kb
Host smart-0cfb4efb-7da1-4d52-8f69-4d683b747585
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293920660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.2293920660
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2650185854
Short name T803
Test name
Test status
Simulation time 2428355176 ps
CPU time 9.51 seconds
Started Jan 03 12:51:06 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 202992 kb
Host smart-66e7e01b-10cc-49ab-8b69-7cb6f17f3235
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650185854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2650185854
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.4168844750
Short name T9
Test name
Test status
Simulation time 1637030754 ps
CPU time 333.88 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 359832 kb
Host smart-592b184d-b8d5-445e-b370-a08b2594dd98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168844750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.4168844750
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.2677777520
Short name T790
Test name
Test status
Simulation time 7319510656 ps
CPU time 14.17 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:45 PM PST 24
Peak memory 202832 kb
Host smart-57871c95-9492-445e-8681-4d3ca999ba3c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677777520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.2677777520
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1238158325
Short name T752
Test name
Test status
Simulation time 43896233969 ps
CPU time 264.45 seconds
Started Jan 03 12:51:22 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 202908 kb
Host smart-fdeee877-1b53-4679-ad2c-b6f4120f1570
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238158325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1238158325
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1389646241
Short name T275
Test name
Test status
Simulation time 48219350 ps
CPU time 1.06 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 203068 kb
Host smart-6c8786da-6a83-4f91-ba64-6e07587f8933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389646241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1389646241
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.4033011153
Short name T981
Test name
Test status
Simulation time 15858715846 ps
CPU time 636.98 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 374620 kb
Host smart-69670426-42de-4e65-a888-86f69dac5e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033011153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4033011153
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.3593149749
Short name T932
Test name
Test status
Simulation time 2736570576 ps
CPU time 88.64 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:53:00 PM PST 24
Peak memory 358056 kb
Host smart-68dea0e1-f5c6-4146-97cf-a4198f3de7ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593149749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3593149749
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.1006887066
Short name T645
Test name
Test status
Simulation time 173523464520 ps
CPU time 3490.71 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 01:49:33 PM PST 24
Peak memory 375752 kb
Host smart-73c7391d-afa9-4686-a3e1-de6113e6570b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006887066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.1006887066
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1040890572
Short name T456
Test name
Test status
Simulation time 3826130579 ps
CPU time 3190.09 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 01:44:38 PM PST 24
Peak memory 433840 kb
Host smart-c45b7ffd-fc47-4fef-8bc7-487fb42d7011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1040890572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1040890572
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1388816872
Short name T406
Test name
Test status
Simulation time 6899978857 ps
CPU time 153.56 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 202920 kb
Host smart-1a3a8e28-c9d5-485c-9e8a-1b4077c6119b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388816872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.1388816872
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.473839597
Short name T225
Test name
Test status
Simulation time 57370406 ps
CPU time 5.53 seconds
Started Jan 03 12:51:08 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 225840 kb
Host smart-904117c8-a149-4625-b4ef-cd2da2df0ede
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473839597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.473839597
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2549789558
Short name T940
Test name
Test status
Simulation time 16708347273 ps
CPU time 545.95 seconds
Started Jan 03 12:51:15 PM PST 24
Finished Jan 03 01:00:38 PM PST 24
Peak memory 346128 kb
Host smart-bc88d742-956b-462b-8cd9-8933eb84afbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549789558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2549789558
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1405813657
Short name T319
Test name
Test status
Simulation time 3714019940 ps
CPU time 63.16 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:52:34 PM PST 24
Peak memory 202936 kb
Host smart-2510dc00-ca2c-4ff7-93c9-838c4f31928a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405813657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1405813657
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.3362856464
Short name T290
Test name
Test status
Simulation time 33683068159 ps
CPU time 276.9 seconds
Started Jan 03 12:50:55 PM PST 24
Finished Jan 03 12:55:54 PM PST 24
Peak memory 373608 kb
Host smart-282ebb89-a927-4953-b61c-be60b6f286d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362856464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.3362856464
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.4161834270
Short name T337
Test name
Test status
Simulation time 739682390 ps
CPU time 21.65 seconds
Started Jan 03 12:51:16 PM PST 24
Finished Jan 03 12:51:55 PM PST 24
Peak memory 211060 kb
Host smart-58595250-7fb7-467e-83ae-dd2087b1de62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161834270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.4161834270
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3425288435
Short name T525
Test name
Test status
Simulation time 138662971 ps
CPU time 75.34 seconds
Started Jan 03 12:51:14 PM PST 24
Finished Jan 03 12:52:47 PM PST 24
Peak memory 334556 kb
Host smart-c120524b-d44e-4323-b959-16e3d8721de8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425288435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3425288435
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.15618672
Short name T693
Test name
Test status
Simulation time 364573450 ps
CPU time 4.5 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:15 PM PST 24
Peak memory 210976 kb
Host smart-c0188b83-d1f1-4756-be4a-9e35310a3e16
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_mem_partial_access.15618672
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.186007169
Short name T827
Test name
Test status
Simulation time 473362209 ps
CPU time 5.25 seconds
Started Jan 03 12:51:23 PM PST 24
Finished Jan 03 12:51:43 PM PST 24
Peak memory 202928 kb
Host smart-c8fa409b-ada8-4ce6-a956-c4e921e151fd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186007169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
mem_walk.186007169
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.423202416
Short name T656
Test name
Test status
Simulation time 13704434895 ps
CPU time 1171.59 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 01:10:50 PM PST 24
Peak memory 376772 kb
Host smart-8e58997e-c90a-43fb-9ac9-6bc93959343a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423202416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl
e_keys.423202416
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2918583019
Short name T617
Test name
Test status
Simulation time 790929097 ps
CPU time 110.82 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:53:12 PM PST 24
Peak memory 374592 kb
Host smart-114ca1a2-6cb7-449a-bcf2-9133cd119167
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918583019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2918583019
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.757039389
Short name T779
Test name
Test status
Simulation time 107711403028 ps
CPU time 351.32 seconds
Started Jan 03 12:51:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 202940 kb
Host smart-70313e8f-41c0-47c0-9092-33dcebb99f41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757039389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.757039389
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.4162840941
Short name T926
Test name
Test status
Simulation time 124742056 ps
CPU time 0.82 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 202896 kb
Host smart-e6bb5494-6c8d-4c16-9fd9-34b903517664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162840941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.4162840941
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3511301313
Short name T477
Test name
Test status
Simulation time 49439870826 ps
CPU time 1504.17 seconds
Started Jan 03 12:51:09 PM PST 24
Finished Jan 03 01:16:31 PM PST 24
Peak memory 374764 kb
Host smart-b6589aec-9adf-4536-ad8f-7c286560bf07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511301313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3511301313
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3435154900
Short name T33
Test name
Test status
Simulation time 399537821 ps
CPU time 1.84 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 221392 kb
Host smart-1928b8db-5dfe-4d46-bf34-6effdd6d70f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435154900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3435154900
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2352603381
Short name T317
Test name
Test status
Simulation time 95783165 ps
CPU time 28.29 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:51:51 PM PST 24
Peak memory 292704 kb
Host smart-6580ca4c-f493-4678-8388-4fb2e701f793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352603381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2352603381
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.494724935
Short name T939
Test name
Test status
Simulation time 278355564525 ps
CPU time 2266.74 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 373372 kb
Host smart-9dea756c-368d-4192-b6e9-857a8c48031f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494724935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_stress_all.494724935
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2283333722
Short name T670
Test name
Test status
Simulation time 245766689 ps
CPU time 1910.64 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 01:23:02 PM PST 24
Peak memory 415800 kb
Host smart-4def7569-4221-4959-9f3a-8b777a3c5b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2283333722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2283333722
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2224825935
Short name T979
Test name
Test status
Simulation time 24123271011 ps
CPU time 248.92 seconds
Started Jan 03 12:51:04 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 202940 kb
Host smart-bf5cc61b-29bc-4f96-95fb-e1d9d1bb6a3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224825935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2224825935
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2481217130
Short name T322
Test name
Test status
Simulation time 625701934 ps
CPU time 23.14 seconds
Started Jan 03 12:50:55 PM PST 24
Finished Jan 03 12:51:40 PM PST 24
Peak memory 284420 kb
Host smart-b6943e70-8bad-4fd4-b600-0aa2d519a729
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481217130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2481217130
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3078210847
Short name T873
Test name
Test status
Simulation time 14033197 ps
CPU time 0.62 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 202728 kb
Host smart-44f5ed93-fe8c-48ab-ae2d-e37922f5d9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078210847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3078210847
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.356561973
Short name T527
Test name
Test status
Simulation time 3419607574 ps
CPU time 47.87 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:55 PM PST 24
Peak memory 202952 kb
Host smart-0ef927e4-69e1-49ab-972e-a85cbfee3b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356561973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.
356561973
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.2507833979
Short name T980
Test name
Test status
Simulation time 2851172266 ps
CPU time 626.07 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 359264 kb
Host smart-2882948f-13ca-4bbc-a9ce-83c31e041126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507833979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.2507833979
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.987354051
Short name T682
Test name
Test status
Simulation time 847474186 ps
CPU time 2.95 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 202848 kb
Host smart-8650bb09-d9f1-4d86-99f5-f79a642c8752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987354051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc
alation.987354051
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.1376389751
Short name T989
Test name
Test status
Simulation time 497267022 ps
CPU time 21.17 seconds
Started Jan 03 12:52:00 PM PST 24
Finished Jan 03 12:52:25 PM PST 24
Peak memory 284660 kb
Host smart-9ed1a49c-2fed-4c21-9afc-e48d6159d500
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376389751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.1376389751
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.596354225
Short name T279
Test name
Test status
Simulation time 88527281 ps
CPU time 2.97 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:52:45 PM PST 24
Peak memory 211060 kb
Host smart-51cb7772-4604-4d12-b3bb-a4c3e28c4261
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596354225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.596354225
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3826321342
Short name T931
Test name
Test status
Simulation time 283729449 ps
CPU time 4.33 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 12:52:07 PM PST 24
Peak memory 202764 kb
Host smart-373b8a9d-3e98-4742-be3f-f1305bd4c20d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826321342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3826321342
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.233583276
Short name T269
Test name
Test status
Simulation time 1941346736 ps
CPU time 353.78 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:58:26 PM PST 24
Peak memory 359376 kb
Host smart-7cdd1c7e-5898-4cb8-b2a4-5d4dd808ec17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233583276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.233583276
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2702984877
Short name T447
Test name
Test status
Simulation time 3432024970 ps
CPU time 9.4 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:52:52 PM PST 24
Peak memory 237372 kb
Host smart-6ab78c0f-1450-4dd1-ad49-e10cfd3cb17c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702984877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2702984877
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3326644068
Short name T312
Test name
Test status
Simulation time 40129345188 ps
CPU time 256.05 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 202884 kb
Host smart-59b991ce-0204-4c27-bbd0-e0b4087cf073
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326644068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.3326644068
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1929743386
Short name T935
Test name
Test status
Simulation time 41551954 ps
CPU time 1.08 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:32 PM PST 24
Peak memory 203088 kb
Host smart-13aece80-3573-4266-819b-ae2384af1c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929743386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1929743386
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.3657346978
Short name T780
Test name
Test status
Simulation time 8022533746 ps
CPU time 142.1 seconds
Started Jan 03 12:51:54 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 360636 kb
Host smart-b563e2af-0ef7-40fa-b0c0-7ca3acb1af39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657346978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3657346978
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.191930690
Short name T388
Test name
Test status
Simulation time 447279846 ps
CPU time 2.88 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 12:54:06 PM PST 24
Peak memory 202752 kb
Host smart-b6f2e555-aeaa-4166-b0d2-1066f2f77429
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191930690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.191930690
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.453729626
Short name T808
Test name
Test status
Simulation time 42057125072 ps
CPU time 2699.67 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 01:37:20 PM PST 24
Peak memory 372704 kb
Host smart-92726402-01a1-4529-9075-c50ab327e1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453729626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_stress_all.453729626
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3599921417
Short name T671
Test name
Test status
Simulation time 1127612663 ps
CPU time 3112.69 seconds
Started Jan 03 12:51:53 PM PST 24
Finished Jan 03 01:43:52 PM PST 24
Peak memory 449592 kb
Host smart-df7a9a66-62ed-41ae-8e12-b3b34491f0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3599921417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3599921417
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2268199406
Short name T333
Test name
Test status
Simulation time 1978343629 ps
CPU time 161.89 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 202872 kb
Host smart-45b58ba7-dc0a-4c4a-9d45-6c75c147dd8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268199406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2268199406
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1985193415
Short name T519
Test name
Test status
Simulation time 140835322 ps
CPU time 69.1 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:53:10 PM PST 24
Peak memory 344520 kb
Host smart-c9d9b120-cc36-4684-bc28-a6c65d2e0bce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985193415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.1985193415
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3732260799
Short name T17
Test name
Test status
Simulation time 3143696133 ps
CPU time 710.27 seconds
Started Jan 03 12:52:18 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 374804 kb
Host smart-5054b75d-f890-4df0-8af5-69411dc380b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732260799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.3732260799
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.156467639
Short name T712
Test name
Test status
Simulation time 20800724 ps
CPU time 0.64 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:32 PM PST 24
Peak memory 202704 kb
Host smart-e1265d43-0e6e-4832-8ca4-26871613cfda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156467639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.156467639
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.775879939
Short name T775
Test name
Test status
Simulation time 3185732789 ps
CPU time 48.43 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 12:53:07 PM PST 24
Peak memory 202872 kb
Host smart-248937d6-e45a-4b6a-81b5-ba125c21edb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775879939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
775879939
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.2197152282
Short name T872
Test name
Test status
Simulation time 44725481615 ps
CPU time 560.97 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 363956 kb
Host smart-c17f9c67-0d9e-4769-b9a4-2ed1bc5b0330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197152282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.2197152282
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.879703162
Short name T831
Test name
Test status
Simulation time 1610750146 ps
CPU time 11.86 seconds
Started Jan 03 12:52:20 PM PST 24
Finished Jan 03 12:53:09 PM PST 24
Peak memory 202796 kb
Host smart-8596fa92-252f-4563-bb81-cabb9269d09c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879703162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc
alation.879703162
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.4014866287
Short name T311
Test name
Test status
Simulation time 98448947 ps
CPU time 37.41 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:53:21 PM PST 24
Peak memory 302384 kb
Host smart-3c58a3f7-3d93-4b2b-afda-65134fb5da08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014866287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.4014866287
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1209369786
Short name T308
Test name
Test status
Simulation time 162209982 ps
CPU time 5.04 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 211144 kb
Host smart-1d29f4d9-244c-4a9e-8b90-3c2a7aa52694
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209369786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1209369786
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.958471664
Short name T264
Test name
Test status
Simulation time 7226788630 ps
CPU time 9.63 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:31 PM PST 24
Peak memory 202964 kb
Host smart-090bbc63-1d4a-490b-8784-891d20685b20
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958471664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.958471664
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.745052560
Short name T917
Test name
Test status
Simulation time 12674763006 ps
CPU time 969.68 seconds
Started Jan 03 12:52:23 PM PST 24
Finished Jan 03 01:09:35 PM PST 24
Peak memory 374360 kb
Host smart-0d535261-6f38-43eb-a2ed-758ea45ee5be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745052560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.745052560
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3209310256
Short name T583
Test name
Test status
Simulation time 7657635490 ps
CPU time 14.76 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:24 PM PST 24
Peak memory 202892 kb
Host smart-d0afacbd-03a6-4992-8d18-dd170fb56454
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209310256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3209310256
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984965878
Short name T111
Test name
Test status
Simulation time 34448629493 ps
CPU time 369 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 12:58:30 PM PST 24
Peak memory 203008 kb
Host smart-ff9f5dfb-4bec-42cc-98e2-132db68e1100
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984965878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.984965878
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.506014243
Short name T426
Test name
Test status
Simulation time 271648920 ps
CPU time 0.89 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:52:44 PM PST 24
Peak memory 202908 kb
Host smart-d24298cc-7fde-449b-9d3d-c1c17f9ae5b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506014243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.506014243
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.442370164
Short name T316
Test name
Test status
Simulation time 876317633 ps
CPU time 100.49 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 313084 kb
Host smart-655fe7f7-c5f1-4eb2-b7b0-0b738d80ad7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442370164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.442370164
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1658519114
Short name T236
Test name
Test status
Simulation time 163065718 ps
CPU time 7.03 seconds
Started Jan 03 12:52:18 PM PST 24
Finished Jan 03 12:52:51 PM PST 24
Peak memory 231468 kb
Host smart-7634d6de-062c-4ffa-b7f8-a9ab704e43e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658519114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1658519114
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.3248402234
Short name T694
Test name
Test status
Simulation time 104099858657 ps
CPU time 1197.46 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 01:12:37 PM PST 24
Peak memory 370692 kb
Host smart-066d5bb1-2c26-487c-959c-0e3462857ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248402234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.3248402234
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2067481362
Short name T969
Test name
Test status
Simulation time 1055391649 ps
CPU time 228.59 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:56:30 PM PST 24
Peak memory 321416 kb
Host smart-604517b1-e5d9-4b3b-bc8d-a38bd5aad094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2067481362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2067481362
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1525322140
Short name T942
Test name
Test status
Simulation time 2232998874 ps
CPU time 213.09 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 202968 kb
Host smart-3a1e368b-1ee5-476f-b3a4-ee0b802f4145
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525322140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.1525322140
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3684938959
Short name T910
Test name
Test status
Simulation time 55324545 ps
CPU time 4.85 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:53:02 PM PST 24
Peak memory 225392 kb
Host smart-cd035614-d841-4512-862e-f53f0374d868
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684938959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3684938959
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2216341311
Short name T340
Test name
Test status
Simulation time 3502710137 ps
CPU time 723.78 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 373688 kb
Host smart-eb4f579e-2b94-4028-bd2a-86f14fb396c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216341311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.2216341311
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.1134446839
Short name T556
Test name
Test status
Simulation time 11953570 ps
CPU time 0.62 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:52:01 PM PST 24
Peak memory 202752 kb
Host smart-c8bf37dc-272b-443e-88a7-7f42c55a1fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134446839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.1134446839
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.20502580
Short name T131
Test name
Test status
Simulation time 12912823103 ps
CPU time 66.16 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 12:53:41 PM PST 24
Peak memory 202936 kb
Host smart-96af7084-3915-4b2b-9419-f6766b610987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20502580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.20502580
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.4178121583
Short name T739
Test name
Test status
Simulation time 437521830 ps
CPU time 58.5 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:53:09 PM PST 24
Peak memory 328768 kb
Host smart-ea9de42a-b2c8-4997-93b2-f6f44fdf18d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178121583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.4178121583
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.362952677
Short name T597
Test name
Test status
Simulation time 365844065 ps
CPU time 2.99 seconds
Started Jan 03 12:52:26 PM PST 24
Finished Jan 03 12:53:28 PM PST 24
Peak memory 211120 kb
Host smart-803cd418-4c09-4d22-999e-51deb88a1a74
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362952677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.362952677
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3573958537
Short name T708
Test name
Test status
Simulation time 267858447 ps
CPU time 5.04 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 12:53:30 PM PST 24
Peak memory 202932 kb
Host smart-d8c01437-ca15-40bd-8c4d-a1e66e1da368
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573958537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3573958537
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.3605752032
Short name T241
Test name
Test status
Simulation time 3803105687 ps
CPU time 1311.77 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 01:14:29 PM PST 24
Peak memory 371564 kb
Host smart-f587ba78-9da2-4c64-8510-181a4899deae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605752032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.3605752032
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.1191439822
Short name T222
Test name
Test status
Simulation time 775418630 ps
CPU time 6.83 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:52:46 PM PST 24
Peak memory 202912 kb
Host smart-12ccd352-1fcc-4307-89c3-5d83c9f15d25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191439822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.1191439822
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3483372712
Short name T892
Test name
Test status
Simulation time 16661063400 ps
CPU time 433.33 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:59:51 PM PST 24
Peak memory 202964 kb
Host smart-710c4838-e223-45a3-b533-9a1056641b06
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483372712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3483372712
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.340692291
Short name T305
Test name
Test status
Simulation time 34777652 ps
CPU time 1.14 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:52:58 PM PST 24
Peak memory 203092 kb
Host smart-ba79f50e-3c53-4304-94ba-7d99c726596f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340692291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.340692291
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.4038600517
Short name T555
Test name
Test status
Simulation time 1164064180 ps
CPU time 523.17 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 01:01:30 PM PST 24
Peak memory 372664 kb
Host smart-888b3e9a-4bcf-4c89-a111-6042d2c47054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038600517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.4038600517
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.126349247
Short name T678
Test name
Test status
Simulation time 108190964 ps
CPU time 23.58 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:55 PM PST 24
Peak memory 286464 kb
Host smart-ebbe60fb-8a4e-412a-af09-b7f8ee20960f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126349247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.126349247
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.3157032723
Short name T676
Test name
Test status
Simulation time 8251018474 ps
CPU time 1643.97 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:19:55 PM PST 24
Peak memory 374684 kb
Host smart-459eb7da-2ce7-453b-9617-bc7815f2506a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157032723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.3157032723
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1503297111
Short name T750
Test name
Test status
Simulation time 2166304265 ps
CPU time 4557.99 seconds
Started Jan 03 12:52:01 PM PST 24
Finished Jan 03 02:08:03 PM PST 24
Peak memory 414740 kb
Host smart-4bb6fd28-2c28-4cd0-a166-0596220ba732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1503297111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1503297111
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.983686737
Short name T454
Test name
Test status
Simulation time 10480902990 ps
CPU time 262.97 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 12:56:44 PM PST 24
Peak memory 202928 kb
Host smart-c8e6d4b9-916c-4aa0-9a94-d11ffcc56ba8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983686737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_stress_pipeline.983686737
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1430563930
Short name T361
Test name
Test status
Simulation time 135138072 ps
CPU time 26.49 seconds
Started Jan 03 12:52:50 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 301044 kb
Host smart-8a690afd-fd86-4d4b-a378-b1cd03bfaa09
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430563930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1430563930
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1596180135
Short name T692
Test name
Test status
Simulation time 11872275318 ps
CPU time 743.27 seconds
Started Jan 03 12:52:21 PM PST 24
Finished Jan 03 01:06:11 PM PST 24
Peak memory 375812 kb
Host smart-c0162aa2-0561-44a0-86e1-74d777b9b799
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596180135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.1596180135
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2171557168
Short name T369
Test name
Test status
Simulation time 20418599 ps
CPU time 0.63 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:07 PM PST 24
Peak memory 201908 kb
Host smart-69adda7d-0055-46d7-bdb3-8c064c3d9866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171557168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2171557168
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.2662973184
Short name T733
Test name
Test status
Simulation time 5417362038 ps
CPU time 78.08 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:53:18 PM PST 24
Peak memory 202992 kb
Host smart-898aea06-d66f-4c87-8737-1a058d5c10eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662973184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.2662973184
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.468635760
Short name T262
Test name
Test status
Simulation time 2395548931 ps
CPU time 520.22 seconds
Started Jan 03 12:52:00 PM PST 24
Finished Jan 03 01:00:44 PM PST 24
Peak memory 371568 kb
Host smart-f88ac803-0921-4ef2-bac5-208cf9163dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468635760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl
e.468635760
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.599144534
Short name T26
Test name
Test status
Simulation time 322359509 ps
CPU time 4 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 202812 kb
Host smart-683c21bc-f6e8-4e96-984a-516d1333f2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599144534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc
alation.599144534
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1520219146
Short name T520
Test name
Test status
Simulation time 404026250 ps
CPU time 39.74 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 12:52:59 PM PST 24
Peak memory 316248 kb
Host smart-cb3aba03-814d-4c51-a411-d5c28ba47015
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520219146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1520219146
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2750691002
Short name T657
Test name
Test status
Simulation time 615369468 ps
CPU time 3.07 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:12 PM PST 24
Peak memory 210960 kb
Host smart-ed6f0467-80e1-40fb-8d88-67e0b5c0d88b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750691002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.2750691002
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.682680248
Short name T518
Test name
Test status
Simulation time 344799288 ps
CPU time 5.11 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:11 PM PST 24
Peak memory 202772 kb
Host smart-764d5d88-4003-4352-836a-bfa56bb8f154
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682680248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.682680248
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.203776765
Short name T976
Test name
Test status
Simulation time 27273317170 ps
CPU time 256.45 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:57:00 PM PST 24
Peak memory 367532 kb
Host smart-5a9be741-24d6-4d4f-b958-e199a6869ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203776765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip
le_keys.203776765
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.163010221
Short name T642
Test name
Test status
Simulation time 1073424203 ps
CPU time 18.14 seconds
Started Jan 03 12:51:58 PM PST 24
Finished Jan 03 12:52:20 PM PST 24
Peak memory 202824 kb
Host smart-5485c8ca-9918-4520-acf8-6f8d36830518
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163010221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.s
ram_ctrl_partial_access.163010221
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1475469128
Short name T309
Test name
Test status
Simulation time 26392037056 ps
CPU time 318.61 seconds
Started Jan 03 12:51:58 PM PST 24
Finished Jan 03 12:57:21 PM PST 24
Peak memory 202856 kb
Host smart-644185cf-cc6e-4a5f-a1db-e81a270c45d1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475469128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.1475469128
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1764852299
Short name T667
Test name
Test status
Simulation time 69182580 ps
CPU time 1.08 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:52:39 PM PST 24
Peak memory 203004 kb
Host smart-590c0ad2-7433-4b30-9e23-2b4ac2174702
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764852299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1764852299
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2042260372
Short name T450
Test name
Test status
Simulation time 13203284171 ps
CPU time 406.64 seconds
Started Jan 03 12:51:58 PM PST 24
Finished Jan 03 12:58:49 PM PST 24
Peak memory 352208 kb
Host smart-47d85b33-3cd9-4bba-8336-ae7db199af66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042260372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2042260372
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1918965666
Short name T352
Test name
Test status
Simulation time 1510976026 ps
CPU time 13.48 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:22 PM PST 24
Peak memory 202924 kb
Host smart-329cd414-83af-421f-84a7-734f43f7d670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918965666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1918965666
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.1946023500
Short name T949
Test name
Test status
Simulation time 31975710207 ps
CPU time 2217.5 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 376848 kb
Host smart-b7b37729-815d-4257-bb6b-7ff6e1cdaf92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946023500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.1946023500
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1621741809
Short name T857
Test name
Test status
Simulation time 950243190 ps
CPU time 1584.63 seconds
Started Jan 03 12:52:02 PM PST 24
Finished Jan 03 01:18:30 PM PST 24
Peak memory 431992 kb
Host smart-dea5f8e9-7057-4a91-988e-2b570137e1f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1621741809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1621741809
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1794832807
Short name T568
Test name
Test status
Simulation time 10309651965 ps
CPU time 241.93 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:56:09 PM PST 24
Peak memory 202964 kb
Host smart-de3ced37-ad5a-4a76-b02f-239918dbac69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794832807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1794832807
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1477861940
Short name T298
Test name
Test status
Simulation time 854422209 ps
CPU time 80.45 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:53:21 PM PST 24
Peak memory 357992 kb
Host smart-5b5d177b-fb2d-488c-97b8-63d407fe629e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477861940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1477861940
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1063113892
Short name T839
Test name
Test status
Simulation time 8741583363 ps
CPU time 518.2 seconds
Started Jan 03 12:52:02 PM PST 24
Finished Jan 03 01:00:44 PM PST 24
Peak memory 362344 kb
Host smart-5c64f242-380a-41cf-b4e6-ba35c8209325
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063113892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1063113892
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2128811229
Short name T787
Test name
Test status
Simulation time 21118572 ps
CPU time 0.63 seconds
Started Jan 03 12:52:20 PM PST 24
Finished Jan 03 12:53:44 PM PST 24
Peak memory 202748 kb
Host smart-15cc9534-73f7-40e9-ad2f-27cf566d6a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128811229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2128811229
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.502116547
Short name T399
Test name
Test status
Simulation time 2321640363 ps
CPU time 25.21 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:53:07 PM PST 24
Peak memory 202804 kb
Host smart-f74ae3d7-3ec2-4c03-94d4-d9269bc5c3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502116547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.
502116547
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.1275319957
Short name T593
Test name
Test status
Simulation time 6928087099 ps
CPU time 1545.51 seconds
Started Jan 03 12:52:18 PM PST 24
Finished Jan 03 01:18:31 PM PST 24
Peak memory 374784 kb
Host smart-8f1272fc-0a13-4cc7-b41b-c728f36fd2c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275319957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.1275319957
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.1559893461
Short name T507
Test name
Test status
Simulation time 731173580 ps
CPU time 79.89 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 12:53:39 PM PST 24
Peak memory 358476 kb
Host smart-862870ad-fc0e-4c58-a997-8c9c23e68b5c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559893461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.1559893461
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3930298403
Short name T79
Test name
Test status
Simulation time 768269830 ps
CPU time 4.78 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 12:53:30 PM PST 24
Peak memory 215896 kb
Host smart-ed6250c5-3f1d-427a-b6a7-95beccc6b1b7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930298403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.3930298403
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3842787490
Short name T764
Test name
Test status
Simulation time 963155898 ps
CPU time 4.79 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:52:43 PM PST 24
Peak memory 202788 kb
Host smart-0a182988-7d19-414d-8cac-d9c677f4a987
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842787490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3842787490
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1583870076
Short name T882
Test name
Test status
Simulation time 8543106405 ps
CPU time 507.89 seconds
Started Jan 03 12:52:20 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 375748 kb
Host smart-671c109d-4ce1-4492-90de-ec58e895e840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583870076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1583870076
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.2351087259
Short name T435
Test name
Test status
Simulation time 433228682 ps
CPU time 2.39 seconds
Started Jan 03 12:52:23 PM PST 24
Finished Jan 03 12:53:27 PM PST 24
Peak memory 202788 kb
Host smart-7cb87aeb-cead-4c15-a17d-5f58ca0372b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351087259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.2351087259
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1208672567
Short name T736
Test name
Test status
Simulation time 185877076246 ps
CPU time 260.98 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 12:56:42 PM PST 24
Peak memory 202920 kb
Host smart-333d0027-c3c7-415b-9b87-3b9aa2610f1a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208672567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.1208672567
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.807017757
Short name T869
Test name
Test status
Simulation time 119125577 ps
CPU time 1.15 seconds
Started Jan 03 12:52:07 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 203028 kb
Host smart-076caec7-a011-49df-8007-c2c4c706cba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807017757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.807017757
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.1239689306
Short name T876
Test name
Test status
Simulation time 15617455700 ps
CPU time 437.54 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 01:00:42 PM PST 24
Peak memory 363372 kb
Host smart-43a9d7d8-15d9-4a9f-9450-b737f543cb9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239689306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1239689306
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3076379482
Short name T509
Test name
Test status
Simulation time 1327636288 ps
CPU time 93.74 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 12:54:10 PM PST 24
Peak memory 374340 kb
Host smart-52128117-31f4-46b0-8000-15ee7d529425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076379482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3076379482
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.1868296847
Short name T536
Test name
Test status
Simulation time 33319677005 ps
CPU time 2376.7 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 01:32:15 PM PST 24
Peak memory 376896 kb
Host smart-9cc80918-540a-4587-9fc6-96910e1a4b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868296847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.1868296847
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2960941068
Short name T954
Test name
Test status
Simulation time 1006023307 ps
CPU time 3461.21 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 01:50:21 PM PST 24
Peak memory 429592 kb
Host smart-5e779fdf-77a0-48d4-8680-c011901a7be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2960941068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2960941068
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2139093250
Short name T366
Test name
Test status
Simulation time 33039201356 ps
CPU time 238.52 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:56:38 PM PST 24
Peak memory 202964 kb
Host smart-a27aa101-5555-474e-aba2-89c03e56c58f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139093250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2139093250
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.230564261
Short name T877
Test name
Test status
Simulation time 155645645 ps
CPU time 83.68 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 374380 kb
Host smart-c0df6932-a174-49fe-9659-0fc9e7b0468c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230564261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_throughput_w_partial_write.230564261
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3571836109
Short name T265
Test name
Test status
Simulation time 1376338329 ps
CPU time 465.64 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 01:01:11 PM PST 24
Peak memory 375612 kb
Host smart-52348b4e-c05e-4386-9cdb-4df1b017b343
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571836109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3571836109
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.3417526636
Short name T373
Test name
Test status
Simulation time 33678322 ps
CPU time 0.63 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:52:01 PM PST 24
Peak memory 202488 kb
Host smart-429cecde-556b-41de-8928-8dbb025da99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417526636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.3417526636
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.4073549686
Short name T806
Test name
Test status
Simulation time 2066734173 ps
CPU time 30.84 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:52 PM PST 24
Peak memory 202748 kb
Host smart-9da50af5-944e-45a5-8e67-f58ba02388f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073549686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.4073549686
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.1408261516
Short name T970
Test name
Test status
Simulation time 63862670998 ps
CPU time 1481.6 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 01:17:25 PM PST 24
Peak memory 374556 kb
Host smart-cafc1328-252f-46e2-86fb-f47a78de740b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408261516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.1408261516
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.3484729861
Short name T355
Test name
Test status
Simulation time 334376617 ps
CPU time 4.18 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:36 PM PST 24
Peak memory 213536 kb
Host smart-81133672-6932-4a65-84a5-a2935673dc3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484729861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.3484729861
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2121771914
Short name T730
Test name
Test status
Simulation time 618720687 ps
CPU time 119.85 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 366820 kb
Host smart-0a3dc436-1f52-4335-9c89-c79bdf79fa3e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121771914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2121771914
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3247710538
Short name T75
Test name
Test status
Simulation time 200422481 ps
CPU time 2.96 seconds
Started Jan 03 12:52:22 PM PST 24
Finished Jan 03 12:53:28 PM PST 24
Peak memory 212164 kb
Host smart-210aa07c-b43b-4535-bb31-5f1495985a0e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247710538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3247710538
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.3812652357
Short name T386
Test name
Test status
Simulation time 548249960 ps
CPU time 8.31 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:52:09 PM PST 24
Peak memory 202796 kb
Host smart-06bf0e24-98db-42cb-8a6f-06b691eeab49
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812652357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.3812652357
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.2582398615
Short name T973
Test name
Test status
Simulation time 74188420370 ps
CPU time 1120.34 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:11:10 PM PST 24
Peak memory 374744 kb
Host smart-19de4864-8df4-479f-aa64-42f51a5c3561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582398615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.2582398615
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.3238820622
Short name T688
Test name
Test status
Simulation time 381782936 ps
CPU time 14.79 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 12:53:40 PM PST 24
Peak memory 257476 kb
Host smart-e7eee7aa-edc3-4fb1-87f4-dead454399d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238820622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.3238820622
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3570225268
Short name T661
Test name
Test status
Simulation time 36948387901 ps
CPU time 239.13 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 203016 kb
Host smart-7b0c083a-7681-46c1-af60-f6a544b63da4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570225268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.3570225268
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.1237906569
Short name T927
Test name
Test status
Simulation time 90003122 ps
CPU time 1.07 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 12:52:13 PM PST 24
Peak memory 203108 kb
Host smart-dd20bb15-ae95-4cb0-affd-f19415123282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237906569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1237906569
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.46313171
Short name T497
Test name
Test status
Simulation time 66128196907 ps
CPU time 444.09 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 01:00:11 PM PST 24
Peak memory 321224 kb
Host smart-780af138-db68-4219-869e-ca3efebe1aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46313171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.46313171
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.2522034576
Short name T418
Test name
Test status
Simulation time 17957326535 ps
CPU time 473.05 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 01:00:12 PM PST 24
Peak memory 376360 kb
Host smart-73c0f90d-c17a-4170-ab14-dd57685b199d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522034576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.2522034576
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2761274608
Short name T705
Test name
Test status
Simulation time 9601805268 ps
CPU time 1187.18 seconds
Started Jan 03 12:51:54 PM PST 24
Finished Jan 03 01:11:47 PM PST 24
Peak memory 405236 kb
Host smart-1b907466-b1a2-4070-86ae-5627c18596eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2761274608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2761274608
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.720652836
Short name T674
Test name
Test status
Simulation time 2806401705 ps
CPU time 249.55 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:56:41 PM PST 24
Peak memory 202940 kb
Host smart-af28295e-a554-4226-b6f0-366740194aac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720652836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.720652836
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.606780527
Short name T358
Test name
Test status
Simulation time 468714188 ps
CPU time 33.5 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:53:14 PM PST 24
Peak memory 300928 kb
Host smart-69bec191-0985-45e9-a3c1-1ec68228213d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606780527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.606780527
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4285075858
Short name T856
Test name
Test status
Simulation time 9495398183 ps
CPU time 1358.96 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 01:15:16 PM PST 24
Peak memory 373736 kb
Host smart-7cdc21c8-f1db-4108-86ff-3dff02fcff74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285075858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.4285075858
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1619570419
Short name T943
Test name
Test status
Simulation time 110287546 ps
CPU time 0.68 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:52:11 PM PST 24
Peak memory 202636 kb
Host smart-5c646023-3ed3-4a44-9e76-839289f368d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619570419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1619570419
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1723857968
Short name T762
Test name
Test status
Simulation time 1556752339 ps
CPU time 20.33 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:52:21 PM PST 24
Peak memory 202812 kb
Host smart-b164400d-1916-49d6-94c1-ed22f4633a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723857968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1723857968
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.2301641031
Short name T552
Test name
Test status
Simulation time 19229750794 ps
CPU time 424.6 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:59:11 PM PST 24
Peak memory 361252 kb
Host smart-b050a7e6-a075-404c-b2d7-7e03c5897088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301641031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.2301641031
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.2617047081
Short name T737
Test name
Test status
Simulation time 40201158 ps
CPU time 2.35 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 211020 kb
Host smart-d97259a1-473b-411a-af88-0293668f914c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617047081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.2617047081
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.700276311
Short name T270
Test name
Test status
Simulation time 188755496 ps
CPU time 3.13 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:12 PM PST 24
Peak memory 211004 kb
Host smart-82c09047-829d-4c94-9e63-97e2e800ede3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700276311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_mem_partial_access.700276311
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.2414927456
Short name T524
Test name
Test status
Simulation time 937615950 ps
CPU time 5.02 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:52:49 PM PST 24
Peak memory 202852 kb
Host smart-551de0d5-cf80-4aa9-b6d0-6d7ffa5375e2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414927456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.2414927456
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3225420700
Short name T508
Test name
Test status
Simulation time 19711702252 ps
CPU time 976.5 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 01:08:19 PM PST 24
Peak memory 375640 kb
Host smart-1b604418-ede2-4604-aba7-e7843516d385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225420700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3225420700
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2937483594
Short name T293
Test name
Test status
Simulation time 325443232 ps
CPU time 5.66 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:12 PM PST 24
Peak memory 202924 kb
Host smart-ffbd3c7e-1201-403b-99b7-63becf9689ef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937483594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2937483594
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3032529355
Short name T690
Test name
Test status
Simulation time 156789494377 ps
CPU time 389.58 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:58:30 PM PST 24
Peak memory 202956 kb
Host smart-159094da-a2d4-4ce1-8c01-9a45e9c6a9c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032529355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3032529355
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1735658315
Short name T650
Test name
Test status
Simulation time 50472252 ps
CPU time 1.13 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 202960 kb
Host smart-471ab95f-1f9b-42b5-8f8d-292fbfffe96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735658315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1735658315
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.510206807
Short name T219
Test name
Test status
Simulation time 97039519062 ps
CPU time 1041.63 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:09:43 PM PST 24
Peak memory 375700 kb
Host smart-a02fb6f4-d2f2-4f96-a3f6-a841c591fc14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510206807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.510206807
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1913456248
Short name T832
Test name
Test status
Simulation time 4991764205 ps
CPU time 16.8 seconds
Started Jan 03 12:52:00 PM PST 24
Finished Jan 03 12:52:20 PM PST 24
Peak memory 202840 kb
Host smart-778d2b30-dc14-41d5-bc27-a4dc9bf011c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913456248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1913456248
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.1476006771
Short name T635
Test name
Test status
Simulation time 267738000544 ps
CPU time 2998.37 seconds
Started Jan 03 12:52:18 PM PST 24
Finished Jan 03 01:42:44 PM PST 24
Peak memory 377052 kb
Host smart-a664529c-018c-4128-9d02-fcff0c0fa747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476006771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.1476006771
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.86105484
Short name T248
Test name
Test status
Simulation time 11640973045 ps
CPU time 1667.84 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 01:20:20 PM PST 24
Peak memory 432240 kb
Host smart-add957de-273d-4efa-aaf0-35dbcc5d1e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=86105484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.86105484
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3032024931
Short name T619
Test name
Test status
Simulation time 7635122848 ps
CPU time 180.56 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 202980 kb
Host smart-87944f8a-097d-4e62-b5af-4efac95f5d0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032024931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3032024931
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2317304528
Short name T557
Test name
Test status
Simulation time 239169155 ps
CPU time 52.65 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 12:53:11 PM PST 24
Peak memory 321404 kb
Host smart-91830a5f-310d-4ef7-b8b7-cce4533da63a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317304528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2317304528
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2631134022
Short name T285
Test name
Test status
Simulation time 33738029219 ps
CPU time 539.34 seconds
Started Jan 03 12:52:21 PM PST 24
Finished Jan 03 01:02:42 PM PST 24
Peak memory 370660 kb
Host smart-5816865b-9e9b-4a0b-8d85-853353f329fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631134022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2631134022
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2253203775
Short name T272
Test name
Test status
Simulation time 37966529 ps
CPU time 0.67 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:22 PM PST 24
Peak memory 202592 kb
Host smart-61c2d08a-2a78-42b7-baf4-a3865df074ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253203775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2253203775
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.898235322
Short name T792
Test name
Test status
Simulation time 7319272183 ps
CPU time 29.05 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:53:09 PM PST 24
Peak memory 203012 kb
Host smart-286d9268-a2bb-4d68-b2bd-2225ec7db8d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898235322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
898235322
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.1662636430
Short name T791
Test name
Test status
Simulation time 25523389647 ps
CPU time 491.39 seconds
Started Jan 03 12:52:21 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 374804 kb
Host smart-436e9ef7-09f6-4d53-850b-bb139f40cabf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662636430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.1662636430
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1298384014
Short name T97
Test name
Test status
Simulation time 1189422021 ps
CPU time 3.82 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 202744 kb
Host smart-328e73b9-5920-4790-a0d7-7b6f671bbc9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298384014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1298384014
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.412824882
Short name T811
Test name
Test status
Simulation time 155645242 ps
CPU time 77.82 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:53:51 PM PST 24
Peak memory 366232 kb
Host smart-36bedc13-63b0-43e9-a0cd-e13eb5cd6b07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412824882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.412824882
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.752952613
Short name T74
Test name
Test status
Simulation time 42783311 ps
CPU time 2.88 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:52:45 PM PST 24
Peak memory 211984 kb
Host smart-5eaca9cd-44e1-4b04-a0ad-d6713b388619
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752952613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.752952613
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.1649167914
Short name T776
Test name
Test status
Simulation time 74717972 ps
CPU time 4.55 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:52:51 PM PST 24
Peak memory 202828 kb
Host smart-38556a3c-d5c6-40a8-9fbc-4eff5033dceb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649167914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.1649167914
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.2173876728
Short name T436
Test name
Test status
Simulation time 2837198787 ps
CPU time 195.46 seconds
Started Jan 03 12:52:23 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 358352 kb
Host smart-7e03407f-3cb7-4aeb-abd8-976084b1b6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173876728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.2173876728
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.4145520208
Short name T229
Test name
Test status
Simulation time 535497995 ps
CPU time 10.44 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 202780 kb
Host smart-498bbfc8-6c70-40d5-8c43-f63a1a106d2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145520208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.4145520208
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3669375022
Short name T646
Test name
Test status
Simulation time 26381903827 ps
CPU time 304.63 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:57:44 PM PST 24
Peak memory 202984 kb
Host smart-14fa7f09-4754-4d85-b6c7-ada263204493
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669375022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.3669375022
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.4036766019
Short name T302
Test name
Test status
Simulation time 111109712 ps
CPU time 1.11 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:52:40 PM PST 24
Peak memory 203064 kb
Host smart-1e8b3f88-954c-440f-8bc5-3e14aea81211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036766019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.4036766019
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.3355341790
Short name T392
Test name
Test status
Simulation time 13245522843 ps
CPU time 758.53 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 374500 kb
Host smart-73c595dd-7591-471a-b2a3-29afac80cdf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355341790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3355341790
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1376722076
Short name T549
Test name
Test status
Simulation time 826512444 ps
CPU time 12.91 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 12:52:48 PM PST 24
Peak memory 202496 kb
Host smart-d60c29ca-1bb7-4f6d-b26f-52dc90ff3bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376722076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1376722076
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.1417629660
Short name T637
Test name
Test status
Simulation time 4087955153 ps
CPU time 799.79 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 370324 kb
Host smart-c889365c-bb4d-4f16-ad48-e523f9f3332d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417629660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.1417629660
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4139697091
Short name T963
Test name
Test status
Simulation time 1932724139 ps
CPU time 5358.31 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 02:22:16 PM PST 24
Peak memory 469176 kb
Host smart-e839ae74-58b0-4826-abac-2923afb37b26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4139697091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4139697091
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1193281096
Short name T681
Test name
Test status
Simulation time 7456829517 ps
CPU time 180.82 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 202716 kb
Host smart-e4830ef8-ce09-4596-a5c1-37cab64b7a11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193281096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.1193281096
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1976054478
Short name T565
Test name
Test status
Simulation time 269333005 ps
CPU time 59.89 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:53:56 PM PST 24
Peak memory 336312 kb
Host smart-c0fce0f3-0855-4ebb-be25-bfd1adb2cf15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976054478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1976054478
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.977903132
Short name T347
Test name
Test status
Simulation time 3534265253 ps
CPU time 982.54 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 01:08:33 PM PST 24
Peak memory 375840 kb
Host smart-1423e8d2-34e5-40f8-b36f-86b65c94ef5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977903132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.977903132
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1839333568
Short name T615
Test name
Test status
Simulation time 13584422 ps
CPU time 0.67 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:07 PM PST 24
Peak memory 202792 kb
Host smart-e59e0b0a-94ae-4ad8-98ef-c73f235da8eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839333568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1839333568
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.2643237884
Short name T488
Test name
Test status
Simulation time 2182295549 ps
CPU time 54.84 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:53:27 PM PST 24
Peak memory 202812 kb
Host smart-254a8a79-e305-4e56-8ea4-24069952246f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643237884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.2643237884
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.2269998853
Short name T535
Test name
Test status
Simulation time 5598889852 ps
CPU time 514.36 seconds
Started Jan 03 12:51:53 PM PST 24
Finished Jan 03 01:00:33 PM PST 24
Peak memory 373644 kb
Host smart-92e0fa73-1e9d-47bc-b1da-4dbd8d5a1497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269998853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.2269998853
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1872845221
Short name T397
Test name
Test status
Simulation time 368821672 ps
CPU time 2.97 seconds
Started Jan 03 12:52:16 PM PST 24
Finished Jan 03 12:52:44 PM PST 24
Peak memory 219316 kb
Host smart-431ce385-f98d-4c51-a84d-43cf9d59b311
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872845221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1872845221
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.3311733317
Short name T723
Test name
Test status
Simulation time 2626196688 ps
CPU time 5.99 seconds
Started Jan 03 12:51:58 PM PST 24
Finished Jan 03 12:52:08 PM PST 24
Peak memory 202848 kb
Host smart-c670d5e5-3935-4184-8fa6-57873f704404
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311733317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.3311733317
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.3883964932
Short name T978
Test name
Test status
Simulation time 180363160 ps
CPU time 6.29 seconds
Started Jan 03 12:52:25 PM PST 24
Finished Jan 03 12:53:31 PM PST 24
Peak memory 225324 kb
Host smart-afccefe7-ab8f-41e3-bbef-cf11202baf5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883964932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.3883964932
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.992384552
Short name T747
Test name
Test status
Simulation time 63647262821 ps
CPU time 347.66 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:58:32 PM PST 24
Peak memory 203020 kb
Host smart-dbdb556c-aae4-4386-b08c-969b48c2b832
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992384552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_partial_access_b2b.992384552
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.2672913732
Short name T794
Test name
Test status
Simulation time 31506103 ps
CPU time 1.14 seconds
Started Jan 03 12:52:08 PM PST 24
Finished Jan 03 12:52:19 PM PST 24
Peak memory 203040 kb
Host smart-f2dc72ab-fa35-4bf2-ae42-921ca19bfbc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672913732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2672913732
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.4274421814
Short name T782
Test name
Test status
Simulation time 13105252085 ps
CPU time 297.93 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:56:58 PM PST 24
Peak memory 359284 kb
Host smart-d3598cae-5cd2-4013-9c4b-3f12dc8cf25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274421814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4274421814
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.4198750980
Short name T459
Test name
Test status
Simulation time 1266488776 ps
CPU time 79.83 seconds
Started Jan 03 12:52:28 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 369376 kb
Host smart-6cbfdb42-f2f3-4b0e-8402-d845a5106ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198750980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4198750980
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3066387211
Short name T941
Test name
Test status
Simulation time 15810398897 ps
CPU time 3024.74 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 01:43:50 PM PST 24
Peak memory 376892 kb
Host smart-cea15b70-9f26-43e2-8aa3-34ed09510630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066387211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3066387211
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.644458678
Short name T639
Test name
Test status
Simulation time 4494573843 ps
CPU time 4791.32 seconds
Started Jan 03 12:51:54 PM PST 24
Finished Jan 03 02:11:52 PM PST 24
Peak memory 432240 kb
Host smart-1f9dfede-cb8c-405a-8019-f6bfeb9748c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=644458678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.644458678
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1164324855
Short name T665
Test name
Test status
Simulation time 4082465339 ps
CPU time 138.94 seconds
Started Jan 03 12:52:26 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 202968 kb
Host smart-a7c1f7e3-b5f7-4ef9-bde1-b42e32058e22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164324855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1164324855
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3519010487
Short name T314
Test name
Test status
Simulation time 110713137 ps
CPU time 36.09 seconds
Started Jan 03 12:52:08 PM PST 24
Finished Jan 03 12:52:54 PM PST 24
Peak memory 303444 kb
Host smart-18ef9f0f-b063-4716-b214-e64bd2890b47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519010487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3519010487
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3651601241
Short name T280
Test name
Test status
Simulation time 8048713772 ps
CPU time 1041.77 seconds
Started Jan 03 12:52:18 PM PST 24
Finished Jan 03 01:10:06 PM PST 24
Peak memory 373704 kb
Host smart-262c7463-78c5-4f99-9bfd-bff82fc3de48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651601241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3651601241
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.1792734078
Short name T887
Test name
Test status
Simulation time 16681744 ps
CPU time 0.63 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:52:47 PM PST 24
Peak memory 202716 kb
Host smart-34b56d1e-5bb2-4c1c-81e8-43b8b13ac1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792734078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.1792734078
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2494188362
Short name T514
Test name
Test status
Simulation time 5018154507 ps
CPU time 72.15 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:53:13 PM PST 24
Peak memory 202956 kb
Host smart-0353d810-1c4b-4d25-bb21-9c458592feac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494188362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2494188362
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.1472361654
Short name T751
Test name
Test status
Simulation time 60687073940 ps
CPU time 726.27 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 01:04:45 PM PST 24
Peak memory 374268 kb
Host smart-1b7e6b8c-0b34-42dd-bc09-0939a822c25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472361654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.1472361654
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1422302574
Short name T607
Test name
Test status
Simulation time 1881636909 ps
CPU time 7.47 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 210948 kb
Host smart-3492528b-7a27-4fe0-ba97-2a2b509a2e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422302574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1422302574
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2505636416
Short name T755
Test name
Test status
Simulation time 100882500 ps
CPU time 48.73 seconds
Started Jan 03 12:52:21 PM PST 24
Finished Jan 03 12:54:14 PM PST 24
Peak memory 313656 kb
Host smart-07204c21-6d86-4f54-9625-585ffc3af8c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505636416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2505636416
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.435554227
Short name T888
Test name
Test status
Simulation time 125879628 ps
CPU time 4.62 seconds
Started Jan 03 12:52:08 PM PST 24
Finished Jan 03 12:52:22 PM PST 24
Peak memory 212540 kb
Host smart-31b0b47b-b0f2-494b-8092-81cfdae23298
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435554227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.435554227
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2585889063
Short name T956
Test name
Test status
Simulation time 272719826 ps
CPU time 8.08 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:17 PM PST 24
Peak memory 202856 kb
Host smart-998ff93f-e5d8-4550-b249-700825d5a586
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585889063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2585889063
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.4027868488
Short name T263
Test name
Test status
Simulation time 41494723792 ps
CPU time 458.97 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 12:59:51 PM PST 24
Peak memory 369196 kb
Host smart-f0f66cd2-8b54-4d0e-b99d-be30fe701372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027868488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.4027868488
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3859138200
Short name T561
Test name
Test status
Simulation time 120044482 ps
CPU time 7.68 seconds
Started Jan 03 12:52:03 PM PST 24
Finished Jan 03 12:52:14 PM PST 24
Peak memory 232572 kb
Host smart-fdd4ec81-b8f5-4bf0-ab2f-77d6a69dff8c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859138200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3859138200
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2128650152
Short name T905
Test name
Test status
Simulation time 3061020669 ps
CPU time 222.27 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 202936 kb
Host smart-58c0c0a4-fe08-48b6-8858-ee12f9a4ef24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128650152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2128650152
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.3556239235
Short name T343
Test name
Test status
Simulation time 78828111 ps
CPU time 0.87 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 12:52:14 PM PST 24
Peak memory 202844 kb
Host smart-0935e623-132b-487b-b488-7dd069fb3eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556239235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3556239235
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.769366224
Short name T915
Test name
Test status
Simulation time 3645399405 ps
CPU time 938.6 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 01:08:16 PM PST 24
Peak memory 374704 kb
Host smart-5ff9b686-f95c-4be9-bdc1-fe6b085b4f3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769366224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.769366224
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.1511504261
Short name T706
Test name
Test status
Simulation time 125153366 ps
CPU time 4.48 seconds
Started Jan 03 12:51:55 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 219276 kb
Host smart-1d31ad94-7c6f-4088-8238-53d1a47f618a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511504261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1511504261
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.1315375831
Short name T500
Test name
Test status
Simulation time 6702696092 ps
CPU time 1415.57 seconds
Started Jan 03 12:52:00 PM PST 24
Finished Jan 03 01:15:39 PM PST 24
Peak memory 366632 kb
Host smart-d8fb0a38-f79b-476e-b7a9-d77741393d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315375831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.1315375831
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.814020838
Short name T628
Test name
Test status
Simulation time 1479049220 ps
CPU time 2814.1 seconds
Started Jan 03 12:52:02 PM PST 24
Finished Jan 03 01:39:00 PM PST 24
Peak memory 419384 kb
Host smart-2cc185db-917e-46b6-a232-176d789ab7d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=814020838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.814020838
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.703457940
Short name T318
Test name
Test status
Simulation time 1605276971 ps
CPU time 148.88 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:54:40 PM PST 24
Peak memory 202904 kb
Host smart-0008aa56-6afa-4641-8d2e-4bf0daccf475
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703457940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.703457940
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3550930770
Short name T117
Test name
Test status
Simulation time 76680170 ps
CPU time 2.07 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:52:11 PM PST 24
Peak memory 210912 kb
Host smart-c9beb0f9-9003-4a0c-b19a-821a43b1781d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550930770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3550930770
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.872052151
Short name T553
Test name
Test status
Simulation time 9022972716 ps
CPU time 486.63 seconds
Started Jan 03 12:51:19 PM PST 24
Finished Jan 03 12:59:42 PM PST 24
Peak memory 375376 kb
Host smart-b5635c37-b8fb-4fa9-881a-9a2144338022
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872052151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_access_during_key_req.872052151
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1172192594
Short name T900
Test name
Test status
Simulation time 13752349 ps
CPU time 0.63 seconds
Started Jan 03 12:51:06 PM PST 24
Finished Jan 03 12:51:25 PM PST 24
Peak memory 202700 kb
Host smart-1e73b67c-be6e-481e-ab87-6107a18920fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172192594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1172192594
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.1527855399
Short name T724
Test name
Test status
Simulation time 22741019162 ps
CPU time 71.04 seconds
Started Jan 03 12:50:55 PM PST 24
Finished Jan 03 12:52:28 PM PST 24
Peak memory 202900 kb
Host smart-04de30f9-c7a0-4011-bb58-226c415db3e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527855399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
1527855399
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.2961862079
Short name T922
Test name
Test status
Simulation time 1628415005 ps
CPU time 114.86 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:53:17 PM PST 24
Peak memory 321560 kb
Host smart-a943f1f0-58d8-4483-b533-174118f4bbed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961862079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.2961862079
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.3540436381
Short name T288
Test name
Test status
Simulation time 649113646 ps
CPU time 8.88 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:31 PM PST 24
Peak memory 202764 kb
Host smart-eb72798b-6081-4020-a74f-b35925c1f2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540436381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.3540436381
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.4250865790
Short name T625
Test name
Test status
Simulation time 70690446 ps
CPU time 11.86 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 251824 kb
Host smart-3e13803a-db64-463b-86b6-7b0298b09716
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250865790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.4250865790
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3015697009
Short name T81
Test name
Test status
Simulation time 248044210 ps
CPU time 4.71 seconds
Started Jan 03 12:51:17 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 212032 kb
Host smart-6eb82d65-96fb-4d8c-a433-36bbebd34930
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015697009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.3015697009
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.1196433587
Short name T988
Test name
Test status
Simulation time 1320749202 ps
CPU time 5.66 seconds
Started Jan 03 12:51:08 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 202812 kb
Host smart-b22abc29-da19-42ca-bdd4-68e0c9f80230
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196433587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.1196433587
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.2948023141
Short name T870
Test name
Test status
Simulation time 5901979216 ps
CPU time 794.6 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 375664 kb
Host smart-620c603f-17e3-438d-9e79-3c96488527d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948023141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.2948023141
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.320814896
Short name T307
Test name
Test status
Simulation time 166766565 ps
CPU time 48.91 seconds
Started Jan 03 12:50:55 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 301784 kb
Host smart-56bcd1c9-188c-4836-86e9-292272fea707
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320814896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr
am_ctrl_partial_access.320814896
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3615035436
Short name T810
Test name
Test status
Simulation time 56704968056 ps
CPU time 379.66 seconds
Started Jan 03 12:50:51 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 202908 kb
Host smart-cb68d48b-da89-4036-93d7-0df0ea6ef8e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615035436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3615035436
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.3396220301
Short name T983
Test name
Test status
Simulation time 31660257 ps
CPU time 0.83 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 202784 kb
Host smart-68ecb93e-656f-4986-9157-1e557979fd6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396220301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3396220301
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.84728837
Short name T909
Test name
Test status
Simulation time 1184412639 ps
CPU time 117.42 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 12:53:25 PM PST 24
Peak memory 346776 kb
Host smart-7df50c30-f0fc-442f-9abd-aeb20a289abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84728837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.84728837
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3605642706
Short name T32
Test name
Test status
Simulation time 209947857 ps
CPU time 2.68 seconds
Started Jan 03 12:51:27 PM PST 24
Finished Jan 03 12:51:43 PM PST 24
Peak memory 221584 kb
Host smart-253f5096-6caf-472e-bf73-46b51142deef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605642706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3605642706
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.3577480110
Short name T945
Test name
Test status
Simulation time 230992112 ps
CPU time 3.84 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 217088 kb
Host smart-953777ed-7bdb-4b1f-9484-cb4e6e12a9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577480110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3577480110
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1634583362
Short name T728
Test name
Test status
Simulation time 69531813587 ps
CPU time 4142.85 seconds
Started Jan 03 12:50:59 PM PST 24
Finished Jan 03 02:00:23 PM PST 24
Peak memory 383016 kb
Host smart-25c6f847-ab43-4637-bfbf-c6236bef4524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634583362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1634583362
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.143519798
Short name T774
Test name
Test status
Simulation time 1771746447 ps
CPU time 2859.29 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 01:39:08 PM PST 24
Peak memory 448456 kb
Host smart-e3ffd11b-109a-4d72-84fe-37d5979136bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=143519798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.143519798
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.156764608
Short name T572
Test name
Test status
Simulation time 2592864945 ps
CPU time 243.7 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 202860 kb
Host smart-454fed92-50ca-4a21-ab2c-7263994577af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156764608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.156764608
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1849098752
Short name T711
Test name
Test status
Simulation time 47345415 ps
CPU time 4.16 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 219064 kb
Host smart-a04b51ad-379a-405f-93d9-bca8dca96393
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849098752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1849098752
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2996643383
Short name T807
Test name
Test status
Simulation time 8127401157 ps
CPU time 781.01 seconds
Started Jan 03 12:52:08 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 371656 kb
Host smart-05fe2df8-c491-4676-864f-88aa339eb3d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996643383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2996643383
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.4129745784
Short name T889
Test name
Test status
Simulation time 13582460 ps
CPU time 0.62 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:52:44 PM PST 24
Peak memory 202620 kb
Host smart-8c360698-330c-4f13-bf6a-4ed91953a9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129745784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.4129745784
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.4065730257
Short name T890
Test name
Test status
Simulation time 761809763 ps
CPU time 51.59 seconds
Started Jan 03 12:52:04 PM PST 24
Finished Jan 03 12:53:00 PM PST 24
Peak memory 202836 kb
Host smart-401a84ca-2361-4b62-9618-c3f44e705855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065730257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.4065730257
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.2344189694
Short name T132
Test name
Test status
Simulation time 2713041989 ps
CPU time 341.67 seconds
Started Jan 03 12:52:25 PM PST 24
Finished Jan 03 12:59:07 PM PST 24
Peak memory 354696 kb
Host smart-399219da-1089-43bc-963a-0f1d1245209c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344189694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.2344189694
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.239524573
Short name T446
Test name
Test status
Simulation time 337310385 ps
CPU time 5.58 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 213316 kb
Host smart-c8681b29-2d47-40db-bb2b-01560a00458a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239524573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.239524573
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.2141087766
Short name T243
Test name
Test status
Simulation time 64527558 ps
CPU time 8.3 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 12:52:49 PM PST 24
Peak memory 241552 kb
Host smart-ec54b4db-a40b-477a-893b-402c9c7369f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141087766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.2141087766
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2651718658
Short name T858
Test name
Test status
Simulation time 233553853 ps
CPU time 4.84 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:53:02 PM PST 24
Peak memory 202832 kb
Host smart-bdf74489-7ab4-4188-b85b-fe8f8934f1a2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651718658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2651718658
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.1737790562
Short name T814
Test name
Test status
Simulation time 17946213908 ps
CPU time 826.68 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 01:07:12 PM PST 24
Peak memory 376740 kb
Host smart-4f808825-2320-4b40-abd5-ce39c85dbee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737790562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.1737790562
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1801156527
Short name T223
Test name
Test status
Simulation time 603151325 ps
CPU time 8.01 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:41 PM PST 24
Peak memory 202872 kb
Host smart-caa32f70-01a8-4d77-b084-ebcef190973b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801156527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1801156527
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.1315823311
Short name T31
Test name
Test status
Simulation time 44902896 ps
CPU time 0.81 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:31 PM PST 24
Peak memory 202872 kb
Host smart-e0c58ee6-6c53-4955-baad-6406ae439d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315823311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1315823311
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.1533397471
Short name T315
Test name
Test status
Simulation time 31272901627 ps
CPU time 512.94 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 371600 kb
Host smart-ef15751b-d8c1-4b84-941e-95d1df139775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533397471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1533397471
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4255150938
Short name T648
Test name
Test status
Simulation time 756911558 ps
CPU time 11.54 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:52:51 PM PST 24
Peak memory 202832 kb
Host smart-40ba8cc6-9529-4afd-ad72-3d62eb24c79b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255150938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4255150938
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3805120501
Short name T108
Test name
Test status
Simulation time 7476423992 ps
CPU time 2489.93 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 01:34:14 PM PST 24
Peak memory 376716 kb
Host smart-0193f48a-b0c3-44ce-a950-a1be9363d298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805120501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3805120501
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3133509233
Short name T424
Test name
Test status
Simulation time 11031040572 ps
CPU time 3324.29 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 01:48:50 PM PST 24
Peak memory 433968 kb
Host smart-5e30b071-17eb-44d2-8cbb-68b4b49278cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3133509233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3133509233
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1898268631
Short name T623
Test name
Test status
Simulation time 3621912351 ps
CPU time 342.53 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:58:04 PM PST 24
Peak memory 202964 kb
Host smart-555b21a9-ce35-4d05-a361-11519f1323ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898268631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1898268631
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1263404020
Short name T684
Test name
Test status
Simulation time 115667857 ps
CPU time 6.34 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:39 PM PST 24
Peak memory 235500 kb
Host smart-3d3742bf-594e-4b92-bbeb-0168f85a30a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263404020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1263404020
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.199149006
Short name T551
Test name
Test status
Simulation time 5485682342 ps
CPU time 914.91 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 01:09:16 PM PST 24
Peak memory 375724 kb
Host smart-7f5fa173-131b-41d7-b2b6-4842436f5db0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199149006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.sram_ctrl_access_during_key_req.199149006
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2791607830
Short name T402
Test name
Test status
Simulation time 1790720638 ps
CPU time 34.64 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 202820 kb
Host smart-1290e143-c338-4a21-80a1-185be27eea3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791607830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2791607830
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1506506532
Short name T471
Test name
Test status
Simulation time 4148927420 ps
CPU time 245.12 seconds
Started Jan 03 12:52:42 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 367552 kb
Host smart-e3e4fe42-233a-492d-a6eb-dbb5b27cda33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506506532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1506506532
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.880609235
Short name T400
Test name
Test status
Simulation time 602953471 ps
CPU time 13.32 seconds
Started Jan 03 12:52:25 PM PST 24
Finished Jan 03 12:53:38 PM PST 24
Peak memory 211140 kb
Host smart-8fef3dc9-acbb-41ac-b9d3-82f8a1fe2125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880609235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.880609235
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.2482379198
Short name T770
Test name
Test status
Simulation time 169361675 ps
CPU time 2.28 seconds
Started Jan 03 12:52:43 PM PST 24
Finished Jan 03 12:54:20 PM PST 24
Peak memory 211120 kb
Host smart-2ca00cc2-c066-44d2-99a8-930c9aa61328
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482379198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.2482379198
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1243880326
Short name T951
Test name
Test status
Simulation time 585833239 ps
CPU time 4.89 seconds
Started Jan 03 12:53:05 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 216212 kb
Host smart-1299aea1-2dce-4a41-ad6a-8ee34dd9d4d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243880326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1243880326
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1298993182
Short name T122
Test name
Test status
Simulation time 2967535605 ps
CPU time 9.81 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 202968 kb
Host smart-3aa45c65-fd1e-4f68-9df0-8c1b0038f571
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298993182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1298993182
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2434935336
Short name T385
Test name
Test status
Simulation time 10571070708 ps
CPU time 150.64 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 298304 kb
Host smart-63011706-c15e-45a3-ad1b-336477952cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434935336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2434935336
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.1606220168
Short name T323
Test name
Test status
Simulation time 119649521 ps
CPU time 24.58 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 287936 kb
Host smart-0cbb5ebc-df9b-4405-82eb-34f37e7e98a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606220168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.1606220168
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3766972969
Short name T662
Test name
Test status
Simulation time 12654329982 ps
CPU time 272.94 seconds
Started Jan 03 12:52:44 PM PST 24
Finished Jan 03 12:58:51 PM PST 24
Peak memory 203024 kb
Host smart-5949efdb-4635-421a-8e17-d3dcc4f0b0a2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766972969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.3766972969
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3449870347
Short name T363
Test name
Test status
Simulation time 61668180 ps
CPU time 1.27 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 203108 kb
Host smart-7d39c3b6-5cb4-4543-b440-2f8460326bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449870347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3449870347
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.1299489664
Short name T699
Test name
Test status
Simulation time 36484009024 ps
CPU time 677.53 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 374732 kb
Host smart-1181e4df-6f57-4b93-b625-c82095ff1f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299489664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1299489664
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.1805557667
Short name T584
Test name
Test status
Simulation time 513187302 ps
CPU time 7.7 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:52:51 PM PST 24
Peak memory 202784 kb
Host smart-3360f688-4f2b-48b3-ae0f-d207be6a47c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805557667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1805557667
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.971775068
Short name T709
Test name
Test status
Simulation time 12303439454 ps
CPU time 650.51 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 369176 kb
Host smart-99330765-29cc-4017-b88a-cdfb0939da44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971775068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_stress_all.971775068
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3238070616
Short name T474
Test name
Test status
Simulation time 4378497656 ps
CPU time 1213.27 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 01:14:43 PM PST 24
Peak memory 419268 kb
Host smart-3e4cbbe1-c6aa-4e95-ae07-dd1f574d671a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3238070616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3238070616
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3458143497
Short name T362
Test name
Test status
Simulation time 28436911411 ps
CPU time 386.23 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 01:00:56 PM PST 24
Peak memory 202900 kb
Host smart-3cff6567-4125-454d-84bf-bc1ac9b1be85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458143497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3458143497
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2931202470
Short name T550
Test name
Test status
Simulation time 2687792671 ps
CPU time 65.6 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 336780 kb
Host smart-c28f4cd3-ca43-4311-919c-3f6b0151841e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931202470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2931202470
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1388873895
Short name T489
Test name
Test status
Simulation time 2892400930 ps
CPU time 806.25 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 01:08:00 PM PST 24
Peak memory 376852 kb
Host smart-d6e42033-9099-4594-894b-d04e9d3f7ba6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388873895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1388873895
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.4088476586
Short name T627
Test name
Test status
Simulation time 1819754166 ps
CPU time 36.49 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:55:01 PM PST 24
Peak memory 202784 kb
Host smart-23e76ba4-46d5-45c7-875b-99d7f37bf049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088476586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.4088476586
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.1620669501
Short name T348
Test name
Test status
Simulation time 14145126810 ps
CPU time 571.53 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 373516 kb
Host smart-ec489ee2-1800-4965-8684-06b4c8007b50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620669501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.1620669501
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.2210150619
Short name T901
Test name
Test status
Simulation time 135627163 ps
CPU time 8.29 seconds
Started Jan 03 12:53:04 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 202908 kb
Host smart-2020f36f-0e37-4dd5-ae0f-fce63b10344b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210150619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.2210150619
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.4128342080
Short name T893
Test name
Test status
Simulation time 7804074307 ps
CPU time 64.26 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 294308 kb
Host smart-19aac116-93f0-4acd-b48d-2fb0ae6f6691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128342080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.4128342080
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2718446201
Short name T757
Test name
Test status
Simulation time 98438607 ps
CPU time 2.05 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:26 PM PST 24
Peak memory 202928 kb
Host smart-7282b8d3-ff9a-4cbc-8cb8-ac05d3829f2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718446201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2718446201
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.4081804105
Short name T582
Test name
Test status
Simulation time 1441207630 ps
CPU time 26.38 seconds
Started Jan 03 12:53:04 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 285644 kb
Host smart-19afb2c5-554a-42f8-b9fb-ebee2c9ca4de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081804105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.4081804105
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.853847742
Short name T287
Test name
Test status
Simulation time 7080428962 ps
CPU time 105.82 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 211148 kb
Host smart-0debbb68-309b-4f29-b565-7df9676d31eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853847742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_stress_all.853847742
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.979641230
Short name T531
Test name
Test status
Simulation time 6738646933 ps
CPU time 164.48 seconds
Started Jan 03 12:52:43 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 202992 kb
Host smart-ad945755-4be6-4e17-b1c1-0473d5ddf2ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979641230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.979641230
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1556951241
Short name T235
Test name
Test status
Simulation time 453254352 ps
CPU time 34.43 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 318064 kb
Host smart-1b4f2dc9-ee95-45bd-be3e-6455df6f63b7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556951241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1556951241
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.813921872
Short name T505
Test name
Test status
Simulation time 1405657360 ps
CPU time 351.44 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 371820 kb
Host smart-0751bfee-99a8-48f2-83ca-f12910049b18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813921872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.813921872
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1165687638
Short name T908
Test name
Test status
Simulation time 13673006 ps
CPU time 0.63 seconds
Started Jan 03 12:52:43 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 201864 kb
Host smart-4153c0f5-dbb2-4580-9e90-436f08805c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165687638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1165687638
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.1720816405
Short name T543
Test name
Test status
Simulation time 1443546935 ps
CPU time 22.57 seconds
Started Jan 03 12:52:26 PM PST 24
Finished Jan 03 12:53:47 PM PST 24
Peak memory 202868 kb
Host smart-dae63c82-a2eb-47f3-877e-efa34fd51acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720816405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.1720816405
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.3804109736
Short name T961
Test name
Test status
Simulation time 8070045207 ps
CPU time 839.1 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 01:08:26 PM PST 24
Peak memory 373656 kb
Host smart-b1a2fabf-53e2-402a-bb16-9c2e9321034b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804109736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.3804109736
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.2582866435
Short name T465
Test name
Test status
Simulation time 503206176 ps
CPU time 7.44 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 213492 kb
Host smart-906019a5-7ae9-4bfd-a634-5d3126212d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582866435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.2582866435
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3874847390
Short name T721
Test name
Test status
Simulation time 480774595 ps
CPU time 68.11 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 347472 kb
Host smart-6ca2a45f-7965-45c7-97ee-5d3fa7c00b1b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874847390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3874847390
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.836174623
Short name T912
Test name
Test status
Simulation time 176508229 ps
CPU time 2.85 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:18 PM PST 24
Peak memory 211148 kb
Host smart-9f62e2d5-0b7e-465f-88e5-cbd316395ba0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836174623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_mem_partial_access.836174623
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.364385041
Short name T374
Test name
Test status
Simulation time 4714211284 ps
CPU time 6.59 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 202964 kb
Host smart-76cff427-8601-4516-a509-c718fe323b0d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364385041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.364385041
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3948078211
Short name T849
Test name
Test status
Simulation time 1803055066 ps
CPU time 273.98 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 12:58:39 PM PST 24
Peak memory 368584 kb
Host smart-8c1e274a-4abc-4749-b059-0eb4675ee430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948078211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3948078211
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.4091195542
Short name T382
Test name
Test status
Simulation time 53006947 ps
CPU time 0.85 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 202836 kb
Host smart-43263fd6-3ea3-45bb-8f96-b8dbbf33e736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091195542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.4091195542
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.218486918
Short name T710
Test name
Test status
Simulation time 6273936138 ps
CPU time 409.03 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 01:01:15 PM PST 24
Peak memory 362424 kb
Host smart-f55d824e-a2b2-4185-b0d6-b61f5c56718d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218486918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.218486918
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.1506624609
Short name T959
Test name
Test status
Simulation time 1260089269 ps
CPU time 40.99 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 317264 kb
Host smart-67181a4c-fa72-4c37-9f15-9a10a7dcf18a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506624609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1506624609
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.1313547925
Short name T480
Test name
Test status
Simulation time 8900542215 ps
CPU time 251.79 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 12:58:12 PM PST 24
Peak memory 374092 kb
Host smart-f9993fa4-2061-48a3-880c-416bb192d4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313547925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.1313547925
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3307881750
Short name T433
Test name
Test status
Simulation time 520942868 ps
CPU time 1526.56 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 01:19:30 PM PST 24
Peak memory 405256 kb
Host smart-54053698-0d66-4a0b-a9c8-315c31d2834a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3307881750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3307881750
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1727028377
Short name T390
Test name
Test status
Simulation time 22372151564 ps
CPU time 2345.63 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 01:33:09 PM PST 24
Peak memory 375780 kb
Host smart-ff970a5a-c5dd-46e5-9734-61542db020b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727028377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1727028377
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.395205935
Short name T875
Test name
Test status
Simulation time 76742203 ps
CPU time 0.63 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202020 kb
Host smart-dbf5c5e4-e4b0-4035-b92b-3f7cbc769aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395205935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.395205935
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.1504049835
Short name T342
Test name
Test status
Simulation time 4965397124 ps
CPU time 288.42 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:59:57 PM PST 24
Peak memory 346812 kb
Host smart-d3428cb1-c317-4dff-90ab-cf600de53624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504049835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.1504049835
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3647987214
Short name T3
Test name
Test status
Simulation time 1720106598 ps
CPU time 12.66 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 202836 kb
Host smart-1eab4b6d-9384-44e1-abdc-4f0fde1b1ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647987214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3647987214
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.1277647749
Short name T313
Test name
Test status
Simulation time 47373858 ps
CPU time 2.16 seconds
Started Jan 03 12:52:43 PM PST 24
Finished Jan 03 12:54:20 PM PST 24
Peak memory 211104 kb
Host smart-f0d4d55c-89e0-4146-af46-5b066c0cfd12
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277647749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.1277647749
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3484651322
Short name T253
Test name
Test status
Simulation time 322623076 ps
CPU time 4.48 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 212092 kb
Host smart-826e885a-6276-498e-92d0-b9c63abf73e4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484651322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3484651322
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.2450196228
Short name T783
Test name
Test status
Simulation time 526117146 ps
CPU time 8.11 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 202948 kb
Host smart-7c010fd6-5635-4ee4-a803-48d42b1efd06
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450196228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.2450196228
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.188652143
Short name T859
Test name
Test status
Simulation time 553556666 ps
CPU time 93.61 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:56:03 PM PST 24
Peak memory 347768 kb
Host smart-71c77a91-40cc-4f88-91a9-4d52883c656c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188652143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip
le_keys.188652143
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.2859067206
Short name T260
Test name
Test status
Simulation time 1512351561 ps
CPU time 24.26 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 287060 kb
Host smart-594cb0f4-a0f6-4c9b-aa8c-03b829b60ac3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859067206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.2859067206
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1484133547
Short name T596
Test name
Test status
Simulation time 10670594516 ps
CPU time 264.25 seconds
Started Jan 03 12:52:58 PM PST 24
Finished Jan 03 12:58:48 PM PST 24
Peak memory 203016 kb
Host smart-f3291d7e-301e-4007-8695-e54a2eac3dab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484133547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1484133547
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.1433596119
Short name T738
Test name
Test status
Simulation time 367114660 ps
CPU time 0.89 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 202884 kb
Host smart-4c1c60d8-28f3-4532-b20a-5ee6de52e6b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433596119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1433596119
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.332556490
Short name T911
Test name
Test status
Simulation time 53968350606 ps
CPU time 805.67 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 01:07:50 PM PST 24
Peak memory 368852 kb
Host smart-2c0573fc-b2b2-4875-b3c0-c504def8efb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332556490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.332556490
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3426574915
Short name T254
Test name
Test status
Simulation time 93099565 ps
CPU time 1.49 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 202804 kb
Host smart-0d5bcdc7-0c44-4f31-864e-5b96012fcf75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426574915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3426574915
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.3845125979
Short name T748
Test name
Test status
Simulation time 48645556899 ps
CPU time 1788.15 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 01:24:15 PM PST 24
Peak memory 371696 kb
Host smart-a6b3c206-be11-425b-8356-4e517fbe27ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845125979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.3845125979
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1402204482
Short name T537
Test name
Test status
Simulation time 1228523718 ps
CPU time 1527.93 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 01:19:27 PM PST 24
Peak memory 404836 kb
Host smart-a87b3a9f-910b-4d7a-be15-7fd235f8886f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1402204482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1402204482
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2355019315
Short name T411
Test name
Test status
Simulation time 6578701763 ps
CPU time 295.8 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 12:59:14 PM PST 24
Peak memory 202916 kb
Host smart-a4cdac9e-1256-49c5-8312-2e6058b9291c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355019315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2355019315
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3888467526
Short name T563
Test name
Test status
Simulation time 153776516 ps
CPU time 61.01 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 343948 kb
Host smart-5abb01e1-4b19-4eb6-a083-77e9a4861360
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888467526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3888467526
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.589342202
Short name T545
Test name
Test status
Simulation time 4093499266 ps
CPU time 356.31 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 374736 kb
Host smart-7ad4f923-498f-4ca3-9baf-f4ab1545d51c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589342202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.589342202
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.3209927638
Short name T453
Test name
Test status
Simulation time 19677779 ps
CPU time 0.62 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 202600 kb
Host smart-232045ed-9558-41ba-a8ae-875cc985dea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209927638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.3209927638
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3420580806
Short name T401
Test name
Test status
Simulation time 3721959514 ps
CPU time 56.6 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 203056 kb
Host smart-9e4435ac-f0d4-48cf-b8f8-ef326c406cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420580806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3420580806
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.3773491154
Short name T666
Test name
Test status
Simulation time 12771449915 ps
CPU time 578.81 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 01:04:21 PM PST 24
Peak memory 359452 kb
Host smart-61e32064-6681-4ed9-9d59-bfd28ce05639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773491154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.3773491154
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1202358999
Short name T540
Test name
Test status
Simulation time 54006307 ps
CPU time 3.21 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 216100 kb
Host smart-142559c9-7db8-4b34-a170-a3ec1db3e51a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202358999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1202358999
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.150671952
Short name T80
Test name
Test status
Simulation time 159167581 ps
CPU time 4.88 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:20 PM PST 24
Peak memory 210976 kb
Host smart-4485f2bf-7adb-46b3-9b92-977f0049afc2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150671952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_mem_partial_access.150671952
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3555300203
Short name T250
Test name
Test status
Simulation time 75639287 ps
CPU time 4.23 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 202792 kb
Host smart-ad6b3c9a-d1a3-4aff-8f7f-748b9ccba9ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555300203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3555300203
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3995583241
Short name T823
Test name
Test status
Simulation time 5632682220 ps
CPU time 417.26 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 367440 kb
Host smart-2d4f754a-53bc-4145-9495-5782c781220f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995583241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3995583241
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.1297433411
Short name T895
Test name
Test status
Simulation time 992018471 ps
CPU time 75.64 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 322488 kb
Host smart-ce98d48c-249c-419b-896d-534ebfef42b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297433411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.1297433411
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.829533328
Short name T740
Test name
Test status
Simulation time 16757345804 ps
CPU time 409.8 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 01:01:50 PM PST 24
Peak memory 202688 kb
Host smart-8a5b48e0-5374-4a6a-8bc2-6b15c08a00b7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829533328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.sram_ctrl_partial_access_b2b.829533328
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1353114030
Short name T828
Test name
Test status
Simulation time 2185536246 ps
CPU time 125.62 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 333668 kb
Host smart-49f35487-f282-4658-aecf-d3643b90400a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353114030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1353114030
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1857373710
Short name T975
Test name
Test status
Simulation time 1601527171 ps
CPU time 15.22 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 202996 kb
Host smart-0a6d9f93-6b00-43e8-ad3f-a03ddae945c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857373710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1857373710
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.739343141
Short name T707
Test name
Test status
Simulation time 262886289091 ps
CPU time 4031.65 seconds
Started Jan 03 12:53:12 PM PST 24
Finished Jan 03 02:01:35 PM PST 24
Peak memory 377796 kb
Host smart-d35c2ded-87d9-449b-955d-d5e2284a2e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739343141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.739343141
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2734773088
Short name T695
Test name
Test status
Simulation time 708005024 ps
CPU time 3015.41 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 01:44:54 PM PST 24
Peak memory 413408 kb
Host smart-f02ef32a-3597-4997-9472-15bc03b00b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2734773088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2734773088
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3722802356
Short name T717
Test name
Test status
Simulation time 3290641584 ps
CPU time 307.85 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:59:26 PM PST 24
Peak memory 202976 kb
Host smart-2397f958-2f6b-41e2-883c-ec66647f4f09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722802356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3722802356
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1638955393
Short name T825
Test name
Test status
Simulation time 86876203 ps
CPU time 18.49 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 272352 kb
Host smart-bc2c56a8-3ca6-4c09-a7af-f92d11eab74e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638955393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1638955393
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2645467846
Short name T952
Test name
Test status
Simulation time 2816163168 ps
CPU time 707.1 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 374744 kb
Host smart-3580ff24-ba94-4516-aa9f-6cd8a26fef67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645467846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.2645467846
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1824263288
Short name T295
Test name
Test status
Simulation time 16355369 ps
CPU time 0.64 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202680 kb
Host smart-a1e67605-abc9-4439-b537-fdebfde4f0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824263288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1824263288
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.294162693
Short name T824
Test name
Test status
Simulation time 13402966950 ps
CPU time 40.32 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 202984 kb
Host smart-09cb95f0-4c08-44c4-9f5e-2f80bdcaf450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294162693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.
294162693
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.2281675641
Short name T437
Test name
Test status
Simulation time 24323336987 ps
CPU time 701.53 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 370488 kb
Host smart-5db25d7b-6138-42d9-bbf3-01fbea5c0918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281675641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.2281675641
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.2048436194
Short name T440
Test name
Test status
Simulation time 3520237303 ps
CPU time 3.4 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 202856 kb
Host smart-3fff5219-2ebc-46b4-a540-bc7117e8bb44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048436194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.2048436194
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.696341441
Short name T466
Test name
Test status
Simulation time 176554751 ps
CPU time 27.88 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 297296 kb
Host smart-be8462c2-cb99-468c-8d13-235f47d07156
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696341441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.sram_ctrl_max_throughput.696341441
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.688360657
Short name T585
Test name
Test status
Simulation time 167997556 ps
CPU time 5.06 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 211136 kb
Host smart-3d1b0eeb-e735-44a7-ba11-d010f12006e2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688360657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_mem_partial_access.688360657
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.745269789
Short name T786
Test name
Test status
Simulation time 934174218 ps
CPU time 8.29 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 202840 kb
Host smart-d1fca032-ea47-47e6-8665-b143316ba258
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745269789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.745269789
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.4129453559
Short name T575
Test name
Test status
Simulation time 4295514345 ps
CPU time 632.72 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 371780 kb
Host smart-345550ae-d53b-44a7-9221-25b7848110fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129453559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.4129453559
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.1189491918
Short name T758
Test name
Test status
Simulation time 854969364 ps
CPU time 11.38 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 202936 kb
Host smart-77c977e1-6c6e-4778-8802-b518907161cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189491918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.1189491918
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3227803819
Short name T467
Test name
Test status
Simulation time 18933675560 ps
CPU time 312.48 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:59:50 PM PST 24
Peak memory 202856 kb
Host smart-af240beb-0445-41b6-94fc-df23634d78af
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227803819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.3227803819
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.4283534312
Short name T30
Test name
Test status
Simulation time 35409682 ps
CPU time 1.18 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 203048 kb
Host smart-7402c9b6-18a5-4eb0-926f-9c834b505493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283534312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.4283534312
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.632727156
Short name T10
Test name
Test status
Simulation time 15925093984 ps
CPU time 1201.18 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 01:14:45 PM PST 24
Peak memory 372868 kb
Host smart-8f41bea4-0859-4098-8eff-e75a7cfad154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632727156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.632727156
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3805186678
Short name T854
Test name
Test status
Simulation time 1016813502 ps
CPU time 14.14 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 202756 kb
Host smart-a14e75ca-fcfe-4e4b-8df6-33a3bd7448e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805186678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3805186678
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.3139075312
Short name T848
Test name
Test status
Simulation time 54692648330 ps
CPU time 2604.87 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 01:37:30 PM PST 24
Peak memory 382988 kb
Host smart-6034dfcf-72fa-41c4-bc4c-8644ab4dabf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139075312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.3139075312
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3410588271
Short name T841
Test name
Test status
Simulation time 3924317985 ps
CPU time 3115.09 seconds
Started Jan 03 12:53:12 PM PST 24
Finished Jan 03 01:46:22 PM PST 24
Peak memory 403244 kb
Host smart-e0073d8b-93e9-4dc5-9215-2501d137f850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3410588271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3410588271
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3053768027
Short name T395
Test name
Test status
Simulation time 3005499665 ps
CPU time 281.73 seconds
Started Jan 03 12:52:44 PM PST 24
Finished Jan 03 12:58:57 PM PST 24
Peak memory 202936 kb
Host smart-21fbc8ff-462e-4985-b19a-25f3814a5239
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053768027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.3053768027
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2825487117
Short name T957
Test name
Test status
Simulation time 144745710 ps
CPU time 65.12 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:56:33 PM PST 24
Peak memory 335732 kb
Host smart-24d18fc1-a3f8-4cf3-a5a9-2d966eebe782
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825487117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2825487117
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.395613648
Short name T499
Test name
Test status
Simulation time 2896902287 ps
CPU time 674.79 seconds
Started Jan 03 12:53:06 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 373712 kb
Host smart-492fddb2-cc08-47e6-9885-0b6b35ffe23a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395613648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.sram_ctrl_access_during_key_req.395613648
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1570593464
Short name T473
Test name
Test status
Simulation time 32903757 ps
CPU time 0.62 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 202556 kb
Host smart-9df0c83d-d32b-4965-80c7-e8cc8dd14f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570593464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1570593464
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.1324212600
Short name T252
Test name
Test status
Simulation time 540983583 ps
CPU time 33.9 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 202788 kb
Host smart-4c7dcfee-41ba-445a-b3b2-b086f10fa9af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324212600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.1324212600
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.2542908336
Short name T891
Test name
Test status
Simulation time 13287477316 ps
CPU time 778.12 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 01:06:59 PM PST 24
Peak memory 373692 kb
Host smart-03e81c2e-8b71-4f35-a7cb-87f090be99bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542908336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.2542908336
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3754865070
Short name T944
Test name
Test status
Simulation time 1480458571 ps
CPU time 10.2 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 211052 kb
Host smart-88dfeb3a-a818-4941-9f86-20010ad28de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754865070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3754865070
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3226733023
Short name T325
Test name
Test status
Simulation time 89618777 ps
CPU time 18.06 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 277724 kb
Host smart-7f6cb2fd-9845-4d7c-9e1e-d03640121cab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226733023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3226733023
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3336578195
Short name T641
Test name
Test status
Simulation time 177080203 ps
CPU time 4.82 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 12:54:06 PM PST 24
Peak memory 211020 kb
Host smart-3783496a-b753-4e87-909f-615ee89b2362
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336578195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3336578195
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.980978188
Short name T510
Test name
Test status
Simulation time 519690900 ps
CPU time 8.14 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 202740 kb
Host smart-aa57f90c-e703-4c55-950d-2fba760c381f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980978188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl
_mem_walk.980978188
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.63030385
Short name T256
Test name
Test status
Simulation time 55696035162 ps
CPU time 558.13 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 01:03:33 PM PST 24
Peak memory 344284 kb
Host smart-c3ca2a6f-50b0-4c14-b4cb-e37ce807719f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63030385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multipl
e_keys.63030385
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1357576280
Short name T455
Test name
Test status
Simulation time 155302288 ps
CPU time 34.25 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 296756 kb
Host smart-a8c521e4-c435-44d0-a97d-0d08901012de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357576280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1357576280
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4108483991
Short name T351
Test name
Test status
Simulation time 3446866078 ps
CPU time 236.43 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:58:26 PM PST 24
Peak memory 202900 kb
Host smart-4afbf1eb-cbb1-4dc5-acdb-22b6e301b35a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108483991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.4108483991
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.1585336503
Short name T554
Test name
Test status
Simulation time 26949617 ps
CPU time 0.86 seconds
Started Jan 03 12:53:06 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 202852 kb
Host smart-f033aa8b-19bc-4884-a4c6-569b3563f2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585336503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1585336503
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.826189735
Short name T396
Test name
Test status
Simulation time 49240747148 ps
CPU time 820.08 seconds
Started Jan 03 12:53:06 PM PST 24
Finished Jan 03 01:07:40 PM PST 24
Peak memory 373904 kb
Host smart-f28373f2-2e4e-4c8d-a3c4-41aa9c0be914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826189735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.826189735
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.668398533
Short name T118
Test name
Test status
Simulation time 868468195 ps
CPU time 31.84 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 298944 kb
Host smart-0a11e560-d5b8-4919-aa5c-cdc526fbd746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668398533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.668398533
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4059404311
Short name T299
Test name
Test status
Simulation time 7091330591 ps
CPU time 3958.2 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 02:00:23 PM PST 24
Peak memory 434000 kb
Host smart-8e7ca57e-114a-483e-842b-60ff09ec69ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4059404311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.4059404311
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.444715012
Short name T548
Test name
Test status
Simulation time 3042966210 ps
CPU time 143.24 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 202912 kb
Host smart-45a3f630-bfcc-43d7-979d-25251a751d9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444715012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_stress_pipeline.444715012
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3874331779
Short name T874
Test name
Test status
Simulation time 572477595 ps
CPU time 100.04 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 366352 kb
Host smart-d4fe4e7c-7a81-4bec-9010-a4c478baa230
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874331779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3874331779
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3430340708
Short name T383
Test name
Test status
Simulation time 2395608222 ps
CPU time 815.07 seconds
Started Jan 03 12:53:29 PM PST 24
Finished Jan 03 01:07:58 PM PST 24
Peak memory 375800 kb
Host smart-9a12625b-0dae-4827-95d8-1282a4dd3d59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430340708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3430340708
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2563850444
Short name T19
Test name
Test status
Simulation time 30543933 ps
CPU time 0.64 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 201872 kb
Host smart-222ab144-4ce9-4d5c-9fd8-076fdf9aa16b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563850444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2563850444
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.623932461
Short name T242
Test name
Test status
Simulation time 1042856234 ps
CPU time 17.72 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 202924 kb
Host smart-38b39780-efe9-4d16-9c48-3383128031c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623932461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
623932461
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.405319061
Short name T460
Test name
Test status
Simulation time 41005599420 ps
CPU time 763.89 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 365736 kb
Host smart-3ed65958-cc3c-4581-bdb4-68341aef3503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405319061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.405319061
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.61052381
Short name T921
Test name
Test status
Simulation time 5000778747 ps
CPU time 9.21 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 211172 kb
Host smart-6e11d8d7-2525-430a-a0e6-754e37675dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61052381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esca
lation.61052381
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.905714670
Short name T127
Test name
Test status
Simulation time 101732986 ps
CPU time 40.22 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 314132 kb
Host smart-4e2466e4-154c-4b83-a1b9-3fa452345e29
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905714670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.905714670
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4184690500
Short name T950
Test name
Test status
Simulation time 226904974 ps
CPU time 4.51 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:10 PM PST 24
Peak memory 211032 kb
Host smart-734a90b2-7da3-4a80-bfa1-aa1678662093
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184690500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.4184690500
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1331625502
Short name T835
Test name
Test status
Simulation time 892783665 ps
CPU time 4.82 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 202840 kb
Host smart-e73fbc99-7c15-4d64-8cca-38bc5c9139f4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331625502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1331625502
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3549398447
Short name T517
Test name
Test status
Simulation time 14658010847 ps
CPU time 412.88 seconds
Started Jan 03 12:52:50 PM PST 24
Finished Jan 03 01:01:31 PM PST 24
Peak memory 349436 kb
Host smart-9af00c7c-18af-4386-96c7-b5c2862dd549
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549398447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3549398447
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.3332068469
Short name T715
Test name
Test status
Simulation time 691992723 ps
CPU time 12.02 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 202828 kb
Host smart-9ebe95da-65ad-4dc5-a290-2224ca55f0a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332068469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.3332068469
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1632572857
Short name T569
Test name
Test status
Simulation time 55983272701 ps
CPU time 303.84 seconds
Started Jan 03 12:53:11 PM PST 24
Finished Jan 03 12:59:30 PM PST 24
Peak memory 202996 kb
Host smart-dcfb98a6-1657-4894-bacd-1a82d07e36f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632572857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1632572857
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3127594734
Short name T720
Test name
Test status
Simulation time 39600876 ps
CPU time 1.43 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 203116 kb
Host smart-a0f035d8-a11c-4c52-8fb6-0fc376f7eec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127594734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3127594734
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3758225814
Short name T718
Test name
Test status
Simulation time 12814674975 ps
CPU time 543.41 seconds
Started Jan 03 12:53:12 PM PST 24
Finished Jan 03 01:03:04 PM PST 24
Peak memory 373936 kb
Host smart-b9e97b78-9887-4eb4-ab6d-b0fd1bf6eb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758225814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3758225814
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1088679319
Short name T562
Test name
Test status
Simulation time 1340562470 ps
CPU time 7.73 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 202888 kb
Host smart-933b44ac-cfbc-413e-9289-07fcb9a4f92e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088679319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1088679319
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.275645743
Short name T649
Test name
Test status
Simulation time 231279987 ps
CPU time 2185.69 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 01:31:49 PM PST 24
Peak memory 415240 kb
Host smart-105b54f4-3426-4dfd-b542-7202123a9304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=275645743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.275645743
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.390457326
Short name T53
Test name
Test status
Simulation time 40630477577 ps
CPU time 370.91 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 01:00:10 PM PST 24
Peak memory 203040 kb
Host smart-9867b3c3-cf07-45bc-8c3d-d3a5f99d34bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390457326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.390457326
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3619885312
Short name T653
Test name
Test status
Simulation time 178357375 ps
CPU time 77.47 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 366152 kb
Host smart-3ea96e49-775f-447e-bdcb-95dbc9da2b57
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619885312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3619885312
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3515012517
Short name T850
Test name
Test status
Simulation time 2458619737 ps
CPU time 659.06 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 373720 kb
Host smart-6a9eafd8-edfb-49b9-ba15-dc215b5cad2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515012517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.3515012517
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.3198986776
Short name T227
Test name
Test status
Simulation time 20220694 ps
CPU time 0.64 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202624 kb
Host smart-26802b75-042c-4675-9f2b-bc05ae1583fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198986776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.3198986776
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.4061801247
Short name T836
Test name
Test status
Simulation time 31791364058 ps
CPU time 76.9 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 12:55:28 PM PST 24
Peak memory 202952 kb
Host smart-87036e8c-b679-4c95-b20f-0321027b7c32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061801247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.4061801247
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1857690665
Short name T886
Test name
Test status
Simulation time 86222993552 ps
CPU time 826.18 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 01:07:54 PM PST 24
Peak memory 374696 kb
Host smart-bfd9999a-952f-4579-be8b-4e2cd18fca68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857690665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1857690665
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.67360506
Short name T714
Test name
Test status
Simulation time 266496173 ps
CPU time 14.18 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 255864 kb
Host smart-7309bf82-a078-44c9-a416-0505c7080907
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67360506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.sram_ctrl_max_throughput.67360506
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2841067547
Short name T966
Test name
Test status
Simulation time 172713576 ps
CPU time 5.03 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 211988 kb
Host smart-bedd1bd0-b54a-4786-b83e-48a076bafab0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841067547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2841067547
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.3602611993
Short name T781
Test name
Test status
Simulation time 333632395 ps
CPU time 5.53 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 202808 kb
Host smart-9bbcdcca-5a2a-4658-aa0b-15406a8cb90f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602611993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.3602611993
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.738011176
Short name T115
Test name
Test status
Simulation time 4944362066 ps
CPU time 393.27 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 01:01:03 PM PST 24
Peak memory 368636 kb
Host smart-2009c9ea-fa90-43d8-90f6-a522d7515d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738011176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip
le_keys.738011176
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.670841624
Short name T769
Test name
Test status
Simulation time 2623440269 ps
CPU time 68.58 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 357360 kb
Host smart-d55ed09a-3fe6-44f8-9949-ec8ec0775122
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670841624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s
ram_ctrl_partial_access.670841624
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.3690245431
Short name T286
Test name
Test status
Simulation time 74779048 ps
CPU time 1.05 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 12:54:07 PM PST 24
Peak memory 203020 kb
Host smart-bea0f57f-cd88-4d6c-bb7d-a0f9e6c6f99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690245431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3690245431
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2790285480
Short name T328
Test name
Test status
Simulation time 106584040516 ps
CPU time 578.85 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 374736 kb
Host smart-2cb870dd-d674-403b-a9e9-d770c8eda7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790285480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2790285480
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3442738293
Short name T246
Test name
Test status
Simulation time 349959103 ps
CPU time 5.91 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:54:14 PM PST 24
Peak memory 202916 kb
Host smart-514c75be-2119-42d1-9c5b-329c1c70275e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442738293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3442738293
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.2689922917
Short name T608
Test name
Test status
Simulation time 130271821511 ps
CPU time 912.37 seconds
Started Jan 03 12:53:05 PM PST 24
Finished Jan 03 01:09:12 PM PST 24
Peak memory 366140 kb
Host smart-a199879c-cd97-4d47-9413-acb025e07e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689922917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.2689922917
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1593078349
Short name T544
Test name
Test status
Simulation time 49735840513 ps
CPU time 292.86 seconds
Started Jan 03 12:52:50 PM PST 24
Finished Jan 03 12:58:52 PM PST 24
Peak memory 202996 kb
Host smart-55ef7319-7491-4e0b-9134-643f9445b299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593078349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.1593078349
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1405120796
Short name T845
Test name
Test status
Simulation time 6247188239 ps
CPU time 960.49 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 01:07:47 PM PST 24
Peak memory 374740 kb
Host smart-dee1503a-e345-4af6-aa38-ea3b129d7385
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405120796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.1405120796
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.23013931
Short name T946
Test name
Test status
Simulation time 35837630 ps
CPU time 0.66 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:51:54 PM PST 24
Peak memory 201856 kb
Host smart-18bced90-fc65-4b4c-81a9-594e300f3107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23013931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_alert_test.23013931
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2425484576
Short name T461
Test name
Test status
Simulation time 20759708815 ps
CPU time 83.97 seconds
Started Jan 03 12:51:24 PM PST 24
Finished Jan 03 12:53:02 PM PST 24
Peak memory 203052 kb
Host smart-2c2aab3d-3701-46dd-b9e1-1896399ed9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425484576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2425484576
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.819241005
Short name T701
Test name
Test status
Simulation time 53731865391 ps
CPU time 993.51 seconds
Started Jan 03 12:51:47 PM PST 24
Finished Jan 03 01:08:29 PM PST 24
Peak memory 374756 kb
Host smart-839a4d26-e99f-4f0a-b10d-50307dad72e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819241005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable
.819241005
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.2379892669
Short name T925
Test name
Test status
Simulation time 1268587988 ps
CPU time 5.05 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:51:52 PM PST 24
Peak memory 202904 kb
Host smart-5064160d-f43f-4b21-9a61-5210928fa054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379892669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.2379892669
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.2320020511
Short name T495
Test name
Test status
Simulation time 147772118 ps
CPU time 17.28 seconds
Started Jan 03 12:51:30 PM PST 24
Finished Jan 03 12:52:00 PM PST 24
Peak memory 268316 kb
Host smart-7b3f127d-7af2-4fea-bc84-b5306f7a7916
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320020511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.2320020511
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2493885820
Short name T834
Test name
Test status
Simulation time 57078570 ps
CPU time 3.14 seconds
Started Jan 03 12:51:44 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 211324 kb
Host smart-8866e071-5f9c-41a2-af74-0610fc7bec8e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493885820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.2493885820
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.122791259
Short name T624
Test name
Test status
Simulation time 528653049 ps
CPU time 7.98 seconds
Started Jan 03 12:51:25 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 202852 kb
Host smart-8abf7612-aa59-4c31-893c-bf29979567c5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122791259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
mem_walk.122791259
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.932233485
Short name T251
Test name
Test status
Simulation time 8695384633 ps
CPU time 729.31 seconds
Started Jan 03 12:51:42 PM PST 24
Finished Jan 03 01:04:03 PM PST 24
Peak memory 368588 kb
Host smart-8726079e-a2f6-40a2-8ef1-4d1be0468ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932233485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl
e_keys.932233485
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.2237096128
Short name T521
Test name
Test status
Simulation time 1385822327 ps
CPU time 16.23 seconds
Started Jan 03 12:51:44 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 202912 kb
Host smart-0c5e649c-1773-4cd1-a427-2d11ebe4a18b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237096128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.2237096128
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3125161908
Short name T675
Test name
Test status
Simulation time 56879709108 ps
CPU time 303.04 seconds
Started Jan 03 12:51:30 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 203056 kb
Host smart-76bcf2d3-932b-410a-8226-a96399c4d849
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125161908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3125161908
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.1727601159
Short name T462
Test name
Test status
Simulation time 97032904 ps
CPU time 0.83 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:51:48 PM PST 24
Peak memory 202904 kb
Host smart-a4878a59-5b4c-4bf9-bf2d-cd677f1a6056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727601159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1727601159
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1703041608
Short name T228
Test name
Test status
Simulation time 61811049578 ps
CPU time 936.07 seconds
Started Jan 03 12:51:22 PM PST 24
Finished Jan 03 01:07:13 PM PST 24
Peak memory 371704 kb
Host smart-d7566438-3aea-45f2-9858-32ac1148b8e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703041608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1703041608
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.1528793616
Short name T21
Test name
Test status
Simulation time 306196540 ps
CPU time 3.05 seconds
Started Jan 03 12:51:24 PM PST 24
Finished Jan 03 12:51:41 PM PST 24
Peak memory 224844 kb
Host smart-c10d0ff4-f88f-475b-b3e6-1edb394ca109
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528793616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.1528793616
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3384962998
Short name T766
Test name
Test status
Simulation time 283999836 ps
CPU time 4.8 seconds
Started Jan 03 12:51:37 PM PST 24
Finished Jan 03 12:51:53 PM PST 24
Peak memory 202800 kb
Host smart-faf9473f-3486-4093-a34e-c8bc33457688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384962998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3384962998
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.527524590
Short name T96
Test name
Test status
Simulation time 13731866327 ps
CPU time 742.88 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 375700 kb
Host smart-ab09a6d9-810f-46ea-b5d4-9d3a050d80ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527524590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_stress_all.527524590
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2828475108
Short name T330
Test name
Test status
Simulation time 4779323720 ps
CPU time 4093.53 seconds
Started Jan 03 12:51:23 PM PST 24
Finished Jan 03 01:59:51 PM PST 24
Peak memory 445288 kb
Host smart-085b4bf2-3aa8-45b6-ad07-73bed4971a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2828475108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2828475108
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3223181662
Short name T968
Test name
Test status
Simulation time 6289595718 ps
CPU time 294.12 seconds
Started Jan 03 12:51:40 PM PST 24
Finished Jan 03 12:56:46 PM PST 24
Peak memory 202868 kb
Host smart-c93f0499-1d01-4630-8a30-cca2687102f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223181662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.3223181662
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.479946956
Short name T404
Test name
Test status
Simulation time 124552266 ps
CPU time 9.17 seconds
Started Jan 03 12:51:24 PM PST 24
Finished Jan 03 12:51:48 PM PST 24
Peak memory 251768 kb
Host smart-af868385-5963-43ce-a20d-cb5bdd50c2b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479946956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.479946956
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4180970225
Short name T16
Test name
Test status
Simulation time 423828568 ps
CPU time 212.01 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:58:28 PM PST 24
Peak memory 362168 kb
Host smart-a4efceb7-5920-4c2e-a6a3-60ee4037d63d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180970225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.4180970225
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.3430259386
Short name T784
Test name
Test status
Simulation time 168458906 ps
CPU time 0.66 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:19 PM PST 24
Peak memory 202644 kb
Host smart-a61667aa-fc33-4835-837f-ff7ff9aab1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430259386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.3430259386
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.595794883
Short name T878
Test name
Test status
Simulation time 1876533352 ps
CPU time 31.33 seconds
Started Jan 03 12:52:58 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 202836 kb
Host smart-23feb75e-e50c-4385-86c8-a8a4bd98462e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595794883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.
595794883
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.3060708573
Short name T746
Test name
Test status
Simulation time 178880450 ps
CPU time 1.26 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:55:19 PM PST 24
Peak memory 202824 kb
Host smart-c0097cf3-c6f5-4071-9c87-c2609563341e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060708573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.3060708573
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1542443888
Short name T394
Test name
Test status
Simulation time 252074538 ps
CPU time 2.65 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 212916 kb
Host smart-f8b244f9-12a6-4170-b5d9-289587414174
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542443888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1542443888
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3228184713
Short name T833
Test name
Test status
Simulation time 569467844 ps
CPU time 2.87 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 211144 kb
Host smart-f27b7ab0-7ac2-46df-b010-68a6c3869b67
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228184713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.3228184713
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1483187236
Short name T659
Test name
Test status
Simulation time 252642082 ps
CPU time 4.26 seconds
Started Jan 03 12:52:58 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 202832 kb
Host smart-75e5b1cd-cd6f-4655-ad44-0bc2ee287d73
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483187236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1483187236
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2574546916
Short name T412
Test name
Test status
Simulation time 10828408195 ps
CPU time 497.37 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 01:03:06 PM PST 24
Peak memory 375272 kb
Host smart-77ab2d03-378a-40bb-9a0b-0b65e2160fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574546916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2574546916
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3696315376
Short name T547
Test name
Test status
Simulation time 336323688 ps
CPU time 6.88 seconds
Started Jan 03 12:53:07 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 202824 kb
Host smart-0b861ede-07bd-44e5-a0b4-701a7748d8d7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696315376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3696315376
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.630738782
Short name T866
Test name
Test status
Simulation time 7612083645 ps
CPU time 282.96 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:59:25 PM PST 24
Peak memory 202976 kb
Host smart-07fd6eaa-de5d-4f81-8718-735156943f54
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630738782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.sram_ctrl_partial_access_b2b.630738782
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.1647134153
Short name T496
Test name
Test status
Simulation time 29401551 ps
CPU time 0.85 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 202768 kb
Host smart-bbe66bb8-4ae3-4cd6-9018-57e8c4dc1204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647134153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1647134153
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.4006982427
Short name T430
Test name
Test status
Simulation time 4294194690 ps
CPU time 281.11 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:58:47 PM PST 24
Peak memory 371636 kb
Host smart-f5ddb2c0-11c7-49a7-a7a2-554111b425b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006982427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4006982427
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2760161612
Short name T804
Test name
Test status
Simulation time 144616831 ps
CPU time 1.12 seconds
Started Jan 03 12:52:42 PM PST 24
Finished Jan 03 12:53:48 PM PST 24
Peak memory 202764 kb
Host smart-d367c196-93d4-47ca-a817-0c8b02d59729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760161612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2760161612
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3783014393
Short name T579
Test name
Test status
Simulation time 155453515287 ps
CPU time 2230.41 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 01:31:37 PM PST 24
Peak memory 375740 kb
Host smart-f52fc41e-99f8-4cc4-8be0-7a6d276fb94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783014393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3783014393
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.916897969
Short name T409
Test name
Test status
Simulation time 731268024 ps
CPU time 3717.32 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 01:56:32 PM PST 24
Peak memory 403240 kb
Host smart-1b725f38-3913-477b-ad08-474e86236c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=916897969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.916897969
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1480014071
Short name T768
Test name
Test status
Simulation time 7075276977 ps
CPU time 329.78 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 01:00:03 PM PST 24
Peak memory 203032 kb
Host smart-3b288e52-2fd4-4f16-ad43-29207516822e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480014071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.1480014071
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1411993899
Short name T41
Test name
Test status
Simulation time 949547915 ps
CPU time 25.46 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 12:54:25 PM PST 24
Peak memory 292448 kb
Host smart-3324a713-1c7a-49c9-8ded-296c6d07d1a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411993899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1411993899
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3688107008
Short name T357
Test name
Test status
Simulation time 9881718424 ps
CPU time 575.92 seconds
Started Jan 03 12:53:02 PM PST 24
Finished Jan 03 01:03:57 PM PST 24
Peak memory 372780 kb
Host smart-78f889c6-d357-4b5f-bc75-44016d23c045
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688107008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.3688107008
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.685509478
Short name T18
Test name
Test status
Simulation time 54822086 ps
CPU time 0.62 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 202616 kb
Host smart-5281f2a0-448a-4aa3-beaa-17edf9f3d049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685509478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.685509478
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.4268607580
Short name T261
Test name
Test status
Simulation time 7688352125 ps
CPU time 68.37 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:55:54 PM PST 24
Peak memory 202924 kb
Host smart-759ed198-b596-4a9e-8ead-b2d8ba141f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268607580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.4268607580
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.3904205503
Short name T472
Test name
Test status
Simulation time 5635885415 ps
CPU time 279.54 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:59:21 PM PST 24
Peak memory 373636 kb
Host smart-8d319c2c-6dec-427d-a4e7-2f9c0f07fb3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904205503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.3904205503
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2023586348
Short name T502
Test name
Test status
Simulation time 909596381 ps
CPU time 3.09 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 202860 kb
Host smart-055ca66b-6b55-4462-bde4-092b78194676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023586348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2023586348
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.928768294
Short name T359
Test name
Test status
Simulation time 234151298 ps
CPU time 52.08 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 332196 kb
Host smart-2331ab4d-ee4f-4a02-993a-bb01ad7f8b76
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928768294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.sram_ctrl_max_throughput.928768294
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1125046080
Short name T240
Test name
Test status
Simulation time 98275876 ps
CPU time 3.04 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 211056 kb
Host smart-9948564b-d84c-451c-9ed8-a8e9ae80e0db
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125046080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1125046080
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3187257194
Short name T853
Test name
Test status
Simulation time 290695703 ps
CPU time 4.71 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 202776 kb
Host smart-96f1fe81-4c68-435c-8ec6-34f3911453b0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187257194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3187257194
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.2981804702
Short name T492
Test name
Test status
Simulation time 12032493685 ps
CPU time 254.39 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:59:22 PM PST 24
Peak memory 344364 kb
Host smart-1ed6a227-d2e6-49bf-a7fe-17c080a518fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981804702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.2981804702
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.3168658067
Short name T913
Test name
Test status
Simulation time 189226751 ps
CPU time 3.91 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:00 PM PST 24
Peak memory 203036 kb
Host smart-c153a79b-850f-4f6f-bd99-bcc22220deba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168658067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.3168658067
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3765349579
Short name T475
Test name
Test status
Simulation time 62534119697 ps
CPU time 339.75 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 202912 kb
Host smart-563c2dd1-2eef-427c-90f3-f953a94266b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765349579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3765349579
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1356882654
Short name T663
Test name
Test status
Simulation time 86521980 ps
CPU time 0.9 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:16 PM PST 24
Peak memory 202928 kb
Host smart-02a08164-130f-404f-bf2c-36f51fffc085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356882654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1356882654
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.470203880
Short name T421
Test name
Test status
Simulation time 62124771790 ps
CPU time 735.11 seconds
Started Jan 03 12:53:24 PM PST 24
Finished Jan 03 01:06:24 PM PST 24
Peak memory 361184 kb
Host smart-f6696af9-9318-4b58-9d56-ff17f190f420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470203880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.470203880
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.289719526
Short name T778
Test name
Test status
Simulation time 2032848360 ps
CPU time 8.69 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202672 kb
Host smart-fd63ad1a-6c37-4d63-8f7f-f072f9285088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289719526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.289719526
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.2177170709
Short name T67
Test name
Test status
Simulation time 80888136461 ps
CPU time 3663 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 01:55:21 PM PST 24
Peak memory 376648 kb
Host smart-b128826e-9b8e-49b2-a3c0-870c0b8e09f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177170709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.2177170709
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4124154511
Short name T476
Test name
Test status
Simulation time 212136156 ps
CPU time 1996.01 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 01:27:19 PM PST 24
Peak memory 450408 kb
Host smart-ac9d277b-1d9d-4cd4-8951-5bfb50d81236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4124154511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4124154511
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2492411308
Short name T360
Test name
Test status
Simulation time 2777744802 ps
CPU time 260.86 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:59:03 PM PST 24
Peak memory 202876 kb
Host smart-fdf29af2-e2be-4cbb-a879-99937276d83f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492411308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2492411308
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.287943045
Short name T679
Test name
Test status
Simulation time 275669652 ps
CPU time 73.53 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 335724 kb
Host smart-72efa32c-80a6-4e9a-9745-aa19b1f1ac0f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287943045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.287943045
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1730501773
Short name T515
Test name
Test status
Simulation time 2904690872 ps
CPU time 600.73 seconds
Started Jan 03 12:52:44 PM PST 24
Finished Jan 03 01:04:19 PM PST 24
Peak memory 375828 kb
Host smart-b9d25bba-c3f0-41fe-9abd-6461fae9bc2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730501773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1730501773
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.3224979154
Short name T743
Test name
Test status
Simulation time 21079764 ps
CPU time 0.61 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 202644 kb
Host smart-c791d744-6c92-4f88-8989-44125ffab7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224979154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.3224979154
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.403002698
Short name T689
Test name
Test status
Simulation time 5270158518 ps
CPU time 22.46 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 202960 kb
Host smart-b7e1c57c-cc22-47df-8ee9-1a3417269ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403002698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
403002698
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.2222993994
Short name T368
Test name
Test status
Simulation time 3348945282 ps
CPU time 982.52 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 01:10:24 PM PST 24
Peak memory 374688 kb
Host smart-7397f18f-76b8-4c6a-acde-44c698a3313d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222993994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.2222993994
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1017867662
Short name T837
Test name
Test status
Simulation time 169731698 ps
CPU time 20.09 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 280352 kb
Host smart-64a41228-7503-4362-86a0-7f63b1c73fb7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017867662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1017867662
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1539864742
Short name T83
Test name
Test status
Simulation time 66025097 ps
CPU time 4.71 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 212332 kb
Host smart-714da0ef-f2dd-465b-b7db-ffe37bc7a678
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539864742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.1539864742
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1735138548
Short name T278
Test name
Test status
Simulation time 1263002357 ps
CPU time 11.71 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 202840 kb
Host smart-a66c7d10-f927-46a4-a58f-878c1b778580
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735138548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1735138548
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2688961322
Short name T861
Test name
Test status
Simulation time 42711279 ps
CPU time 1.03 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 203112 kb
Host smart-e8812935-d0f4-4d68-a921-2444a9f5e1b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688961322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2688961322
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.302135179
Short name T620
Test name
Test status
Simulation time 61891868353 ps
CPU time 408.87 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 01:01:04 PM PST 24
Peak memory 350724 kb
Host smart-8f2f2603-14ba-455f-b9b9-5c31bfb8ea8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302135179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.302135179
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.1643367817
Short name T796
Test name
Test status
Simulation time 73482271 ps
CPU time 10.25 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:19 PM PST 24
Peak memory 248892 kb
Host smart-10c13834-595f-4187-bc5e-58b6eaf9815b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643367817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1643367817
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.4090147017
Short name T512
Test name
Test status
Simulation time 92795287501 ps
CPU time 4118.36 seconds
Started Jan 03 12:53:05 PM PST 24
Finished Jan 03 02:02:38 PM PST 24
Peak memory 375692 kb
Host smart-9aa6208e-0ea3-47c6-b074-2ff59dceaa09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090147017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.4090147017
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1812688137
Short name T798
Test name
Test status
Simulation time 907704522 ps
CPU time 3793.43 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 01:57:23 PM PST 24
Peak memory 444216 kb
Host smart-f30c6209-0749-4bd9-b5b3-5afa5512d0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1812688137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1812688137
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1983944930
Short name T416
Test name
Test status
Simulation time 3958905196 ps
CPU time 362.41 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 01:00:05 PM PST 24
Peak memory 202868 kb
Host smart-900519c3-b068-4964-96c8-59a116a270a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983944930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.1983944930
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1894310328
Short name T244
Test name
Test status
Simulation time 448036227 ps
CPU time 4.72 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 218820 kb
Host smart-6c59768e-192f-46ac-91b6-766b574c1fb8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894310328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1894310328
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1996518385
Short name T602
Test name
Test status
Simulation time 3157521527 ps
CPU time 615.04 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 352744 kb
Host smart-c17a0429-7ba7-4d33-a913-67e59fbeed96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996518385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.1996518385
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1937719336
Short name T916
Test name
Test status
Simulation time 34673971 ps
CPU time 0.61 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 12:54:01 PM PST 24
Peak memory 201836 kb
Host smart-269a8634-2531-484d-a538-2e46badfc0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937719336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1937719336
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.477149300
Short name T387
Test name
Test status
Simulation time 4368357375 ps
CPU time 65.77 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 202808 kb
Host smart-28f8e4aa-3df7-4924-aa7f-9f97609a2615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477149300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
477149300
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.27666920
Short name T413
Test name
Test status
Simulation time 695141806 ps
CPU time 7.16 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 213456 kb
Host smart-0dd67b09-331a-4bcb-a8f0-9663bfa89ab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esca
lation.27666920
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2822301258
Short name T375
Test name
Test status
Simulation time 938971485 ps
CPU time 82.46 seconds
Started Jan 03 12:53:19 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 354196 kb
Host smart-e2d91e5f-4add-4d53-9081-a5786186e309
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822301258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2822301258
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2110533865
Short name T802
Test name
Test status
Simulation time 973906834 ps
CPU time 5.16 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:39 PM PST 24
Peak memory 211044 kb
Host smart-872a97a2-a825-46b5-910d-4a6aa74c2f86
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110533865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.2110533865
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.294138589
Short name T486
Test name
Test status
Simulation time 1035904701 ps
CPU time 5.88 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 202936 kb
Host smart-3a67bcd8-aac3-4917-b272-fcfc2a0a370b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294138589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl
_mem_walk.294138589
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.3617828506
Short name T829
Test name
Test status
Simulation time 3260811932 ps
CPU time 31.55 seconds
Started Jan 03 12:53:07 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 202836 kb
Host smart-0d612cf4-650a-4da3-a4bb-6457e562a33a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617828506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.3617828506
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.4210129866
Short name T879
Test name
Test status
Simulation time 60432318 ps
CPU time 2.96 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 202952 kb
Host smart-c212f3fc-ff5d-47c9-8ffe-ce216d2caf24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210129866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.4210129866
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1537825891
Short name T655
Test name
Test status
Simulation time 32522504 ps
CPU time 1.15 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:10 PM PST 24
Peak memory 203020 kb
Host smart-84bf33d3-66dd-40c1-a492-989fe01957a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537825891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1537825891
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.595668310
Short name T899
Test name
Test status
Simulation time 10849276902 ps
CPU time 814.6 seconds
Started Jan 03 12:53:28 PM PST 24
Finished Jan 03 01:07:56 PM PST 24
Peak memory 364532 kb
Host smart-1a9f6698-0ca5-4340-90a0-2f2c3b5b761d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595668310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.595668310
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3489700227
Short name T481
Test name
Test status
Simulation time 1237818106 ps
CPU time 114.92 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:57:10 PM PST 24
Peak memory 360072 kb
Host smart-3a320f64-48e7-454b-a7b1-2375625057e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489700227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3489700227
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.2382231811
Short name T813
Test name
Test status
Simulation time 136582545100 ps
CPU time 2302.98 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 01:33:29 PM PST 24
Peak memory 383932 kb
Host smart-fbc16961-a4fb-4245-bb87-20b2b26527a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382231811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.2382231811
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3898783751
Short name T221
Test name
Test status
Simulation time 2060508761 ps
CPU time 6057.58 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 02:35:25 PM PST 24
Peak memory 451772 kb
Host smart-ab092ea9-bf6f-43af-b11f-cbf42faf4f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3898783751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3898783751
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2533738314
Short name T289
Test name
Test status
Simulation time 2749021252 ps
CPU time 256.3 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:58:48 PM PST 24
Peak memory 202932 kb
Host smart-8575abbe-f4a2-456a-9f58-15ef8f821089
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533738314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2533738314
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1706877637
Short name T589
Test name
Test status
Simulation time 274177354 ps
CPU time 78.51 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 354164 kb
Host smart-3a41069c-f619-4f51-82df-29b74deded09
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706877637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1706877637
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2667866113
Short name T529
Test name
Test status
Simulation time 3409395596 ps
CPU time 577.41 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 346076 kb
Host smart-d5619c0e-3e58-49fc-9059-b75ed776ff5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667866113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2667866113
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1056053808
Short name T389
Test name
Test status
Simulation time 14787248 ps
CPU time 0.63 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 202656 kb
Host smart-420f7fea-ce64-4d35-8808-21f0bd1aaf38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056053808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1056053808
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.202773112
Short name T546
Test name
Test status
Simulation time 4760989907 ps
CPU time 71.75 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 202892 kb
Host smart-4f6d7789-3bd0-4414-9fb1-70426066ab06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202773112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.
202773112
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.2337930010
Short name T532
Test name
Test status
Simulation time 17107733932 ps
CPU time 827.9 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 01:08:33 PM PST 24
Peak memory 360412 kb
Host smart-17f66201-9abf-4a6d-a115-31dc304ebd8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337930010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.2337930010
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1383156369
Short name T865
Test name
Test status
Simulation time 2381967839 ps
CPU time 7.83 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 202856 kb
Host smart-bb8d0172-b1fb-4615-bbb9-feeac136b921
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383156369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1383156369
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3476461548
Short name T914
Test name
Test status
Simulation time 687775001 ps
CPU time 6.2 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 235096 kb
Host smart-d60ef7fb-082e-48a7-ab81-cbeab3d41134
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476461548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3476461548
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.35342632
Short name T559
Test name
Test status
Simulation time 646675560 ps
CPU time 4.89 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 211116 kb
Host smart-eeb41a75-47d1-43fe-ad70-cbd95686a2e4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35342632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_mem_partial_access.35342632
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.4243204205
Short name T458
Test name
Test status
Simulation time 1322890796 ps
CPU time 5.47 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 12:54:04 PM PST 24
Peak memory 202904 kb
Host smart-60083dc9-492f-4348-8546-9f90687c1c93
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243204205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.4243204205
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2353073632
Short name T640
Test name
Test status
Simulation time 30693127409 ps
CPU time 564.81 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 01:04:07 PM PST 24
Peak memory 375208 kb
Host smart-7d8a168b-0a0b-4e3e-9d02-05b8fced8e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353073632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2353073632
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.3268148214
Short name T948
Test name
Test status
Simulation time 619346992 ps
CPU time 11.8 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 202896 kb
Host smart-0cec65c9-3fb9-4ce5-99bd-654c697b0747
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268148214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.3268148214
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3984282183
Short name T777
Test name
Test status
Simulation time 15310123808 ps
CPU time 314.03 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:59:59 PM PST 24
Peak memory 202968 kb
Host smart-e574b453-1367-40e0-8054-0e497febaaa5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984282183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3984282183
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3223119965
Short name T370
Test name
Test status
Simulation time 90410677 ps
CPU time 0.86 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 202864 kb
Host smart-a4fa7622-413e-4980-8321-c93c254a48a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223119965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3223119965
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2810991674
Short name T629
Test name
Test status
Simulation time 11449248130 ps
CPU time 1068.46 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 01:12:07 PM PST 24
Peak memory 372700 kb
Host smart-6a553270-466d-47b3-96a0-ab02ab54bb1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810991674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2810991674
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.3544867167
Short name T300
Test name
Test status
Simulation time 115511696 ps
CPU time 16.51 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 275816 kb
Host smart-ef5df0ce-659c-40e1-8b4c-757b7d73427b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544867167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3544867167
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.257144423
Short name T580
Test name
Test status
Simulation time 51307491196 ps
CPU time 2255.3 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 01:31:47 PM PST 24
Peak memory 368676 kb
Host smart-1773dd59-14b2-488b-b334-9773def4945d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257144423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_stress_all.257144423
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3272967324
Short name T27
Test name
Test status
Simulation time 874549034 ps
CPU time 4017.5 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 02:00:58 PM PST 24
Peak memory 432428 kb
Host smart-82b233f6-d9f9-4ab5-b418-3aef3b0c2f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3272967324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3272967324
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2370844715
Short name T66
Test name
Test status
Simulation time 6076109750 ps
CPU time 138.77 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 202832 kb
Host smart-2f930f8d-5a38-4bd1-a84c-70a0746c365c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370844715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2370844715
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1050279551
Short name T558
Test name
Test status
Simulation time 595289422 ps
CPU time 125.82 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 366384 kb
Host smart-e7c2f2da-107c-4594-854a-fb06eae15f1b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050279551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1050279551
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4128275221
Short name T448
Test name
Test status
Simulation time 12100815405 ps
CPU time 1133.18 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 01:13:23 PM PST 24
Peak memory 371196 kb
Host smart-8fd4cdb3-8d9a-432e-bc15-4a4cf1052e2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128275221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.4128275221
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.3765680793
Short name T765
Test name
Test status
Simulation time 22428830 ps
CPU time 0.64 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 201848 kb
Host smart-7adf06c7-fdb8-4d95-bf74-5a075ebb27b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765680793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.3765680793
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2369692854
Short name T598
Test name
Test status
Simulation time 2197005238 ps
CPU time 21.84 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 202892 kb
Host smart-556456dc-1d8b-4760-8d96-88e36dfa052f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369692854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2369692854
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.3863993553
Short name T918
Test name
Test status
Simulation time 10545502561 ps
CPU time 582.77 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 342072 kb
Host smart-41868329-2a2c-427c-8a12-816dd107efaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863993553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3863993553
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3912828548
Short name T885
Test name
Test status
Simulation time 1026837751 ps
CPU time 11.93 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 213476 kb
Host smart-b3aabbd2-d7cc-460a-875a-b7ed578870b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912828548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3912828548
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.2228412332
Short name T691
Test name
Test status
Simulation time 689791747 ps
CPU time 8.94 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 243236 kb
Host smart-77f47e8a-2190-4f01-9c13-969869ffce4a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228412332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.2228412332
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.39661381
Short name T258
Test name
Test status
Simulation time 175401206 ps
CPU time 2.99 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 212092 kb
Host smart-de0c2121-23e4-4317-a48a-88c84180762e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_mem_partial_access.39661381
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.4081217201
Short name T599
Test name
Test status
Simulation time 139237733 ps
CPU time 8.22 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 202824 kb
Host smart-e7da1682-56cf-4c57-bc2b-125382fdfdb3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081217201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.4081217201
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.1447133767
Short name T564
Test name
Test status
Simulation time 10376472581 ps
CPU time 562.44 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 375468 kb
Host smart-77853b5d-4598-4efe-ba5e-5aecf76963c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447133767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.1447133767
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.3156145374
Short name T816
Test name
Test status
Simulation time 2513368299 ps
CPU time 9.09 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:54:18 PM PST 24
Peak memory 202952 kb
Host smart-941a0409-6455-4e3f-baae-90703740701b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156145374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.3156145374
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2379764897
Short name T560
Test name
Test status
Simulation time 12668332820 ps
CPU time 436.69 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 01:02:13 PM PST 24
Peak memory 202880 kb
Host smart-ae7d1bc9-674e-41bd-b9c4-d509c1146532
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379764897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.2379764897
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.90321606
Short name T126
Test name
Test status
Simulation time 27321194 ps
CPU time 0.89 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:36 PM PST 24
Peak memory 202852 kb
Host smart-b508f567-2d1e-44bf-97f5-d4663d763544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90321606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.90321606
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.959260421
Short name T528
Test name
Test status
Simulation time 839955089 ps
CPU time 422.19 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 01:01:23 PM PST 24
Peak memory 365456 kb
Host smart-d713ce7f-1261-4d59-b73e-c0034cd29945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959260421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.959260421
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3144209519
Short name T962
Test name
Test status
Simulation time 1195446076 ps
CPU time 13.36 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:14 PM PST 24
Peak memory 202780 kb
Host smart-4ed72983-5e36-41ae-9be9-9d6e01ff30f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144209519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3144209519
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1467215336
Short name T729
Test name
Test status
Simulation time 8693514871 ps
CPU time 149.47 seconds
Started Jan 03 12:52:50 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 284648 kb
Host smart-e6c26570-374c-4ec7-bfac-1bbfd9d09174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467215336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1467215336
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3921734220
Short name T923
Test name
Test status
Simulation time 7953345553 ps
CPU time 5208.61 seconds
Started Jan 03 12:53:19 PM PST 24
Finished Jan 03 02:20:52 PM PST 24
Peak memory 432040 kb
Host smart-af12a4f5-e3cc-4cae-918d-0ff502ec35e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3921734220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3921734220
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1533785559
Short name T381
Test name
Test status
Simulation time 3005374839 ps
CPU time 286.14 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:59:16 PM PST 24
Peak memory 202964 kb
Host smart-f8cffb95-620d-4ed4-820e-595193095ad3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533785559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1533785559
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1814160997
Short name T772
Test name
Test status
Simulation time 113527402 ps
CPU time 46.74 seconds
Started Jan 03 12:53:02 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 314884 kb
Host smart-18270ce3-4f2a-42ab-9619-f48da845f9f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814160997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1814160997
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3625166733
Short name T576
Test name
Test status
Simulation time 69122034 ps
CPU time 11.77 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 248784 kb
Host smart-9c28647b-9940-4a2b-9594-02ca9f66f43a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625166733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.3625166733
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.341383155
Short name T842
Test name
Test status
Simulation time 13794438 ps
CPU time 0.63 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:37 PM PST 24
Peak memory 201988 kb
Host smart-f151f408-5dcf-4e78-b18f-28b363073306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341383155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.341383155
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1339624670
Short name T124
Test name
Test status
Simulation time 5719521656 ps
CPU time 36.38 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 202976 kb
Host smart-986abc9b-b22a-4609-a1d2-e586e09d733c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339624670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1339624670
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.1648348742
Short name T680
Test name
Test status
Simulation time 26359954125 ps
CPU time 650.45 seconds
Started Jan 03 12:53:20 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 374428 kb
Host smart-eea94feb-b4ab-4435-b3f3-0f0193fb4787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648348742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.1648348742
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.3033345462
Short name T226
Test name
Test status
Simulation time 1034572489 ps
CPU time 4.22 seconds
Started Jan 03 12:53:21 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 202932 kb
Host smart-591d98ea-c320-40d9-9c16-ad886d2e56b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033345462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.3033345462
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2776487337
Short name T789
Test name
Test status
Simulation time 457402087 ps
CPU time 60.42 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:56:16 PM PST 24
Peak memory 330208 kb
Host smart-59d512fd-0d8e-41f3-a4bd-b01039e318fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776487337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2776487337
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3209469687
Short name T268
Test name
Test status
Simulation time 172999123 ps
CPU time 2.9 seconds
Started Jan 03 12:54:07 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 211056 kb
Host smart-77e3a699-bed8-469b-97e8-338611c1575c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209469687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3209469687
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.58040911
Short name T491
Test name
Test status
Simulation time 285435036 ps
CPU time 4.3 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:44 PM PST 24
Peak memory 202936 kb
Host smart-55501d1a-5619-44e1-94bf-58fb862cd12e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58040911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_
mem_walk.58040911
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.4244083119
Short name T39
Test name
Test status
Simulation time 84171223969 ps
CPU time 1257.87 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 01:15:24 PM PST 24
Peak memory 369032 kb
Host smart-cd06e2af-b503-4b4d-9b74-43c638d8dcdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244083119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.4244083119
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.751517082
Short name T820
Test name
Test status
Simulation time 235852586 ps
CPU time 81.98 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 370688 kb
Host smart-5e43d2fa-a4c7-4b8e-8116-630d5decbfdb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751517082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.751517082
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2995059652
Short name T487
Test name
Test status
Simulation time 44621327665 ps
CPU time 224.57 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:58:03 PM PST 24
Peak memory 202944 kb
Host smart-fa9e4482-daf0-4029-9d03-da8a2eb0287e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995059652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2995059652
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1392972464
Short name T501
Test name
Test status
Simulation time 62692815 ps
CPU time 1.19 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 202988 kb
Host smart-b822bb3b-bb0b-42f3-b225-3e309c9b1a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392972464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1392972464
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2866864904
Short name T42
Test name
Test status
Simulation time 7357726541 ps
CPU time 609.7 seconds
Started Jan 03 12:53:22 PM PST 24
Finished Jan 03 01:04:18 PM PST 24
Peak memory 369536 kb
Host smart-d4132a0d-084b-432f-acea-fbec80bc1739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866864904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2866864904
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.1389365734
Short name T346
Test name
Test status
Simulation time 244182647 ps
CPU time 46.97 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:55:20 PM PST 24
Peak memory 331288 kb
Host smart-dd0f5345-d9d5-4625-a11c-fc582cd7b5e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389365734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1389365734
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.830053247
Short name T742
Test name
Test status
Simulation time 180242541408 ps
CPU time 4134.67 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 02:03:40 PM PST 24
Peak memory 377496 kb
Host smart-65ace3d6-f637-4292-b071-d16eae4e54fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830053247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_stress_all.830053247
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4066551524
Short name T230
Test name
Test status
Simulation time 2475060300 ps
CPU time 130.93 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 377204 kb
Host smart-5624cafc-7399-4916-a19e-1c40da9c69da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4066551524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.4066551524
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2468712640
Short name T846
Test name
Test status
Simulation time 15658655728 ps
CPU time 361.36 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 01:00:00 PM PST 24
Peak memory 202892 kb
Host smart-9305ca92-13dd-4999-ab25-a22ad4cd3cfc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468712640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.2468712640
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2618942212
Short name T273
Test name
Test status
Simulation time 310582787 ps
CPU time 67.27 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 369252 kb
Host smart-f6e5b5f9-013d-4c9f-a6b2-446756d36b10
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618942212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2618942212
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1278963744
Short name T920
Test name
Test status
Simulation time 3960543845 ps
CPU time 1134.93 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 01:12:56 PM PST 24
Peak memory 374756 kb
Host smart-7077862a-5489-4df6-905c-1a1e84d9b4bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278963744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.1278963744
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.3048899223
Short name T571
Test name
Test status
Simulation time 40436801 ps
CPU time 0.62 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:03 PM PST 24
Peak memory 202816 kb
Host smart-50e9f470-8e9e-400f-acc7-033babe8162e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048899223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.3048899223
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3476574101
Short name T972
Test name
Test status
Simulation time 24600722500 ps
CPU time 56.33 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 202864 kb
Host smart-ab80fd05-935b-48c9-9c60-93b8ea31251f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476574101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3476574101
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.1006414439
Short name T444
Test name
Test status
Simulation time 22204710357 ps
CPU time 811.72 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 01:07:46 PM PST 24
Peak memory 374652 kb
Host smart-c59d13f4-18fe-4f57-8059-91a9c5f9e744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006414439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.1006414439
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.977759090
Short name T434
Test name
Test status
Simulation time 525727209 ps
CPU time 6.66 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:06 PM PST 24
Peak memory 211112 kb
Host smart-8b3c56f7-a426-4c4e-822b-3bca96069ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977759090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.977759090
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.1860299109
Short name T54
Test name
Test status
Simulation time 335100232 ps
CPU time 14.44 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 12:54:14 PM PST 24
Peak memory 261336 kb
Host smart-d988352a-7d3e-4e79-aa99-b5854b52907a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860299109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.1860299109
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2055960119
Short name T749
Test name
Test status
Simulation time 65590743 ps
CPU time 2.82 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:03 PM PST 24
Peak memory 212052 kb
Host smart-0056e4f3-2ac3-4282-ac51-81b47a32cb12
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055960119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2055960119
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.3778084890
Short name T687
Test name
Test status
Simulation time 239168395 ps
CPU time 4.97 seconds
Started Jan 03 12:52:42 PM PST 24
Finished Jan 03 12:53:52 PM PST 24
Peak memory 202884 kb
Host smart-b1441d9d-fbb0-472e-b55e-54453b78a549
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778084890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.3778084890
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1368880910
Short name T726
Test name
Test status
Simulation time 26615033963 ps
CPU time 421.92 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 352824 kb
Host smart-11521a0d-c078-4ad5-a7aa-2aefa5df606e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368880910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1368880910
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.1666954180
Short name T34
Test name
Test status
Simulation time 617449747 ps
CPU time 10.49 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 247768 kb
Host smart-9f334137-57af-4123-a6ad-f379e8c9edbe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666954180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.1666954180
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1004507584
Short name T809
Test name
Test status
Simulation time 11270724252 ps
CPU time 153.55 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:56:52 PM PST 24
Peak memory 202976 kb
Host smart-615b79a7-a686-4342-9e11-fb025472b009
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004507584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.1004507584
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1930715747
Short name T282
Test name
Test status
Simulation time 78161492 ps
CPU time 1.03 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 203036 kb
Host smart-4d434e69-b3cf-4ed0-a725-c32affa12e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930715747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1930715747
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.2102533481
Short name T630
Test name
Test status
Simulation time 28843830723 ps
CPU time 1520.31 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 01:19:35 PM PST 24
Peak memory 375820 kb
Host smart-050bbe77-2896-4fe3-9c7c-9099e06de040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102533481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2102533481
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.2645819105
Short name T785
Test name
Test status
Simulation time 161475739 ps
CPU time 22.13 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 292784 kb
Host smart-005ae726-36b0-4cce-8235-202bea054766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645819105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2645819105
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.948760528
Short name T732
Test name
Test status
Simulation time 4695512810 ps
CPU time 728.17 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 01:06:09 PM PST 24
Peak memory 372592 kb
Host smart-b2955218-0c0a-4c55-9c34-474cf5648b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948760528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.948760528
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.353413743
Short name T276
Test name
Test status
Simulation time 2258895976 ps
CPU time 2942.26 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 01:43:42 PM PST 24
Peak memory 430168 kb
Host smart-e037b227-c01d-44aa-8fd3-b4051162ca08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=353413743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.353413743
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3430569496
Short name T281
Test name
Test status
Simulation time 3627966119 ps
CPU time 329.89 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 12:59:44 PM PST 24
Peak memory 202900 kb
Host smart-8c8a77b7-5be2-4156-b8b9-cc23d6f7cc61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430569496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.3430569496
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3693954339
Short name T698
Test name
Test status
Simulation time 1861557962 ps
CPU time 64.44 seconds
Started Jan 03 12:52:44 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 349944 kb
Host smart-95d563a2-baa2-4cf6-82d8-0b1438865438
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693954339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3693954339
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.729806734
Short name T365
Test name
Test status
Simulation time 1798667522 ps
CPU time 362.83 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 01:00:21 PM PST 24
Peak memory 365432 kb
Host smart-ad8538aa-07fb-4393-80c1-fe023a107f72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729806734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.sram_ctrl_access_during_key_req.729806734
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1644774042
Short name T364
Test name
Test status
Simulation time 14794197 ps
CPU time 0.61 seconds
Started Jan 03 12:53:18 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 202440 kb
Host smart-5b7cdf67-7850-4bfc-93b5-86ad22dc0d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644774042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1644774042
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.4056885293
Short name T533
Test name
Test status
Simulation time 5257972556 ps
CPU time 77.09 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:56:06 PM PST 24
Peak memory 203016 kb
Host smart-6fb24f5b-4319-4eba-b626-e1d12c8711e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056885293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.4056885293
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.3103209037
Short name T128
Test name
Test status
Simulation time 118397995 ps
CPU time 38.18 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 310868 kb
Host smart-70f3e1f9-5e8a-4325-90d0-705af2fdc0ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103209037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.3103209037
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2058168376
Short name T672
Test name
Test status
Simulation time 196482035 ps
CPU time 2.97 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:40 PM PST 24
Peak memory 211084 kb
Host smart-db41065a-8dce-4070-abea-d9109c656a6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058168376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2058168376
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3734278645
Short name T843
Test name
Test status
Simulation time 529036530 ps
CPU time 56.31 seconds
Started Jan 03 12:52:45 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 324480 kb
Host smart-ba4cd82c-259f-4996-aa93-73e477586334
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734278645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3734278645
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2424161074
Short name T503
Test name
Test status
Simulation time 135535793 ps
CPU time 2.86 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:02 PM PST 24
Peak memory 211124 kb
Host smart-57d6fc6e-f192-4d59-89a1-caa9cd6ad274
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424161074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.2424161074
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.3297118352
Short name T120
Test name
Test status
Simulation time 287308786 ps
CPU time 4.47 seconds
Started Jan 03 12:53:20 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 202980 kb
Host smart-e49e1937-bd4b-47f3-b287-86d3a30bc974
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297118352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.3297118352
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.2052493040
Short name T754
Test name
Test status
Simulation time 36704365931 ps
CPU time 377.11 seconds
Started Jan 03 12:52:49 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 362116 kb
Host smart-6116dd6b-dcc8-413e-8d12-296d00d7d5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052493040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.2052493040
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.4279851172
Short name T595
Test name
Test status
Simulation time 803483366 ps
CPU time 15.51 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 202748 kb
Host smart-a984329e-f894-4834-bef1-f69fa0897cba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279851172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.4279851172
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4158703671
Short name T294
Test name
Test status
Simulation time 4980438768 ps
CPU time 344.3 seconds
Started Jan 03 12:52:58 PM PST 24
Finished Jan 03 01:00:14 PM PST 24
Peak memory 202944 kb
Host smart-8a51f08e-7351-47fc-a198-af95ca394cd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158703671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.4158703671
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3083281420
Short name T863
Test name
Test status
Simulation time 79711470 ps
CPU time 1.06 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:54:10 PM PST 24
Peak memory 203204 kb
Host smart-bcd9c280-812b-470e-8c9a-c1062cea11cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083281420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3083281420
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.3203757022
Short name T114
Test name
Test status
Simulation time 20545336062 ps
CPU time 966.52 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 01:10:43 PM PST 24
Peak memory 373640 kb
Host smart-ba1b3b81-919a-45c8-93d5-3044b6bfc5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203757022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3203757022
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.623625573
Short name T498
Test name
Test status
Simulation time 82055069 ps
CPU time 4.19 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:54:10 PM PST 24
Peak memory 202824 kb
Host smart-43ad3bce-4646-4071-a4b8-e159fe6a7b57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623625573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.623625573
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3601285344
Short name T800
Test name
Test status
Simulation time 464886213 ps
CPU time 2152.32 seconds
Started Jan 03 12:52:50 PM PST 24
Finished Jan 03 01:30:07 PM PST 24
Peak memory 421468 kb
Host smart-cc315734-edcd-4571-90cf-f1224ff74477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3601285344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3601285344
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1929885946
Short name T513
Test name
Test status
Simulation time 9227932908 ps
CPU time 232.89 seconds
Started Jan 03 12:53:02 PM PST 24
Finished Jan 03 12:57:54 PM PST 24
Peak memory 202980 kb
Host smart-4b7d5128-04ac-4d22-921f-18d09c675867
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929885946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.1929885946
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3108985859
Short name T37
Test name
Test status
Simulation time 141661551 ps
CPU time 60.25 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 350332 kb
Host smart-3bf4fd3e-e497-461b-8884-19b9862bde44
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108985859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3108985859
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1232223455
Short name T745
Test name
Test status
Simulation time 21929871078 ps
CPU time 618.97 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 01:04:20 PM PST 24
Peak memory 375164 kb
Host smart-9c987357-5495-4e69-ad75-b511b5545961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232223455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1232223455
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.178069529
Short name T405
Test name
Test status
Simulation time 96046250 ps
CPU time 0.66 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 201928 kb
Host smart-db0ac88c-360e-4a7e-ac90-d99c2268f9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178069529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.178069529
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.1354406732
Short name T773
Test name
Test status
Simulation time 3231006783 ps
CPU time 63.87 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:56:09 PM PST 24
Peak memory 202900 kb
Host smart-58b30880-af31-4cb2-b2f6-8ebce2d02809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354406732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.1354406732
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.282314414
Short name T403
Test name
Test status
Simulation time 27577374965 ps
CPU time 518.99 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 01:03:35 PM PST 24
Peak memory 366564 kb
Host smart-2ccd3d88-45cd-4a81-a3bc-99ee1ad2fb5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282314414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl
e.282314414
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1810763407
Short name T384
Test name
Test status
Simulation time 4994211395 ps
CPU time 7.96 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 211272 kb
Host smart-4a7cb42d-8e8d-4343-baba-92968d80fd9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810763407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1810763407
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.2231178696
Short name T590
Test name
Test status
Simulation time 257458685 ps
CPU time 95.96 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:56:36 PM PST 24
Peak memory 353960 kb
Host smart-3bbf7225-6303-4be6-a9cb-6dd7b6694170
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231178696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.2231178696
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3351095734
Short name T937
Test name
Test status
Simulation time 63342790 ps
CPU time 4.36 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 211204 kb
Host smart-75da2560-265e-48c8-88b6-b55375d443d5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351095734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3351095734
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.640468762
Short name T378
Test name
Test status
Simulation time 550064627 ps
CPU time 8.32 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 202880 kb
Host smart-99e250b4-4b86-41d0-a260-1c8827ce62a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640468762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl
_mem_walk.640468762
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3919498845
Short name T660
Test name
Test status
Simulation time 33984619913 ps
CPU time 1204.73 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 01:14:11 PM PST 24
Peak memory 375668 kb
Host smart-d0fe15be-0f37-4406-9a5e-02bea9f898fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919498845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3919498845
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.3697278422
Short name T898
Test name
Test status
Simulation time 2114745527 ps
CPU time 18.38 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 203020 kb
Host smart-4061e4c1-eaae-4567-8470-ad640b06228a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697278422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.3697278422
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1645841119
Short name T407
Test name
Test status
Simulation time 112435784837 ps
CPU time 325.14 seconds
Started Jan 03 12:53:11 PM PST 24
Finished Jan 03 12:59:49 PM PST 24
Peak memory 202900 kb
Host smart-982de5c4-8bdd-407b-a305-652a1ee6eb1e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645841119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.1645841119
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.3323833944
Short name T523
Test name
Test status
Simulation time 123554494 ps
CPU time 0.81 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 202924 kb
Host smart-ace0eaf0-ecc7-4c16-a520-dfc2631f5622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323833944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3323833944
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2246752758
Short name T376
Test name
Test status
Simulation time 43084515881 ps
CPU time 376.07 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 01:01:06 PM PST 24
Peak memory 333704 kb
Host smart-7ec549a6-c3e3-4418-b291-4a86a3e4d3b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246752758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2246752758
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1444143562
Short name T631
Test name
Test status
Simulation time 133403980 ps
CPU time 1.9 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 202884 kb
Host smart-03c2ef3d-f00b-477a-842f-458808347c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444143562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1444143562
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.3052061816
Short name T788
Test name
Test status
Simulation time 357491676671 ps
CPU time 2158.82 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 01:30:26 PM PST 24
Peak memory 371812 kb
Host smart-f5114f37-947f-4664-980d-df685caf2c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052061816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.3052061816
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2003686842
Short name T534
Test name
Test status
Simulation time 5652897255 ps
CPU time 4025.23 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 02:01:39 PM PST 24
Peak memory 403180 kb
Host smart-dc76eca6-1eb8-4472-8602-2f65f971203d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2003686842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2003686842
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.680028609
Short name T483
Test name
Test status
Simulation time 3740734725 ps
CPU time 114.65 seconds
Started Jan 03 12:53:04 PM PST 24
Finished Jan 03 12:56:03 PM PST 24
Peak memory 202864 kb
Host smart-9caa3256-45ea-4524-a589-76c7cbfb3578
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680028609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.680028609
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3301058756
Short name T493
Test name
Test status
Simulation time 253216233 ps
CPU time 11.66 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 254908 kb
Host smart-d8d635c5-a9b9-436e-8303-a6895a51d0d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301058756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3301058756
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3250316431
Short name T592
Test name
Test status
Simulation time 2248411980 ps
CPU time 447.03 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:59:14 PM PST 24
Peak memory 374860 kb
Host smart-1185835f-05b5-4b03-b02e-eb4f14d940bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250316431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3250316431
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.2724458621
Short name T647
Test name
Test status
Simulation time 15494808 ps
CPU time 0.64 seconds
Started Jan 03 12:51:51 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 201872 kb
Host smart-bba3be24-8fa1-42b0-8c90-59e14ca24c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724458621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.2724458621
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.3788985559
Short name T36
Test name
Test status
Simulation time 1656375833 ps
CPU time 34.52 seconds
Started Jan 03 12:51:33 PM PST 24
Finished Jan 03 12:52:19 PM PST 24
Peak memory 202752 kb
Host smart-e5eb08bc-c50c-4e9d-8b10-faf2e9c5c0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788985559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
3788985559
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.3185833739
Short name T588
Test name
Test status
Simulation time 7787382679 ps
CPU time 433.79 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:59:00 PM PST 24
Peak memory 350228 kb
Host smart-96d020c5-bdf7-4c6e-be20-96673843b82a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185833739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.3185833739
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3283249062
Short name T938
Test name
Test status
Simulation time 1104164629 ps
CPU time 8.15 seconds
Started Jan 03 12:51:48 PM PST 24
Finished Jan 03 12:52:04 PM PST 24
Peak memory 211032 kb
Host smart-3e2a3979-1928-46c4-a782-46a3b01d5a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283249062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3283249062
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.2319325762
Short name T868
Test name
Test status
Simulation time 473243865 ps
CPU time 77.69 seconds
Started Jan 03 12:51:31 PM PST 24
Finished Jan 03 12:53:01 PM PST 24
Peak memory 340876 kb
Host smart-66bae22a-18d8-4a10-8617-7f22d72886bb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319325762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.2319325762
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.686761514
Short name T805
Test name
Test status
Simulation time 576169916 ps
CPU time 4.96 seconds
Started Jan 03 12:51:39 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 211024 kb
Host smart-c34257c5-39d3-42eb-830b-e523e1322b3d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686761514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.686761514
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1489355001
Short name T470
Test name
Test status
Simulation time 518169403 ps
CPU time 8.2 seconds
Started Jan 03 12:51:30 PM PST 24
Finished Jan 03 12:51:51 PM PST 24
Peak memory 202836 kb
Host smart-0cf7d83c-52bd-4ec9-946d-de323f6e1f69
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489355001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1489355001
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1349517233
Short name T977
Test name
Test status
Simulation time 2350694531 ps
CPU time 401.63 seconds
Started Jan 03 12:51:29 PM PST 24
Finished Jan 03 12:58:23 PM PST 24
Peak memory 370572 kb
Host smart-3f7ee774-63e3-41d6-b5c2-2585524116ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349517233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1349517233
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.1390620413
Short name T727
Test name
Test status
Simulation time 1688372574 ps
CPU time 8.14 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:52:02 PM PST 24
Peak memory 203004 kb
Host smart-6b8a2b8d-4d97-40a4-9429-3a6a0b87b1ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390620413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.1390620413
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3018629268
Short name T581
Test name
Test status
Simulation time 53593328663 ps
CPU time 352.26 seconds
Started Jan 03 12:51:22 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 202892 kb
Host smart-c7ff0cd3-a568-4d78-9816-0044b70f312e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018629268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.3018629268
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.2590626201
Short name T586
Test name
Test status
Simulation time 30064491 ps
CPU time 0.87 seconds
Started Jan 03 12:51:47 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 202868 kb
Host smart-40d42f78-5521-415b-9e2a-cf15f15d3112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590626201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2590626201
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.4214517514
Short name T735
Test name
Test status
Simulation time 1408031567 ps
CPU time 367.15 seconds
Started Jan 03 12:51:31 PM PST 24
Finished Jan 03 12:57:50 PM PST 24
Peak memory 367352 kb
Host smart-1b3b84a1-f468-42eb-979e-127ee5f008dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214517514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.4214517514
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.4033335945
Short name T22
Test name
Test status
Simulation time 998591169 ps
CPU time 3.16 seconds
Started Jan 03 12:51:41 PM PST 24
Finished Jan 03 12:51:55 PM PST 24
Peak memory 224876 kb
Host smart-65bafa7d-b17d-404b-a477-417016986617
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033335945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.4033335945
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.1225378363
Short name T947
Test name
Test status
Simulation time 94282264 ps
CPU time 2.5 seconds
Started Jan 03 12:51:26 PM PST 24
Finished Jan 03 12:51:42 PM PST 24
Peak memory 202780 kb
Host smart-1bb42e6c-e6f1-447a-b003-fbf2ca840460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225378363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1225378363
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.2837406127
Short name T974
Test name
Test status
Simulation time 71047731204 ps
CPU time 2265.89 seconds
Started Jan 03 12:51:50 PM PST 24
Finished Jan 03 01:29:44 PM PST 24
Peak memory 383852 kb
Host smart-35454246-098c-4dd5-8329-560525f729bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837406127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.2837406127
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.884818265
Short name T410
Test name
Test status
Simulation time 1340575190 ps
CPU time 663.09 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 377120 kb
Host smart-84aefa95-5d2f-4ab8-8f32-2af3e602656c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=884818265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.884818265
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.342165110
Short name T606
Test name
Test status
Simulation time 3236637073 ps
CPU time 302.71 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:56:39 PM PST 24
Peak memory 203008 kb
Host smart-454a02b6-2532-4cf7-8f10-a0e6d72267ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342165110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.342165110
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2474979243
Short name T296
Test name
Test status
Simulation time 160919463 ps
CPU time 107.9 seconds
Started Jan 03 12:51:28 PM PST 24
Finished Jan 03 12:53:29 PM PST 24
Peak memory 373476 kb
Host smart-4ddaf6da-634c-451a-ba9b-a9f558eb2fe7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474979243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2474979243
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2915627763
Short name T967
Test name
Test status
Simulation time 3230319631 ps
CPU time 567.87 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 01:03:31 PM PST 24
Peak memory 375844 kb
Host smart-bd51abf1-0016-4ba1-bea1-558b9adbc752
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915627763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.2915627763
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.1072519983
Short name T321
Test name
Test status
Simulation time 1372173011 ps
CPU time 27.94 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 202748 kb
Host smart-fc0cf898-3fd0-4a17-a79b-fd12d2b26f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072519983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1072519983
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.1927849505
Short name T457
Test name
Test status
Simulation time 1923581783 ps
CPU time 27.33 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:56:09 PM PST 24
Peak memory 278504 kb
Host smart-c0ef872f-024a-497c-b3ed-d21d9af00976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927849505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.1927849505
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.1273198676
Short name T98
Test name
Test status
Simulation time 2867336160 ps
CPU time 8.09 seconds
Started Jan 03 12:53:29 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 211064 kb
Host smart-e353f15c-9dcf-481f-98dd-c4986c0785ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273198676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.1273198676
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.766915155
Short name T129
Test name
Test status
Simulation time 610492208 ps
CPU time 76.46 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 367016 kb
Host smart-f865aa6e-1e81-4ce7-9675-5c0e5a149570
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766915155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.766915155
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.22578614
Short name T327
Test name
Test status
Simulation time 596632344 ps
CPU time 5.26 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 216124 kb
Host smart-694f11e4-9afa-496f-af8a-ebbee9c8d140
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_mem_partial_access.22578614
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2802511638
Short name T121
Test name
Test status
Simulation time 479307547 ps
CPU time 8.78 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 202860 kb
Host smart-e8138831-ee40-4e47-a66d-586b99ea2e14
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802511638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2802511638
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3137867831
Short name T267
Test name
Test status
Simulation time 4640317450 ps
CPU time 378.99 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 01:00:22 PM PST 24
Peak memory 371524 kb
Host smart-5bff6001-c0f2-4154-904c-411c990857ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137867831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3137867831
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.4002138321
Short name T324
Test name
Test status
Simulation time 4375127633 ps
CPU time 11.5 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 202944 kb
Host smart-a6c3d6e8-b05e-42dc-a084-214b3a006c89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002138321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.4002138321
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1045696668
Short name T393
Test name
Test status
Simulation time 2189372439 ps
CPU time 145.97 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:56:56 PM PST 24
Peak memory 202808 kb
Host smart-14359a2c-076b-4836-b9bb-10d654c84e50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045696668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1045696668
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1512267287
Short name T350
Test name
Test status
Simulation time 29812735 ps
CPU time 0.84 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 202824 kb
Host smart-a08e98b7-d760-4ea5-8fa0-b6ef4afd01c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512267287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1512267287
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3457676473
Short name T452
Test name
Test status
Simulation time 13787634113 ps
CPU time 813.24 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 01:07:42 PM PST 24
Peak memory 368216 kb
Host smart-1b28e169-51ee-465e-8d3f-a9ab7c77e2fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457676473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3457676473
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.529086852
Short name T958
Test name
Test status
Simulation time 179849223 ps
CPU time 1.44 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 202896 kb
Host smart-924221f2-b9ac-41ec-857b-9ad3b6b3c07f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529086852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.529086852
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.485215213
Short name T822
Test name
Test status
Simulation time 845655760 ps
CPU time 1215.25 seconds
Started Jan 03 12:52:47 PM PST 24
Finished Jan 03 01:14:24 PM PST 24
Peak memory 465880 kb
Host smart-a6ed8705-df7f-488d-acab-a6d6f81967a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=485215213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.485215213
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.4419465
Short name T303
Test name
Test status
Simulation time 10186098744 ps
CPU time 217.73 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:57:37 PM PST 24
Peak memory 202836 kb
Host smart-5a5c2c98-af4d-4c34-bbab-3438da6d5810
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4419465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_stress_pipeline.4419465
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3032810343
Short name T332
Test name
Test status
Simulation time 262395335 ps
CPU time 8.47 seconds
Started Jan 03 12:52:51 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 241316 kb
Host smart-1e8e1db0-eec9-473f-acf5-582ad14c5889
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032810343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3032810343
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1665053199
Short name T420
Test name
Test status
Simulation time 3135297634 ps
CPU time 155.15 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 334416 kb
Host smart-fb3e250d-03d3-4590-aea4-ae1f4d4934ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665053199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.1665053199
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.762888156
Short name T818
Test name
Test status
Simulation time 28463105 ps
CPU time 0.64 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 201936 kb
Host smart-824e2373-7bf3-4e7e-a9e8-73428137d9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762888156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.762888156
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2367859192
Short name T897
Test name
Test status
Simulation time 12085152918 ps
CPU time 47.27 seconds
Started Jan 03 12:52:54 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 202896 kb
Host smart-0729cbc7-31a3-44b2-9018-7dd51c2cba7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367859192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2367859192
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.4235062930
Short name T414
Test name
Test status
Simulation time 32623867221 ps
CPU time 971.81 seconds
Started Jan 03 12:53:19 PM PST 24
Finished Jan 03 01:10:38 PM PST 24
Peak memory 374780 kb
Host smart-15d9fdec-b7d9-4318-9b2d-6fbab242e1f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235062930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.4235062930
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.3557387011
Short name T6
Test name
Test status
Simulation time 4275820687 ps
CPU time 9.25 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 203012 kb
Host smart-c611e02e-e19d-4310-baa4-6b5dac6548da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557387011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.3557387011
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2693561971
Short name T284
Test name
Test status
Simulation time 130542201 ps
CPU time 57.47 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:55:24 PM PST 24
Peak memory 352612 kb
Host smart-6c4f2658-6c10-4b12-8782-03c8eb257828
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693561971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2693561971
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3884480772
Short name T331
Test name
Test status
Simulation time 54807210 ps
CPU time 2.74 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 215988 kb
Host smart-d86803b1-c2ed-46b6-9a5f-c8a237a76f08
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884480772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.3884480772
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3583396593
Short name T530
Test name
Test status
Simulation time 457159081 ps
CPU time 5.2 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:04 PM PST 24
Peak memory 202984 kb
Host smart-9ff12f27-869a-4b5e-8ee8-9edf11ce9d9c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583396593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3583396593
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.4219184835
Short name T356
Test name
Test status
Simulation time 3012400011 ps
CPU time 385.95 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 01:00:29 PM PST 24
Peak memory 353564 kb
Host smart-4ae8b6b9-be3a-4b43-bcff-7ec4ba9bce5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219184835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.4219184835
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.708362788
Short name T852
Test name
Test status
Simulation time 239381705 ps
CPU time 1.53 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 202968 kb
Host smart-08d9f8ca-19f8-44bb-b2bc-19dcf0635c67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708362788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s
ram_ctrl_partial_access.708362788
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.710188679
Short name T719
Test name
Test status
Simulation time 7711043333 ps
CPU time 182.67 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:58:02 PM PST 24
Peak memory 202812 kb
Host smart-727c4734-e4ca-4e77-a1d6-04b212bfa334
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710188679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.710188679
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2921562537
Short name T987
Test name
Test status
Simulation time 93306717 ps
CPU time 1.01 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 203004 kb
Host smart-f0b26719-a6b1-4922-90d6-616f05ba79e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921562537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2921562537
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.2230435198
Short name T604
Test name
Test status
Simulation time 93659800275 ps
CPU time 1339.87 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 01:16:50 PM PST 24
Peak memory 370536 kb
Host smart-57399b7e-f71f-4b61-9a72-a170d5af8c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230435198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2230435198
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2989473139
Short name T40
Test name
Test status
Simulation time 599900987 ps
CPU time 80.85 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 361752 kb
Host smart-84fe94a0-ee60-469c-bb57-c2e657c992d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989473139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2989473139
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.273214362
Short name T573
Test name
Test status
Simulation time 252925345350 ps
CPU time 4276.21 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 02:05:58 PM PST 24
Peak memory 382952 kb
Host smart-d59931c5-8c97-4469-998d-4b83e4813f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273214362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_stress_all.273214362
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3956743067
Short name T700
Test name
Test status
Simulation time 350825696 ps
CPU time 1568.69 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 01:20:49 PM PST 24
Peak memory 433172 kb
Host smart-3e8f18fa-f809-4968-94e0-1bcac13d90ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3956743067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3956743067
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2193811271
Short name T38
Test name
Test status
Simulation time 2602718392 ps
CPU time 137.03 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 203028 kb
Host smart-34962d83-6ca3-4efb-bb1a-ba73b88280af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193811271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.2193811271
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2014020017
Short name T896
Test name
Test status
Simulation time 137722160 ps
CPU time 71.89 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 331660 kb
Host smart-2cc5ac34-5dd8-4a11-b34b-6370108d2489
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014020017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2014020017
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2287220457
Short name T15
Test name
Test status
Simulation time 8158715562 ps
CPU time 415.61 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 01:02:37 PM PST 24
Peak memory 369592 kb
Host smart-d393c40b-ba7b-494e-918c-8132e4e51bd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287220457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.2287220457
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2794600580
Short name T955
Test name
Test status
Simulation time 17437506 ps
CPU time 0.68 seconds
Started Jan 03 12:53:07 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 201756 kb
Host smart-10c5a483-786e-49a7-913a-b918adc7654d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794600580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2794600580
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.2053825645
Short name T123
Test name
Test status
Simulation time 1644271624 ps
CPU time 34.44 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 202780 kb
Host smart-35e4dd08-c66f-4ad8-8125-63dcda094f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053825645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.2053825645
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.1387560944
Short name T238
Test name
Test status
Simulation time 14836375389 ps
CPU time 880.07 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 01:08:55 PM PST 24
Peak memory 372616 kb
Host smart-2e42de69-c558-4e03-9edc-918f931b8a5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387560944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.1387560944
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1659500452
Short name T415
Test name
Test status
Simulation time 1938825013 ps
CPU time 11.65 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:17 PM PST 24
Peak memory 212120 kb
Host smart-d4e8fa35-850e-4496-84ba-13781d4fb0ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659500452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1659500452
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.4025461552
Short name T239
Test name
Test status
Simulation time 247014918 ps
CPU time 71.57 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:56:29 PM PST 24
Peak memory 331320 kb
Host smart-6c58f68f-2aa6-4b31-b537-e72d0657e4b6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025461552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.4025461552
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.135638562
Short name T73
Test name
Test status
Simulation time 65692035 ps
CPU time 4.58 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 210960 kb
Host smart-df3adcda-d758-45d9-8f71-3005bcf2e4a4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135638562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_mem_partial_access.135638562
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.4166537589
Short name T819
Test name
Test status
Simulation time 137341282 ps
CPU time 7.91 seconds
Started Jan 03 12:53:21 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 202972 kb
Host smart-0a59f6f6-042b-4679-bf37-a4e7c99d350f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166537589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.4166537589
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3256587991
Short name T815
Test name
Test status
Simulation time 10403728095 ps
CPU time 809.3 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 01:08:45 PM PST 24
Peak memory 356232 kb
Host smart-0abfc134-ba46-41be-8699-69404b45c71c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256587991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3256587991
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1969248018
Short name T907
Test name
Test status
Simulation time 332161216 ps
CPU time 16.41 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 202796 kb
Host smart-1f1b18f7-3290-429d-9b72-c9411f394ad5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969248018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1969248018
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3835420043
Short name T812
Test name
Test status
Simulation time 21039852420 ps
CPU time 532.5 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 01:04:03 PM PST 24
Peak memory 203072 kb
Host smart-f8b6a2ed-9473-46c1-a443-3faba58002b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835420043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.3835420043
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3181199908
Short name T600
Test name
Test status
Simulation time 86040077 ps
CPU time 1.08 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 203024 kb
Host smart-0eb8dd2e-468a-47ea-bd04-4032aca03503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181199908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3181199908
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1430258224
Short name T110
Test name
Test status
Simulation time 644151120 ps
CPU time 17.7 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 267988 kb
Host smart-24aa7a2b-745f-41cc-b1fe-6cfbde787ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430258224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1430258224
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.947703597
Short name T335
Test name
Test status
Simulation time 3017366960 ps
CPU time 13.24 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 202960 kb
Host smart-2a31e3e4-66a5-45b5-94dc-6e0b36fd4f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947703597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.947703597
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.2560307848
Short name T756
Test name
Test status
Simulation time 26061997693 ps
CPU time 3364.04 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 01:50:49 PM PST 24
Peak memory 375696 kb
Host smart-abe4c942-ad4d-4d33-bc79-d26fced8d9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560307848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.2560307848
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1281950290
Short name T795
Test name
Test status
Simulation time 395597592 ps
CPU time 1809.26 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 01:24:10 PM PST 24
Peak memory 422548 kb
Host smart-c9b195e2-6436-48a4-b9b2-5b01a4aab12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1281950290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1281950290
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1098516049
Short name T570
Test name
Test status
Simulation time 3560691153 ps
CPU time 321.73 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 01:00:43 PM PST 24
Peak memory 202836 kb
Host smart-ba9ae0a1-3fce-457f-8658-1ebeb8e53b69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098516049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1098516049
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3510243357
Short name T432
Test name
Test status
Simulation time 590189335 ps
CPU time 97.86 seconds
Started Jan 03 12:53:19 PM PST 24
Finished Jan 03 12:55:41 PM PST 24
Peak memory 361816 kb
Host smart-17f1856c-8207-4d93-8469-efea56c4a319
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510243357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3510243357
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3995969527
Short name T881
Test name
Test status
Simulation time 19123492114 ps
CPU time 1484.9 seconds
Started Jan 03 12:52:44 PM PST 24
Finished Jan 03 01:19:03 PM PST 24
Peak memory 376740 kb
Host smart-f20ebf94-9da6-43f2-bf4e-e45e76f3c610
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995969527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.3995969527
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.3880917401
Short name T249
Test name
Test status
Simulation time 24456222 ps
CPU time 0.61 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 202688 kb
Host smart-f3309d6a-faf4-4dc0-8287-74f608b9cc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880917401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.3880917401
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2766108788
Short name T35
Test name
Test status
Simulation time 1084576162 ps
CPU time 63.06 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 202716 kb
Host smart-402d80c3-3264-4334-9f24-2abf1f277967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766108788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2766108788
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.3788596435
Short name T353
Test name
Test status
Simulation time 15747190045 ps
CPU time 576.57 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 01:03:36 PM PST 24
Peak memory 362516 kb
Host smart-bd95df23-e21b-4f20-82c9-022829e4baf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788596435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.3788596435
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3445628598
Short name T840
Test name
Test status
Simulation time 79173806 ps
CPU time 1.83 seconds
Started Jan 03 12:52:53 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 202832 kb
Host smart-e6d164ee-7056-433e-93df-a4c4db15b8d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445628598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3445628598
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.136518976
Short name T379
Test name
Test status
Simulation time 129014718 ps
CPU time 99.41 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 355492 kb
Host smart-c184c368-df89-41f8-ba59-6b3fb27309f5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136518976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.136518976
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.957925964
Short name T372
Test name
Test status
Simulation time 124609080 ps
CPU time 4.84 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 215744 kb
Host smart-30b4972c-263a-4bcc-8933-bdaf25579d17
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957925964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_mem_partial_access.957925964
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.2308786571
Short name T371
Test name
Test status
Simulation time 3632662788 ps
CPU time 10.99 seconds
Started Jan 03 12:52:52 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 202912 kb
Host smart-1f0d36df-09fb-40d6-a4b2-6e2fb1d1a70b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308786571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.2308786571
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3855647219
Short name T668
Test name
Test status
Simulation time 5217471823 ps
CPU time 19.41 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:44 PM PST 24
Peak memory 202868 kb
Host smart-534f5a5e-6c06-4f8b-840b-239aafdcffbe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855647219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.3855647219
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1361234029
Short name T801
Test name
Test status
Simulation time 53421781752 ps
CPU time 325.05 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:59:46 PM PST 24
Peak memory 203000 kb
Host smart-8755b83b-5f2f-4ebd-926a-8dfbea811e8b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361234029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1361234029
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3222669953
Short name T929
Test name
Test status
Simulation time 2296076018 ps
CPU time 160 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 338448 kb
Host smart-ace75343-f753-4e77-b2c7-2865b57b0172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222669953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3222669953
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.64498277
Short name T609
Test name
Test status
Simulation time 3439636196 ps
CPU time 3175.47 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 01:46:59 PM PST 24
Peak memory 470012 kb
Host smart-babd9a5d-7697-4cf2-8af2-cec3f76f8301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=64498277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.64498277
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1368703467
Short name T7
Test name
Test status
Simulation time 4021638395 ps
CPU time 377.78 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 202840 kb
Host smart-e5dd8412-f62b-4b43-b457-11ffb2d54420
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368703467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1368703467
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3235683753
Short name T817
Test name
Test status
Simulation time 215349663 ps
CPU time 4.22 seconds
Started Jan 03 12:53:06 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 220196 kb
Host smart-2f719213-0a73-4d08-845d-4cab4385cdf1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235683753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3235683753
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3551354376
Short name T744
Test name
Test status
Simulation time 4303083647 ps
CPU time 1197.02 seconds
Started Jan 03 12:53:26 PM PST 24
Finished Jan 03 01:14:15 PM PST 24
Peak memory 375748 kb
Host smart-2d7d0773-751f-4c71-8e4f-5684dc52f432
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551354376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3551354376
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3597542763
Short name T490
Test name
Test status
Simulation time 15345524 ps
CPU time 0.65 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 201876 kb
Host smart-9c9896c3-d9c3-4e76-9ca1-3e2da2fb878d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597542763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3597542763
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.74266120
Short name T367
Test name
Test status
Simulation time 24799735891 ps
CPU time 34.8 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 202884 kb
Host smart-d9a5eed6-0eb4-46a5-bfe5-43258262e855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74266120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.74266120
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.296001266
Short name T398
Test name
Test status
Simulation time 675547094 ps
CPU time 2.76 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 211092 kb
Host smart-9af7d57a-40cd-42a6-ac9e-b77c72e9a2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296001266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc
alation.296001266
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.4139719234
Short name T591
Test name
Test status
Simulation time 227701775 ps
CPU time 11.46 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:26 PM PST 24
Peak memory 251860 kb
Host smart-d5362671-d48d-4ff8-9971-eb1e890b17ee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139719234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.4139719234
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3971247400
Short name T468
Test name
Test status
Simulation time 91015183 ps
CPU time 3.06 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 219300 kb
Host smart-ed528dff-1206-47a8-bdab-73845307baa3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971247400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.3971247400
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2308965228
Short name T464
Test name
Test status
Simulation time 889194638 ps
CPU time 9.55 seconds
Started Jan 03 12:53:04 PM PST 24
Finished Jan 03 12:54:33 PM PST 24
Peak memory 202840 kb
Host smart-5a2fc022-ac43-404f-8d1b-6cf5276c9833
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308965228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2308965228
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2648911128
Short name T904
Test name
Test status
Simulation time 16130412576 ps
CPU time 505.38 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 01:02:46 PM PST 24
Peak memory 375712 kb
Host smart-664d8746-2209-4f71-b7b2-eeca6e97a416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648911128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2648911128
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3509202226
Short name T612
Test name
Test status
Simulation time 168669235 ps
CPU time 49.53 seconds
Started Jan 03 12:52:43 PM PST 24
Finished Jan 03 12:55:08 PM PST 24
Peak memory 334648 kb
Host smart-81a5c875-3720-45cd-9d9b-fe6af5c5c377
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509202226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3509202226
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1256901001
Short name T826
Test name
Test status
Simulation time 164417585010 ps
CPU time 347.97 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 12:59:49 PM PST 24
Peak memory 203084 kb
Host smart-e301320f-4acd-41aa-8da2-0de829326316
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256901001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.1256901001
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.4154432411
Short name T306
Test name
Test status
Simulation time 47940711 ps
CPU time 1 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:00 PM PST 24
Peak memory 203020 kb
Host smart-b4094f10-2f47-4ccf-93cf-367533fd6f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154432411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4154432411
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.519376747
Short name T734
Test name
Test status
Simulation time 1934753152 ps
CPU time 602.98 seconds
Started Jan 03 12:52:56 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 374864 kb
Host smart-08fa84b1-9ef2-484e-85d0-cbc4c751a779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519376747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.519376747
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.4149548023
Short name T821
Test name
Test status
Simulation time 3350666038 ps
CPU time 93.66 seconds
Started Jan 03 12:52:46 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 365556 kb
Host smart-d27d3a08-02f3-4aa3-bd80-ac334e3a51ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149548023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4149548023
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.2700374826
Short name T431
Test name
Test status
Simulation time 96164729571 ps
CPU time 1414.33 seconds
Started Jan 03 12:52:48 PM PST 24
Finished Jan 03 01:17:43 PM PST 24
Peak memory 381888 kb
Host smart-4b8384e2-6fd4-47a5-ba72-c46d92c2a3eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700374826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.2700374826
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2401882231
Short name T380
Test name
Test status
Simulation time 2233450177 ps
CPU time 216.73 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:58:34 PM PST 24
Peak memory 202940 kb
Host smart-7529c503-ebb2-4212-bde6-a92854329cc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401882231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.2401882231
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3824128858
Short name T297
Test name
Test status
Simulation time 156905488 ps
CPU time 83.18 seconds
Started Jan 03 12:53:06 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 363756 kb
Host smart-131ae811-2354-4a31-8211-7fcf617dabe4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824128858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3824128858
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3761433126
Short name T906
Test name
Test status
Simulation time 17686130445 ps
CPU time 827.29 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 01:07:49 PM PST 24
Peak memory 375912 kb
Host smart-76f0965a-5939-4495-b56f-4b89f75e66ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761433126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3761433126
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.1356584354
Short name T903
Test name
Test status
Simulation time 34759020 ps
CPU time 0.62 seconds
Started Jan 03 12:53:20 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 201836 kb
Host smart-e4bc9d92-94e4-484d-b3ab-a93f3a7a4bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356584354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.1356584354
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.1202938567
Short name T301
Test name
Test status
Simulation time 1796834621 ps
CPU time 18.73 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 202912 kb
Host smart-21b56047-bf77-43bc-a9dd-feaf97c4c68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202938567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.1202938567
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.2709072097
Short name T292
Test name
Test status
Simulation time 32968257973 ps
CPU time 476.75 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 01:02:06 PM PST 24
Peak memory 364132 kb
Host smart-80599dac-d5f8-470b-8550-134f0818619c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709072097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.2709072097
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.201373674
Short name T231
Test name
Test status
Simulation time 1872269226 ps
CPU time 3.13 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:28 PM PST 24
Peak memory 202900 kb
Host smart-e74ceddf-9cdd-4592-b9d2-51e0430ad990
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201373674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc
alation.201373674
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.2513676800
Short name T964
Test name
Test status
Simulation time 133249961 ps
CPU time 13.98 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 258732 kb
Host smart-31d85b4d-440e-4e45-ae96-f0129c64a0e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513676800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.2513676800
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4039373600
Short name T767
Test name
Test status
Simulation time 636985763 ps
CPU time 3.15 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 211060 kb
Host smart-bd387285-9f88-4e77-8468-9fd951c41613
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039373600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.4039373600
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1773823095
Short name T341
Test name
Test status
Simulation time 378794368 ps
CPU time 5.4 seconds
Started Jan 03 12:52:58 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 202924 kb
Host smart-cb2d1233-073f-4fb8-bc3a-eedf1ecc34c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773823095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1773823095
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.4261705864
Short name T753
Test name
Test status
Simulation time 31467522240 ps
CPU time 662.93 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 346960 kb
Host smart-c966431c-f6aa-4e6b-9828-52d2fc0edb1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261705864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.4261705864
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.2655772231
Short name T611
Test name
Test status
Simulation time 1027153317 ps
CPU time 10.8 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:53 PM PST 24
Peak memory 202896 kb
Host smart-fe3fd18c-818f-4dc6-a344-d05ef45fa078
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655772231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.2655772231
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3121123101
Short name T93
Test name
Test status
Simulation time 7267052295 ps
CPU time 255.38 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 12:58:30 PM PST 24
Peak memory 202936 kb
Host smart-8171c459-c436-4c9c-9075-d9209e06ca73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121123101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3121123101
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2561776775
Short name T237
Test name
Test status
Simulation time 174016425 ps
CPU time 0.85 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 202924 kb
Host smart-04a963aa-67aa-44e2-ad24-afc91d1a71ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561776775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2561776775
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.3883722766
Short name T871
Test name
Test status
Simulation time 13427248974 ps
CPU time 431.99 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 01:01:46 PM PST 24
Peak memory 329036 kb
Host smart-36e07c15-0b39-4e80-a3fe-0f7f10a8c6c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883722766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3883722766
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.256882565
Short name T936
Test name
Test status
Simulation time 1328023380 ps
CPU time 2.39 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 205736 kb
Host smart-1a30e1c5-f03e-4d09-be31-14187f1db350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256882565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.256882565
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.230841145
Short name T567
Test name
Test status
Simulation time 8960210314 ps
CPU time 1507.35 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 01:20:04 PM PST 24
Peak memory 416156 kb
Host smart-b74f8cb4-68d3-4caa-a87c-235b9dd10129
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=230841145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.230841145
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.440619912
Short name T14
Test name
Test status
Simulation time 2497813505 ps
CPU time 234.61 seconds
Started Jan 03 12:52:55 PM PST 24
Finished Jan 03 12:58:12 PM PST 24
Peak memory 202964 kb
Host smart-39696f21-e51b-4f8d-9f76-1313374a5005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440619912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.440619912
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1170037777
Short name T116
Test name
Test status
Simulation time 115602284 ps
CPU time 1.51 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:26 PM PST 24
Peak memory 202672 kb
Host smart-320e6652-d7cb-448a-889f-5ff84817f0a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170037777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1170037777
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.624124285
Short name T232
Test name
Test status
Simulation time 4009658361 ps
CPU time 306.2 seconds
Started Jan 03 12:53:02 PM PST 24
Finished Jan 03 12:59:29 PM PST 24
Peak memory 365532 kb
Host smart-f8138135-7b5a-44aa-9ab4-6a46c65ba8bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624124285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.sram_ctrl_access_during_key_req.624124285
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.4024635506
Short name T20
Test name
Test status
Simulation time 15049359 ps
CPU time 0.61 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:06 PM PST 24
Peak memory 202732 kb
Host smart-bd706000-6e21-4de1-b27a-fca91ce70711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024635506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.4024635506
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.288673404
Short name T52
Test name
Test status
Simulation time 857975693 ps
CPU time 54.28 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 202876 kb
Host smart-67a7104a-924d-46ac-8636-0bcb07d088d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288673404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
288673404
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.2533681252
Short name T428
Test name
Test status
Simulation time 40291182597 ps
CPU time 651.85 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 371564 kb
Host smart-c60a96e4-031e-46e7-8c53-36d31e1aa8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533681252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.2533681252
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.1830628315
Short name T677
Test name
Test status
Simulation time 127313936 ps
CPU time 1.96 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 202904 kb
Host smart-79abfeb1-6e35-45e7-89eb-13128d51f650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830628315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.1830628315
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1576321093
Short name T616
Test name
Test status
Simulation time 126786111 ps
CPU time 58.82 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 344472 kb
Host smart-73f2dd6c-8734-43cc-be22-341e817c6cf6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576321093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1576321093
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.164797250
Short name T618
Test name
Test status
Simulation time 176530835 ps
CPU time 5.3 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 211016 kb
Host smart-448e18cd-1f7b-4e11-8e95-b40fbabf4398
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164797250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_mem_partial_access.164797250
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.772993281
Short name T441
Test name
Test status
Simulation time 266820061 ps
CPU time 4.33 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 202856 kb
Host smart-f6567cb9-e61d-4b05-9abb-7e082dce7214
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772993281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.772993281
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.3944815027
Short name T377
Test name
Test status
Simulation time 13775249086 ps
CPU time 620.2 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 369632 kb
Host smart-081815c2-c5e4-4dde-b3cb-b08fa3215400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944815027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.3944815027
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.4102625355
Short name T704
Test name
Test status
Simulation time 1327560765 ps
CPU time 22.01 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:54 PM PST 24
Peak memory 279356 kb
Host smart-404af1cd-933e-428b-8746-223240bb548f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102625355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.4102625355
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1611863829
Short name T864
Test name
Test status
Simulation time 22873258447 ps
CPU time 270.39 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:59:55 PM PST 24
Peak memory 203040 kb
Host smart-02ebf9df-2ec9-440a-9318-578209e1fea2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611863829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1611863829
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.251554250
Short name T417
Test name
Test status
Simulation time 80672368 ps
CPU time 1.03 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 203016 kb
Host smart-34b4b006-1fe6-497a-ac7e-52d09c727ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251554250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.251554250
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.470681480
Short name T883
Test name
Test status
Simulation time 1015276841 ps
CPU time 191.33 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 351968 kb
Host smart-c2159286-9496-489f-8329-fa7bf903619e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470681480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.470681480
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2372791144
Short name T799
Test name
Test status
Simulation time 638560992 ps
CPU time 93.98 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:56:30 PM PST 24
Peak memory 365672 kb
Host smart-8557daa0-81e4-4dcb-8a49-43032ec95b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372791144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2372791144
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.219766180
Short name T855
Test name
Test status
Simulation time 87746095256 ps
CPU time 2530.76 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 01:37:05 PM PST 24
Peak memory 376840 kb
Host smart-b96e82b3-62bc-4539-ae48-f484cfca2634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219766180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_stress_all.219766180
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1279302739
Short name T880
Test name
Test status
Simulation time 4375456356 ps
CPU time 1799.96 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 01:24:38 PM PST 24
Peak memory 451880 kb
Host smart-5d72d43c-1c80-4ab3-a993-7a1491eda2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1279302739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1279302739
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1475315521
Short name T234
Test name
Test status
Simulation time 5647273575 ps
CPU time 269.33 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:58:53 PM PST 24
Peak memory 202944 kb
Host smart-f153a19f-3057-46b0-9d40-37a31a55075d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475315521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1475315521
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4029539358
Short name T304
Test name
Test status
Simulation time 509336085 ps
CPU time 3 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 216564 kb
Host smart-7aaee003-bb40-455c-8654-a0b8b14d767c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029539358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.4029539358
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2830439415
Short name T867
Test name
Test status
Simulation time 4587848184 ps
CPU time 826.92 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 01:08:56 PM PST 24
Peak memory 370652 kb
Host smart-cacf4ad2-6160-4df8-8b43-b8c5fabea2a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830439415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.2830439415
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.634478104
Short name T696
Test name
Test status
Simulation time 13263746 ps
CPU time 0.63 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 202696 kb
Host smart-403a0cdd-7c89-4960-ab00-2e585c32d7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634478104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.634478104
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.583509510
Short name T408
Test name
Test status
Simulation time 1059134007 ps
CPU time 22.79 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:19 PM PST 24
Peak memory 202836 kb
Host smart-2ca6bbde-6331-4496-a7ec-e07335ef6b37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583509510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.
583509510
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.2191785577
Short name T761
Test name
Test status
Simulation time 18341445133 ps
CPU time 378.78 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 01:01:19 PM PST 24
Peak memory 357064 kb
Host smart-0c23e1de-3f94-4cec-8319-3c8c67506716
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191785577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.2191785577
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1619798781
Short name T442
Test name
Test status
Simulation time 47367963 ps
CPU time 3.29 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 218852 kb
Host smart-450ea3de-6794-4ee3-b00e-306484090b21
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619798781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1619798781
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.427895424
Short name T626
Test name
Test status
Simulation time 46511157 ps
CPU time 2.8 seconds
Started Jan 03 12:53:18 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 212288 kb
Host smart-a652602f-c1bd-4ffc-870b-6f50588cbc6e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427895424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_mem_partial_access.427895424
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.2020647531
Short name T953
Test name
Test status
Simulation time 1323979554 ps
CPU time 5.37 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 202864 kb
Host smart-fc95dda8-6a40-4edc-842e-ece794ffcd79
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020647531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.2020647531
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3614174433
Short name T479
Test name
Test status
Simulation time 5502770753 ps
CPU time 370.55 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 01:00:10 PM PST 24
Peak memory 375756 kb
Host smart-e8864f37-dec3-4f98-80f7-74237f8cd726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614174433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3614174433
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.1006409452
Short name T334
Test name
Test status
Simulation time 409263072 ps
CPU time 20.76 seconds
Started Jan 03 12:53:21 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 274012 kb
Host smart-fa75ffe5-fd23-432a-982d-5d9950adb9b8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006409452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.1006409452
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3980505296
Short name T91
Test name
Test status
Simulation time 5026388776 ps
CPU time 333.15 seconds
Started Jan 03 12:53:05 PM PST 24
Finished Jan 03 12:59:39 PM PST 24
Peak memory 202868 kb
Host smart-450e85ff-85b0-47c8-bf9d-7d4db6f16bd3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980505296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.3980505296
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.3764037391
Short name T478
Test name
Test status
Simulation time 54750424 ps
CPU time 0.85 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 12:54:00 PM PST 24
Peak memory 202936 kb
Host smart-c489ba77-991d-49c4-b489-fb355e3ef8b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764037391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3764037391
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.882916773
Short name T1
Test name
Test status
Simulation time 7453737363 ps
CPU time 258.75 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:59:07 PM PST 24
Peak memory 355720 kb
Host smart-703ab62b-38f1-4b95-ba40-4219b23e1905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882916773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.882916773
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2336320631
Short name T797
Test name
Test status
Simulation time 2169794124 ps
CPU time 9.71 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 241376 kb
Host smart-9c4fdf7d-bf8c-4a00-a580-7edf56d3a952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336320631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2336320631
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.128168566
Short name T703
Test name
Test status
Simulation time 12347229150 ps
CPU time 2548.74 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 01:36:44 PM PST 24
Peak memory 382032 kb
Host smart-2729e805-e68b-49fc-8d00-5b0a20170cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128168566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_stress_all.128168566
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2539527145
Short name T847
Test name
Test status
Simulation time 1251017297 ps
CPU time 4469.62 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 02:09:12 PM PST 24
Peak memory 420576 kb
Host smart-2a3a6338-9280-4ec7-a566-2c12102aeb7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2539527145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2539527145
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.191750848
Short name T92
Test name
Test status
Simulation time 4521219875 ps
CPU time 209.37 seconds
Started Jan 03 12:53:27 PM PST 24
Finished Jan 03 12:57:47 PM PST 24
Peak memory 202968 kb
Host smart-90ed40bf-9544-4f5f-a090-cdaccd93ee40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191750848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_stress_pipeline.191750848
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1894487314
Short name T862
Test name
Test status
Simulation time 159902427 ps
CPU time 95.73 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:56:51 PM PST 24
Peak memory 357236 kb
Host smart-4f90ffd6-3cc1-4b80-81e0-2015024712b3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894487314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1894487314
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.877290648
Short name T345
Test name
Test status
Simulation time 4964259269 ps
CPU time 1402.88 seconds
Started Jan 03 12:53:16 PM PST 24
Finished Jan 03 01:17:24 PM PST 24
Peak memory 374972 kb
Host smart-34ee3bcd-f7d2-4517-8178-75cf87db3556
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877290648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.sram_ctrl_access_during_key_req.877290648
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.4096228691
Short name T425
Test name
Test status
Simulation time 29318266 ps
CPU time 0.64 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 201792 kb
Host smart-1c2543b8-ec01-487e-9352-5af1a44554b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096228691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.4096228691
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.80800893
Short name T651
Test name
Test status
Simulation time 554077669 ps
CPU time 33.09 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 202668 kb
Host smart-c9e0e88a-740b-4ce2-949c-f2a8c5fd2933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80800893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.80800893
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.807176064
Short name T934
Test name
Test status
Simulation time 36603988553 ps
CPU time 531.9 seconds
Started Jan 03 12:53:18 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 371804 kb
Host smart-950d1c33-f438-4439-a865-dbdfadd9d05a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807176064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.807176064
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2203586159
Short name T614
Test name
Test status
Simulation time 571216676 ps
CPU time 8.03 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 211132 kb
Host smart-f8468b9a-d473-4106-bd1c-4921a375887b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203586159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.2203586159
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.1801431166
Short name T919
Test name
Test status
Simulation time 472968514 ps
CPU time 108.12 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:56:22 PM PST 24
Peak memory 367260 kb
Host smart-2f10fca7-bb71-4296-8bbf-ce39acd8869b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801431166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.1801431166
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.80978485
Short name T725
Test name
Test status
Simulation time 47882826 ps
CPU time 2.92 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:38 PM PST 24
Peak memory 211012 kb
Host smart-58d346de-3f22-4e2a-9dc2-22ee91a1f650
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80978485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_mem_partial_access.80978485
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3940483916
Short name T984
Test name
Test status
Simulation time 5665381415 ps
CPU time 11.45 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:19 PM PST 24
Peak memory 202852 kb
Host smart-7173185e-838a-4b53-947e-44925a7eabea
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940483916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3940483916
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.497611157
Short name T494
Test name
Test status
Simulation time 51957464176 ps
CPU time 751.03 seconds
Started Jan 03 12:53:07 PM PST 24
Finished Jan 03 01:06:40 PM PST 24
Peak memory 376152 kb
Host smart-8ab12e5f-62c1-455d-9677-75f2e9db3991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497611157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.497611157
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.4007442763
Short name T233
Test name
Test status
Simulation time 440018928 ps
CPU time 5.91 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 202900 kb
Host smart-da1661a3-c61e-4203-a72d-4967e48f4d07
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007442763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.4007442763
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3380666514
Short name T669
Test name
Test status
Simulation time 17699721302 ps
CPU time 380.49 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 01:01:41 PM PST 24
Peak memory 203040 kb
Host smart-d2f2c51d-8b33-4dd7-aef1-cd1a208e3786
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380666514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.3380666514
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.623398444
Short name T484
Test name
Test status
Simulation time 66824428222 ps
CPU time 1371.26 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 01:16:52 PM PST 24
Peak memory 371728 kb
Host smart-95b70f7f-85e6-499e-9638-25b7794f6279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623398444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.623398444
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1192927826
Short name T902
Test name
Test status
Simulation time 997448463 ps
CPU time 5.86 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 202900 kb
Host smart-7aa039f8-88c8-49ca-b567-57bd5b28e52b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192927826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1192927826
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.153626887
Short name T336
Test name
Test status
Simulation time 54897509310 ps
CPU time 4018.89 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 02:01:20 PM PST 24
Peak memory 377880 kb
Host smart-bc30c0a1-71d9-4cd4-a60d-2247bc179155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153626887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_stress_all.153626887
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1169996248
Short name T577
Test name
Test status
Simulation time 1103972354 ps
CPU time 2815.98 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 01:41:34 PM PST 24
Peak memory 419188 kb
Host smart-4b48878b-a958-4e00-95f6-9c68bbd97e5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1169996248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1169996248
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1284775280
Short name T329
Test name
Test status
Simulation time 2002942192 ps
CPU time 188.69 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:58:24 PM PST 24
Peak memory 202872 kb
Host smart-ddf154e5-d203-4f13-8832-228541251df4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284775280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.1284775280
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.85822944
Short name T326
Test name
Test status
Simulation time 2916047775 ps
CPU time 98.66 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:56:32 PM PST 24
Peak memory 364076 kb
Host smart-6896dad4-3c47-47a7-bb9f-b309c0ffb54f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85822944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.sram_ctrl_throughput_w_partial_write.85822944
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2086849548
Short name T610
Test name
Test status
Simulation time 14819127024 ps
CPU time 634.46 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 375784 kb
Host smart-b69888ea-87af-4129-aa9e-f6862d4af77d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086849548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.2086849548
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.1696193283
Short name T644
Test name
Test status
Simulation time 20844072 ps
CPU time 0.65 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 202600 kb
Host smart-7c2b2a90-6b56-42d4-a7d5-b69eaa397d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696193283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.1696193283
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2301183738
Short name T632
Test name
Test status
Simulation time 19483285294 ps
CPU time 78.18 seconds
Started Jan 03 12:53:18 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 202944 kb
Host smart-f0df8ee1-079c-4815-b4c8-86774a0d77ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301183738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2301183738
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1817994580
Short name T741
Test name
Test status
Simulation time 11686005253 ps
CPU time 916.63 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 01:09:58 PM PST 24
Peak memory 373256 kb
Host smart-ba63af87-194c-4909-b9c7-5d39b3555385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817994580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1817994580
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.3804212943
Short name T539
Test name
Test status
Simulation time 1355912853 ps
CPU time 6.49 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:40 PM PST 24
Peak memory 210984 kb
Host smart-e0420044-8286-41c1-a07b-5982e8f7eaa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804212943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.3804212943
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.367335262
Short name T652
Test name
Test status
Simulation time 481492504 ps
CPU time 82.02 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:56:11 PM PST 24
Peak memory 353052 kb
Host smart-ea9970af-1517-4d4e-bd62-1b85ce828f6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367335262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.sram_ctrl_max_throughput.367335262
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.139531283
Short name T516
Test name
Test status
Simulation time 344072803 ps
CPU time 2.96 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 219304 kb
Host smart-8f1fc6c1-e2d5-48a8-b6e4-e875b5d4cedf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139531283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_mem_partial_access.139531283
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.870240028
Short name T119
Test name
Test status
Simulation time 672398543 ps
CPU time 5.39 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 202824 kb
Host smart-6fbdfa56-d05f-479d-8e91-8bbc741ee88a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870240028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_mem_walk.870240028
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1414523064
Short name T633
Test name
Test status
Simulation time 15194070975 ps
CPU time 864.6 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 01:08:54 PM PST 24
Peak memory 371612 kb
Host smart-3ba0f53a-6dc8-4fe3-8f3a-dc0fff7da735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414523064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1414523064
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3853439717
Short name T469
Test name
Test status
Simulation time 2369963635 ps
CPU time 106.67 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 356780 kb
Host smart-15e8c5d0-c5a9-4224-8ba6-67a11f93a486
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853439717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3853439717
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4010552114
Short name T277
Test name
Test status
Simulation time 6264930466 ps
CPU time 452.45 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 203028 kb
Host smart-f1269462-bad2-4ac2-b206-f0b6a13f5ec4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010552114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.4010552114
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.4244349054
Short name T587
Test name
Test status
Simulation time 82371460 ps
CPU time 1.15 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 203036 kb
Host smart-79c695ba-00ae-44a1-a11d-1a1d49285f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244349054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4244349054
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.946769254
Short name T894
Test name
Test status
Simulation time 8972291489 ps
CPU time 388.56 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 01:01:23 PM PST 24
Peak memory 321428 kb
Host smart-4a2afb6c-26d5-40ea-8015-706277425567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946769254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.946769254
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1978246587
Short name T838
Test name
Test status
Simulation time 809854006 ps
CPU time 9.32 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 202924 kb
Host smart-b1712051-193d-4f31-9d4c-80c89b58ed7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978246587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1978246587
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.1034064294
Short name T771
Test name
Test status
Simulation time 210133910074 ps
CPU time 3457.12 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 01:52:34 PM PST 24
Peak memory 374528 kb
Host smart-2a163541-3639-4c9b-96d1-ec71a7eadd9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034064294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.1034064294
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2403665649
Short name T28
Test name
Test status
Simulation time 422640028 ps
CPU time 1687.27 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 01:22:52 PM PST 24
Peak memory 418360 kb
Host smart-30a0ed3f-1163-401d-a393-9f3de6369211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2403665649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2403665649
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2624669784
Short name T291
Test name
Test status
Simulation time 8297156332 ps
CPU time 361.32 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 01:00:04 PM PST 24
Peak memory 202876 kb
Host smart-2193e4c4-c82d-4073-9cfa-befe6c8a721d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624669784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2624669784
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3565046141
Short name T354
Test name
Test status
Simulation time 215456285 ps
CPU time 6.27 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 235448 kb
Host smart-9d48ddf9-f700-4ca3-997f-6c97aa22da6b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565046141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3565046141
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1604820393
Short name T673
Test name
Test status
Simulation time 4427703744 ps
CPU time 400.1 seconds
Started Jan 03 12:51:33 PM PST 24
Finished Jan 03 12:58:25 PM PST 24
Peak memory 367120 kb
Host smart-e1aa9a95-a238-4db3-89d7-d85c99502256
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604820393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1604820393
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2822271907
Short name T985
Test name
Test status
Simulation time 13870747 ps
CPU time 0.69 seconds
Started Jan 03 12:51:48 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 202680 kb
Host smart-0428fac1-bf90-4469-a4af-9b7d34244d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822271907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2822271907
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3282563570
Short name T257
Test name
Test status
Simulation time 3442740344 ps
CPU time 69.81 seconds
Started Jan 03 12:51:33 PM PST 24
Finished Jan 03 12:52:54 PM PST 24
Peak memory 202856 kb
Host smart-59a21fa3-666f-49a0-9389-9b4e3820a234
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282563570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3282563570
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.1205539552
Short name T224
Test name
Test status
Simulation time 29277757982 ps
CPU time 732.2 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 01:04:06 PM PST 24
Peak memory 361356 kb
Host smart-adf1b31d-32cb-492e-947f-b324f74a4b97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205539552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.1205539552
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.2905617834
Short name T429
Test name
Test status
Simulation time 1606849661 ps
CPU time 3.76 seconds
Started Jan 03 12:51:37 PM PST 24
Finished Jan 03 12:51:52 PM PST 24
Peak memory 211072 kb
Host smart-a0f215fa-54ab-4538-9e72-9d1e389ebffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905617834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.2905617834
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.3686877112
Short name T830
Test name
Test status
Simulation time 223834574 ps
CPU time 6.09 seconds
Started Jan 03 12:51:37 PM PST 24
Finished Jan 03 12:51:54 PM PST 24
Peak memory 235648 kb
Host smart-6dfa6413-bc20-4140-8b90-9ce1b92c1440
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686877112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.3686877112
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3796684246
Short name T924
Test name
Test status
Simulation time 590050656 ps
CPU time 4.62 seconds
Started Jan 03 12:51:40 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 212072 kb
Host smart-5c91a8ef-88e1-4d3c-a4af-383638d8bc69
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796684246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3796684246
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.515919855
Short name T965
Test name
Test status
Simulation time 308709176 ps
CPU time 5.4 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:51:51 PM PST 24
Peak memory 202856 kb
Host smart-27cbe0c6-81ec-4ead-87ef-cac57bc53ea8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515919855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
mem_walk.515919855
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3867716749
Short name T605
Test name
Test status
Simulation time 5036588311 ps
CPU time 311.6 seconds
Started Jan 03 12:51:34 PM PST 24
Finished Jan 03 12:56:57 PM PST 24
Peak memory 316560 kb
Host smart-a91b9af8-8018-492f-b258-f36a2e4d3920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867716749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3867716749
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3698922274
Short name T310
Test name
Test status
Simulation time 162148435 ps
CPU time 44.3 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:52:38 PM PST 24
Peak memory 314152 kb
Host smart-1dc511f5-4e90-4bf2-ab42-d5f489fa7d44
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698922274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3698922274
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.844817065
Short name T419
Test name
Test status
Simulation time 28950327542 ps
CPU time 350.48 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 203076 kb
Host smart-e2836a36-342f-4e4d-a60d-9a04663cfae6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844817065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.844817065
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1950783444
Short name T713
Test name
Test status
Simulation time 147041768 ps
CPU time 0.83 seconds
Started Jan 03 12:51:49 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 202928 kb
Host smart-de6009f7-b103-4995-839d-ec149747975c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950783444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1950783444
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.35482735
Short name T24
Test name
Test status
Simulation time 17468336741 ps
CPU time 600.14 seconds
Started Jan 03 12:51:54 PM PST 24
Finished Jan 03 01:02:00 PM PST 24
Peak memory 374752 kb
Host smart-ae695a87-4f28-4737-a791-8aba38fec157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.35482735
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.1045810678
Short name T344
Test name
Test status
Simulation time 244157349 ps
CPU time 14.63 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:52:09 PM PST 24
Peak memory 202752 kb
Host smart-77634efe-fd0f-4c9d-b07b-44f27ad9b40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045810678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1045810678
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.1671965238
Short name T664
Test name
Test status
Simulation time 221876648623 ps
CPU time 3289.15 seconds
Started Jan 03 12:51:47 PM PST 24
Finished Jan 03 01:46:45 PM PST 24
Peak memory 374816 kb
Host smart-761a4705-0e66-4587-a6ec-ae24122e0c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671965238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.1671965238
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.541051629
Short name T860
Test name
Test status
Simulation time 280805658 ps
CPU time 1552.14 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 01:18:05 PM PST 24
Peak memory 449396 kb
Host smart-6cef996e-14f0-431a-ac16-09bd1e71533d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=541051629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.541051629
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.517277876
Short name T884
Test name
Test status
Simulation time 8014031905 ps
CPU time 202.5 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 202964 kb
Host smart-ec515718-ce6c-425c-9825-669b9bb093fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517277876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.517277876
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4058253296
Short name T654
Test name
Test status
Simulation time 462396335 ps
CPU time 34.01 seconds
Started Jan 03 12:51:49 PM PST 24
Finished Jan 03 12:52:31 PM PST 24
Peak memory 300460 kb
Host smart-980454ac-dc10-415c-925a-d642cc896650
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058253296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.4058253296
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3205014698
Short name T463
Test name
Test status
Simulation time 2277857138 ps
CPU time 522.24 seconds
Started Jan 03 12:51:45 PM PST 24
Finished Jan 03 01:00:37 PM PST 24
Peak memory 371744 kb
Host smart-65112688-cbcb-42f2-9015-d6a44cff59dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205014698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.3205014698
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2057383829
Short name T851
Test name
Test status
Simulation time 36890109 ps
CPU time 0.62 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 202712 kb
Host smart-5995ef2b-7c39-4945-9ae2-d74e5b46e390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057383829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2057383829
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.1539211477
Short name T125
Test name
Test status
Simulation time 1458453840 ps
CPU time 33.15 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 12:52:54 PM PST 24
Peak memory 202864 kb
Host smart-5803f243-2dcd-4a94-91a5-05d2c867198e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539211477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
1539211477
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.1255682211
Short name T422
Test name
Test status
Simulation time 84328244137 ps
CPU time 978.18 seconds
Started Jan 03 12:51:41 PM PST 24
Finished Jan 03 01:08:10 PM PST 24
Peak memory 358168 kb
Host smart-7ade3235-d684-48c4-ab78-751957970a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255682211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.1255682211
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.1767700257
Short name T449
Test name
Test status
Simulation time 152526982 ps
CPU time 2.45 seconds
Started Jan 03 12:51:56 PM PST 24
Finished Jan 03 12:52:03 PM PST 24
Peak memory 202844 kb
Host smart-4e09b7fd-5ae0-4b22-9b8b-8d1694692ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767700257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.1767700257
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3543035812
Short name T574
Test name
Test status
Simulation time 64723689 ps
CPU time 7.16 seconds
Started Jan 03 12:51:51 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 235628 kb
Host smart-44964f9e-4061-47f4-951f-0000b3e7a3d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543035812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3543035812
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1702252283
Short name T541
Test name
Test status
Simulation time 165449915 ps
CPU time 2.81 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:51:39 PM PST 24
Peak memory 212316 kb
Host smart-f2213e09-520f-4152-91ca-73ce96b6d08f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702252283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1702252283
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.2486559714
Short name T601
Test name
Test status
Simulation time 559987698 ps
CPU time 5.43 seconds
Started Jan 03 12:51:49 PM PST 24
Finished Jan 03 12:52:02 PM PST 24
Peak memory 202900 kb
Host smart-e320efba-44f0-4a45-ace7-029469ec600f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486559714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.2486559714
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.4256970429
Short name T113
Test name
Test status
Simulation time 13390364525 ps
CPU time 856.43 seconds
Started Jan 03 12:51:40 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 374696 kb
Host smart-ec657e38-9fb1-4085-9a61-414223fb65c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256970429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.4256970429
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.3798767563
Short name T683
Test name
Test status
Simulation time 617719324 ps
CPU time 108.32 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:53:35 PM PST 24
Peak memory 355232 kb
Host smart-087a280c-bd1e-47b6-9888-3845347bffb5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798767563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.3798767563
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3604041687
Short name T451
Test name
Test status
Simulation time 25230062379 ps
CPU time 243.7 seconds
Started Jan 03 12:51:39 PM PST 24
Finished Jan 03 12:55:54 PM PST 24
Peak memory 203040 kb
Host smart-310efaac-36ed-4f25-abd3-a442f303d4fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604041687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.3604041687
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2383950132
Short name T578
Test name
Test status
Simulation time 30215731 ps
CPU time 1.09 seconds
Started Jan 03 12:51:23 PM PST 24
Finished Jan 03 12:51:39 PM PST 24
Peak memory 203096 kb
Host smart-ac76c0a6-a11b-4a39-a8b7-8dc62c8d58ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383950132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2383950132
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.192619728
Short name T482
Test name
Test status
Simulation time 10279741092 ps
CPU time 690.71 seconds
Started Jan 03 12:51:38 PM PST 24
Finished Jan 03 01:03:21 PM PST 24
Peak memory 370604 kb
Host smart-e13f59dc-ec06-42b8-bf05-b2817b6962d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192619728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.192619728
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.2703342506
Short name T218
Test name
Test status
Simulation time 718439535 ps
CPU time 11.04 seconds
Started Jan 03 12:51:54 PM PST 24
Finished Jan 03 12:52:11 PM PST 24
Peak memory 202748 kb
Host smart-94d31930-2647-4c35-8539-bc84e84d3a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703342506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2703342506
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.2897790236
Short name T731
Test name
Test status
Simulation time 266575848900 ps
CPU time 4266.98 seconds
Started Jan 03 12:51:42 PM PST 24
Finished Jan 03 02:03:00 PM PST 24
Peak memory 377876 kb
Host smart-885db6c9-fed8-4d2a-af60-2e502113ab5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897790236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.2897790236
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2744747308
Short name T722
Test name
Test status
Simulation time 276540300 ps
CPU time 55.16 seconds
Started Jan 03 12:51:26 PM PST 24
Finished Jan 03 12:52:35 PM PST 24
Peak memory 238400 kb
Host smart-7b49db05-9ba0-459b-aef0-7d127b4395d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2744747308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2744747308
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3975898630
Short name T933
Test name
Test status
Simulation time 10902118360 ps
CPU time 248.16 seconds
Started Jan 03 12:51:40 PM PST 24
Finished Jan 03 12:56:00 PM PST 24
Peak memory 203020 kb
Host smart-44dfbce3-606a-478a-94a0-6bed8723dc23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975898630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3975898630
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3198217221
Short name T506
Test name
Test status
Simulation time 440587101 ps
CPU time 43.71 seconds
Started Jan 03 12:51:39 PM PST 24
Finished Jan 03 12:52:34 PM PST 24
Peak memory 313588 kb
Host smart-9455ef3e-a018-42f2-a751-f69263b5a8bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198217221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3198217221
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.29946152
Short name T658
Test name
Test status
Simulation time 512011800 ps
CPU time 143.08 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:54:09 PM PST 24
Peak memory 347064 kb
Host smart-ecbad1d2-ceef-4ed7-885b-e7b2753155e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.sram_ctrl_access_during_key_req.29946152
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.1414461645
Short name T763
Test name
Test status
Simulation time 31543848 ps
CPU time 0.64 seconds
Started Jan 03 12:51:42 PM PST 24
Finished Jan 03 12:51:54 PM PST 24
Peak memory 202696 kb
Host smart-b8717302-b696-419d-9d70-bd1945ade6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414461645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.1414461645
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.637968566
Short name T349
Test name
Test status
Simulation time 1866515110 ps
CPU time 27.99 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:52:14 PM PST 24
Peak memory 202844 kb
Host smart-79de354a-eb37-456f-82e8-41237c4e71ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637968566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.637968566
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.690518417
Short name T274
Test name
Test status
Simulation time 42364580677 ps
CPU time 694.58 seconds
Started Jan 03 12:51:25 PM PST 24
Finished Jan 03 01:03:13 PM PST 24
Peak memory 373660 kb
Host smart-fb86f799-1a12-4a50-9c3d-4e011b37a9b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690518417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.690518417
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2160795458
Short name T5
Test name
Test status
Simulation time 514172298 ps
CPU time 6.34 seconds
Started Jan 03 12:51:47 PM PST 24
Finished Jan 03 12:52:02 PM PST 24
Peak memory 202840 kb
Host smart-d4e3885c-4251-40e2-8466-2a9d0ae55fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160795458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2160795458
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.3582488688
Short name T443
Test name
Test status
Simulation time 337769191 ps
CPU time 53.79 seconds
Started Jan 03 12:51:25 PM PST 24
Finished Jan 03 12:52:33 PM PST 24
Peak memory 327608 kb
Host smart-a5f36781-a2af-4a69-9f62-0d72c4ad5db6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582488688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.3582488688
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3154488533
Short name T84
Test name
Test status
Simulation time 189864425 ps
CPU time 2.84 seconds
Started Jan 03 12:51:45 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 216056 kb
Host smart-5e15d2b7-8676-4ff5-a726-ff400c134a35
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154488533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.3154488533
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.3103444157
Short name T423
Test name
Test status
Simulation time 673180008 ps
CPU time 9.95 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:52:04 PM PST 24
Peak memory 202860 kb
Host smart-9e928899-fdaf-4831-84cb-cd33bdb1aad3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103444157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.3103444157
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3811178444
Short name T438
Test name
Test status
Simulation time 2430029998 ps
CPU time 632.92 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 351224 kb
Host smart-681092a7-1bdb-43ca-b47a-721b05fb1a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811178444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3811178444
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.263517226
Short name T686
Test name
Test status
Simulation time 998117924 ps
CPU time 14.26 seconds
Started Jan 03 12:51:31 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 202900 kb
Host smart-126aba17-cfc3-4cad-a1ef-50932d10f3ae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263517226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.263517226
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2555781167
Short name T271
Test name
Test status
Simulation time 8659590079 ps
CPU time 310.42 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:56:58 PM PST 24
Peak memory 202988 kb
Host smart-4aefd357-ca9f-4260-8466-a7071d0fcba8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555781167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.2555781167
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1700319369
Short name T685
Test name
Test status
Simulation time 30646002 ps
CPU time 1.17 seconds
Started Jan 03 12:51:37 PM PST 24
Finished Jan 03 12:51:49 PM PST 24
Peak memory 203092 kb
Host smart-c630282e-6120-4ece-983b-4ecbbcca8d91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700319369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1700319369
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.831150437
Short name T445
Test name
Test status
Simulation time 13160737326 ps
CPU time 807.93 seconds
Started Jan 03 12:51:53 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 365556 kb
Host smart-8e7d7554-7d9e-42e4-a7b9-dcd87ec30b96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831150437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.831150437
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.3110754913
Short name T928
Test name
Test status
Simulation time 161325599 ps
CPU time 9.49 seconds
Started Jan 03 12:51:37 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 202884 kb
Host smart-2ec7e7c9-70e2-400a-b194-815704775e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110754913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3110754913
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.303641521
Short name T982
Test name
Test status
Simulation time 2268468944 ps
CPU time 1597.99 seconds
Started Jan 03 12:52:10 PM PST 24
Finished Jan 03 01:18:59 PM PST 24
Peak memory 419996 kb
Host smart-0b92607a-9901-4a88-b24f-f618f7494798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=303641521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.303641521
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3733616032
Short name T566
Test name
Test status
Simulation time 2229795470 ps
CPU time 202.04 seconds
Started Jan 03 12:51:38 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 202936 kb
Host smart-a4d2bf1b-b952-48d3-97b0-df1ce79b394e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733616032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3733616032
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1204693169
Short name T4
Test name
Test status
Simulation time 301027519 ps
CPU time 45.79 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 12:52:39 PM PST 24
Peak memory 309148 kb
Host smart-b1b0b814-d828-4bf0-8e19-7b2e0757ef24
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204693169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1204693169
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2066687694
Short name T266
Test name
Test status
Simulation time 16468584267 ps
CPU time 1661.7 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 01:20:00 PM PST 24
Peak memory 376744 kb
Host smart-bce2492d-0420-4d74-b584-eb9d0cb693ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066687694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2066687694
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.922506618
Short name T542
Test name
Test status
Simulation time 15459186 ps
CPU time 0.62 seconds
Started Jan 03 12:52:09 PM PST 24
Finished Jan 03 12:52:19 PM PST 24
Peak memory 202704 kb
Host smart-49a64267-1d43-4bf2-b735-7860a7d236a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922506618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.922506618
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.2534182655
Short name T986
Test name
Test status
Simulation time 8140800641 ps
CPU time 31.22 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:52:18 PM PST 24
Peak memory 202884 kb
Host smart-18388f48-a81a-413a-adc4-fa35cc0d57ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534182655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
2534182655
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.3710453044
Short name T220
Test name
Test status
Simulation time 36338096222 ps
CPU time 613.95 seconds
Started Jan 03 12:52:07 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 375392 kb
Host smart-47263c83-dce6-47a5-805a-cd9459c314b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710453044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.3710453044
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.217005659
Short name T643
Test name
Test status
Simulation time 496881325 ps
CPU time 6.63 seconds
Started Jan 03 12:52:00 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 213536 kb
Host smart-23f61a84-4e14-4c3d-8e4f-7afdb202530e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217005659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.217005659
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.4061014589
Short name T638
Test name
Test status
Simulation time 57731744 ps
CPU time 6.09 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:52:17 PM PST 24
Peak memory 234940 kb
Host smart-e7dd6383-0c3f-441d-a1cb-f04b518a4f50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061014589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.4061014589
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.439143892
Short name T247
Test name
Test status
Simulation time 457289480 ps
CPU time 3 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 211004 kb
Host smart-e288879b-ba39-47f4-acd3-e95f3eebae47
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439143892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.439143892
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.623159783
Short name T427
Test name
Test status
Simulation time 238895906 ps
CPU time 4.8 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 12:52:40 PM PST 24
Peak memory 202572 kb
Host smart-d84a0562-bfe5-4a35-86c5-36ec92ee8a93
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623159783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
mem_walk.623159783
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.200468374
Short name T793
Test name
Test status
Simulation time 43954627682 ps
CPU time 1659.38 seconds
Started Jan 03 12:51:43 PM PST 24
Finished Jan 03 01:19:33 PM PST 24
Peak memory 372680 kb
Host smart-e0bf3f63-2f52-4605-8f04-16df1ca3ffe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200468374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl
e_keys.200468374
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3775353300
Short name T697
Test name
Test status
Simulation time 903975906 ps
CPU time 40.21 seconds
Started Jan 03 12:51:50 PM PST 24
Finished Jan 03 12:52:37 PM PST 24
Peak memory 307480 kb
Host smart-6b054896-620f-4c22-a522-6f4b4ecce092
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775353300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3775353300
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1820084117
Short name T130
Test name
Test status
Simulation time 23592625816 ps
CPU time 411.36 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:58:39 PM PST 24
Peak memory 202912 kb
Host smart-620ae2b5-ef29-4cea-97b6-26646c3eaa93
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820084117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.1820084117
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3542879455
Short name T511
Test name
Test status
Simulation time 8029581540 ps
CPU time 191.18 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 371264 kb
Host smart-9e452622-1f59-46fc-b46a-2da10d516948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542879455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3542879455
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3068215173
Short name T245
Test name
Test status
Simulation time 188024366 ps
CPU time 11.22 seconds
Started Jan 03 12:51:33 PM PST 24
Finished Jan 03 12:51:55 PM PST 24
Peak memory 202744 kb
Host smart-cbfd0227-78d1-4dd2-a970-cc325debade4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068215173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3068215173
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.328164455
Short name T283
Test name
Test status
Simulation time 40986736677 ps
CPU time 2371.96 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:32:02 PM PST 24
Peak memory 374176 kb
Host smart-fbad3d21-0a34-44ee-9592-e54b1a460f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328164455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_stress_all.328164455
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2175093898
Short name T760
Test name
Test status
Simulation time 11046111371 ps
CPU time 3930.56 seconds
Started Jan 03 12:52:15 PM PST 24
Finished Jan 03 01:58:10 PM PST 24
Peak memory 403840 kb
Host smart-bfbf01da-8014-4567-b7b0-0e0d4c6e687d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2175093898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2175093898
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3564283464
Short name T759
Test name
Test status
Simulation time 3391938737 ps
CPU time 330.92 seconds
Started Jan 03 12:51:36 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 202992 kb
Host smart-d748cb02-20a6-437c-ba2c-62e68ab7fc3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564283464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.3564283464
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.433267040
Short name T522
Test name
Test status
Simulation time 74604540 ps
CPU time 1.94 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 211000 kb
Host smart-076626c9-181f-4be9-aa93-b0f506529e3c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433267040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.433267040
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1628944376
Short name T594
Test name
Test status
Simulation time 21606389 ps
CPU time 0.72 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:52:44 PM PST 24
Peak memory 202684 kb
Host smart-f0a48e5b-799f-4f56-8dc0-15ca81c1397c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628944376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1628944376
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.2444881663
Short name T716
Test name
Test status
Simulation time 4023946603 ps
CPU time 68.16 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 12:54:33 PM PST 24
Peak memory 202884 kb
Host smart-4196c0b5-1e87-411b-944e-6bc622c94aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444881663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
2444881663
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2025144509
Short name T622
Test name
Test status
Simulation time 1259053537 ps
CPU time 481.52 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 01:00:48 PM PST 24
Peak memory 372544 kb
Host smart-edd5626b-b2c4-494c-87f9-8c4def2ca4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025144509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2025144509
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.1865712435
Short name T960
Test name
Test status
Simulation time 1171666792 ps
CPU time 7.78 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:52:29 PM PST 24
Peak memory 211188 kb
Host smart-93056ef2-4ae2-4bc5-a146-9bff02962e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865712435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.1865712435
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2592058158
Short name T538
Test name
Test status
Simulation time 521933150 ps
CPU time 120.31 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:54:44 PM PST 24
Peak memory 371316 kb
Host smart-20fa4233-36a7-4c44-85a1-cd4c4964d0d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592058158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2592058158
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2212354777
Short name T621
Test name
Test status
Simulation time 286460272 ps
CPU time 4.65 seconds
Started Jan 03 12:52:12 PM PST 24
Finished Jan 03 12:52:38 PM PST 24
Peak memory 215876 kb
Host smart-3ff3d617-3754-4ec7-8ddf-e9fe00a4efc9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212354777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2212354777
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.4000459824
Short name T504
Test name
Test status
Simulation time 1296578422 ps
CPU time 10.29 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 12:52:45 PM PST 24
Peak memory 202904 kb
Host smart-01f7715d-af06-4546-a069-6fe35aa81b76
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000459824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.4000459824
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.4285538238
Short name T603
Test name
Test status
Simulation time 15784863003 ps
CPU time 1086.31 seconds
Started Jan 03 12:52:13 PM PST 24
Finished Jan 03 01:10:43 PM PST 24
Peak memory 375792 kb
Host smart-4d389c3b-2c95-4265-b683-98c535091c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285538238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.4285538238
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3558051565
Short name T112
Test name
Test status
Simulation time 1847457282 ps
CPU time 15.37 seconds
Started Jan 03 12:52:17 PM PST 24
Finished Jan 03 12:52:59 PM PST 24
Peak memory 202816 kb
Host smart-fe9f999c-e716-470f-988b-1a01d2b87306
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558051565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3558051565
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3419953409
Short name T439
Test name
Test status
Simulation time 16509478461 ps
CPU time 185.83 seconds
Started Jan 03 12:52:25 PM PST 24
Finished Jan 03 12:56:31 PM PST 24
Peak memory 203008 kb
Host smart-93a20cdb-ffbc-49d4-b847-a0aef5f4fb98
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419953409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.3419953409
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2839654511
Short name T613
Test name
Test status
Simulation time 33151384 ps
CPU time 0.82 seconds
Started Jan 03 12:52:27 PM PST 24
Finished Jan 03 12:53:26 PM PST 24
Peak memory 202768 kb
Host smart-2a85394f-8dee-418f-93b8-16990844a7ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839654511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2839654511
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1559221817
Short name T526
Test name
Test status
Simulation time 2718844955 ps
CPU time 445.46 seconds
Started Jan 03 12:52:19 PM PST 24
Finished Jan 03 01:00:12 PM PST 24
Peak memory 353668 kb
Host smart-d923571e-d13f-4d06-ac46-1beb4ada9c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559221817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1559221817
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1120409334
Short name T971
Test name
Test status
Simulation time 1907575097 ps
CPU time 55.44 seconds
Started Jan 03 12:51:59 PM PST 24
Finished Jan 03 12:52:58 PM PST 24
Peak memory 320360 kb
Host smart-b2385c13-afdf-40f8-9d16-9887a17c6ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120409334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1120409334
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3589887969
Short name T485
Test name
Test status
Simulation time 125672012967 ps
CPU time 1721.96 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 01:21:03 PM PST 24
Peak memory 372460 kb
Host smart-2da79754-b36d-47e6-b884-eddcec5e98d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589887969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3589887969
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.851762509
Short name T339
Test name
Test status
Simulation time 7983534576 ps
CPU time 212.39 seconds
Started Jan 03 12:52:14 PM PST 24
Finished Jan 03 12:56:11 PM PST 24
Peak memory 202936 kb
Host smart-f1571306-28a8-429e-a678-679338541eee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851762509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.851762509
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3830589175
Short name T636
Test name
Test status
Simulation time 301031129 ps
CPU time 85.67 seconds
Started Jan 03 12:52:24 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 363460 kb
Host smart-116e5788-90d7-4836-a561-aa753ae6613f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830589175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3830589175
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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