Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10581592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

47223451

1

T9

40

T18

20

T23

298

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28813889	1			T9	40		T18	20		T23	73
values[0x0]	13437137	1			T23	116		T26	19		T1	54033
values[0x1]	15554017	1			T23	109		T26	18		T1	58123

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5274118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52530925

1

T9

40

T18

20

T23

298

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	229188	1			T1	787		T2	37		T3	5
valid_sources[0x01]	222022	1			T1	874		T2	41		T3	10
valid_sources[0x02]	201693	1			T18	17		T1	855		T2	36
valid_sources[0x03]	195655	1			T1	932		T2	24		T3	13
valid_sources[0x04]	249451	1			T1	905		T2	23		T3	8
valid_sources[0x05]	199677	1			T1	879		T2	26		T3	5
valid_sources[0x06]	251784	1			T1	841		T2	39		T3	13
valid_sources[0x07]	254643	1			T1	961		T2	26		T3	10
valid_sources[0x08]	291719	1			T1	830		T2	31		T3	12
valid_sources[0x09]	213993	1			T1	919		T2	29		T3	19
valid_sources[0x0a]	260459	1			T1	847		T2	30		T3	12
valid_sources[0x0b]	211253	1			T9	1		T1	904		T2	27
valid_sources[0x0c]	243937	1			T1	908		T2	22		T3	13
valid_sources[0x0d]	256257	1			T1	826		T2	39		T3	14
valid_sources[0x0e]	267508	1			T9	3		T1	794		T2	28
valid_sources[0x0f]	206233	1			T1	837		T2	24		T3	12
valid_sources[0x10]	214187	1			T1	822		T2	20		T3	16
valid_sources[0x11]	217359	1			T1	858		T2	30		T3	15
valid_sources[0x12]	196066	1			T1	826		T2	27		T3	7
valid_sources[0x13]	200191	1			T9	1		T1	901		T2	21
valid_sources[0x14]	275683	1			T1	855		T2	18		T3	11
valid_sources[0x15]	216457	1			T26	1		T1	922		T2	32
valid_sources[0x16]	330381	1			T1	857		T2	33		T3	14
valid_sources[0x17]	251994	1			T26	1		T1	896		T2	36
valid_sources[0x18]	211523	1			T1	928		T2	30		T3	11
valid_sources[0x19]	201287	1			T1	862		T2	34		T3	12
valid_sources[0x1a]	257948	1			T1	872		T2	35		T3	9
valid_sources[0x1b]	209732	1			T1	917		T2	34		T3	10
valid_sources[0x1c]	211513	1			T1	896		T2	21		T3	6
valid_sources[0x1d]	237465	1			T1	859		T2	25		T3	21
valid_sources[0x1e]	296049	1			T1	858		T2	19		T3	7
valid_sources[0x1f]	235085	1			T1	906		T2	33		T3	10
valid_sources[0x20]	267509	1			T9	3		T1	895		T2	30
valid_sources[0x21]	209424	1			T1	876		T2	34		T3	18
valid_sources[0x22]	235103	1			T9	3		T1	894		T2	16
valid_sources[0x23]	203638	1			T26	2		T1	817		T2	29
valid_sources[0x24]	200959	1			T1	887		T2	26		T3	7
valid_sources[0x25]	200929	1			T1	839		T2	31		T3	8
valid_sources[0x26]	193700	1			T1	822		T2	43		T3	13
valid_sources[0x27]	216284	1			T1	891		T2	21		T3	14
valid_sources[0x28]	215136	1			T1	856		T2	39		T3	11
valid_sources[0x29]	191897	1			T9	1		T1	824		T2	27
valid_sources[0x2a]	207170	1			T1	853		T2	29		T3	6
valid_sources[0x2b]	193803	1			T1	897		T2	23		T3	14
valid_sources[0x2c]	196485	1			T1	817		T2	36		T3	10
valid_sources[0x2d]	263175	1			T9	1		T26	2		T1	866
valid_sources[0x2e]	223335	1			T26	1		T1	894		T2	20
valid_sources[0x2f]	233730	1			T1	857		T2	35		T3	19
valid_sources[0x30]	197352	1			T1	883		T2	32		T3	20
valid_sources[0x31]	262586	1			T1	919		T2	25		T3	13
valid_sources[0x32]	231992	1			T1	851		T2	25		T3	14
valid_sources[0x33]	203277	1			T26	1		T1	889		T2	26
valid_sources[0x34]	192658	1			T9	1		T1	806		T2	28
valid_sources[0x35]	201786	1			T26	1		T1	814		T2	31
valid_sources[0x36]	206415	1			T1	837		T2	28		T3	12
valid_sources[0x37]	220639	1			T26	1		T1	850		T2	28
valid_sources[0x38]	255583	1			T9	1		T1	827		T2	26
valid_sources[0x39]	263769	1			T1	819		T2	28		T3	15
valid_sources[0x3a]	203563	1			T1	884		T2	33		T3	8
valid_sources[0x3b]	204794	1			T26	2		T1	864		T2	25
valid_sources[0x3c]	269274	1			T1	835		T2	29		T3	10
valid_sources[0x3d]	219668	1			T1	857		T2	28		T3	10
valid_sources[0x3e]	268364	1			T1	932		T2	28		T3	10
valid_sources[0x3f]	199839	1			T26	1		T1	905		T2	38
valid_sources[0x40]	245191	1			T9	1		T26	1		T1	926
valid_sources[0x41]	362889	1			T1	888		T2	27		T3	5
valid_sources[0x42]	226684	1			T26	2		T1	805		T2	31
valid_sources[0x43]	244650	1			T1	805		T2	36		T3	12
valid_sources[0x44]	207401	1			T1	823		T2	19		T3	9
valid_sources[0x45]	251189	1			T1	967		T2	37		T3	20
valid_sources[0x46]	250482	1			T1	893		T2	30		T3	15
valid_sources[0x47]	218797	1			T1	869		T2	19		T3	14
valid_sources[0x48]	220103	1			T1	851		T2	30		T3	7
valid_sources[0x49]	261331	1			T1	841		T2	19		T3	10
valid_sources[0x4a]	219381	1			T1	894		T2	28		T3	10
valid_sources[0x4b]	219475	1			T1	837		T2	25		T3	14
valid_sources[0x4c]	233848	1			T26	1		T1	857		T2	26
valid_sources[0x4d]	218122	1			T1	892		T2	25		T3	20
valid_sources[0x4e]	288421	1			T1	919		T2	36		T3	12
valid_sources[0x4f]	201479	1			T1	874		T2	30		T3	9
valid_sources[0x50]	223083	1			T26	1		T1	882		T2	25
valid_sources[0x51]	197033	1			T1	857		T2	32		T3	7
valid_sources[0x52]	226860	1			T1	866		T2	42		T3	8
valid_sources[0x53]	197464	1			T1	859		T2	34		T3	17
valid_sources[0x54]	240563	1			T1	817		T2	21		T3	12
valid_sources[0x55]	215564	1			T1	867		T2	41		T3	13
valid_sources[0x56]	192800	1			T9	3		T1	870		T2	26
valid_sources[0x57]	208887	1			T1	816		T2	32		T3	4
valid_sources[0x58]	201724	1			T1	926		T2	25		T3	12
valid_sources[0x59]	217587	1			T1	861		T2	25		T3	15
valid_sources[0x5a]	202712	1			T1	869		T2	32		T3	7
valid_sources[0x5b]	213314	1			T1	879		T2	32		T3	12
valid_sources[0x5c]	251998	1			T1	899		T2	31		T3	7
valid_sources[0x5d]	209295	1			T1	879		T2	32		T3	11
valid_sources[0x5e]	207611	1			T1	851		T2	25		T3	12
valid_sources[0x5f]	267429	1			T1	832		T2	40		T3	13
valid_sources[0x60]	202447	1			T1	917		T2	23		T3	16
valid_sources[0x61]	236113	1			T1	912		T2	26		T3	13
valid_sources[0x62]	219374	1			T26	1		T1	851		T2	29
valid_sources[0x63]	211498	1			T1	932		T2	20		T3	8
valid_sources[0x64]	212184	1			T1	835		T2	31		T3	10
valid_sources[0x65]	247023	1			T1	942		T2	27		T3	11
valid_sources[0x66]	198895	1			T26	1		T1	857		T2	17
valid_sources[0x67]	228671	1			T26	2		T1	845		T2	31
valid_sources[0x68]	199595	1			T26	1		T1	902		T2	23
valid_sources[0x69]	238058	1			T1	879		T2	36		T3	19
valid_sources[0x6a]	283067	1			T1	928		T2	36		T3	6
valid_sources[0x6b]	206336	1			T26	1		T1	883		T2	29
valid_sources[0x6c]	249817	1			T1	855		T2	25		T3	18
valid_sources[0x6d]	259590	1			T1	881		T2	32		T3	10
valid_sources[0x6e]	264812	1			T26	1		T1	913		T2	43
valid_sources[0x6f]	197847	1			T1	861		T2	20		T3	26
valid_sources[0x70]	250672	1			T1	865		T2	37		T3	14
valid_sources[0x71]	201442	1			T1	863		T2	27		T3	14
valid_sources[0x72]	223750	1			T9	1		T1	894		T2	20
valid_sources[0x73]	202458	1			T1	881		T2	23		T3	12
valid_sources[0x74]	192514	1			T1	802		T2	18		T3	11
valid_sources[0x75]	222784	1			T1	888		T2	27		T3	16
valid_sources[0x76]	193831	1			T1	916		T2	22		T3	12
valid_sources[0x77]	219706	1			T1	897		T2	31		T3	13
valid_sources[0x78]	216268	1			T1	860		T2	24		T3	13
valid_sources[0x79]	220861	1			T1	916		T2	26		T3	9
valid_sources[0x7a]	195202	1			T26	1		T1	902		T2	28
valid_sources[0x7b]	202777	1			T1	863		T2	30		T3	13
valid_sources[0x7c]	205271	1			T9	1		T1	910		T2	22
valid_sources[0x7d]	231843	1			T1	864		T2	21		T3	12
valid_sources[0x7e]	249058	1			T1	892		T2	15		T3	16
valid_sources[0x7f]	286745	1			T1	901		T2	35		T3	7
valid_sources[0x80]	214273	1			T1	848		T2	30		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23526858

1

T9

40

T18

20

T23

73

values[0x0]

all_enables

biggest_size

11848283

1

T23

116

T26

19

T1

50971

values[0x1]

all_enables

biggest_size

11848310

1

T23

109

T26

18

T1

50910

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1867327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

106534

1

T9

51

T18

29

T19

97

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1880378	1			T9	2669		T18	5789		T19	53
values[0x0]	45469	1			T9	60		T18	29		T19	27
values[0x1]	48014	1			T9	57		T18	31		T19	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1248221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

725640

1

T9

940

T18

1961

T19

97

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5506	1			T9	16		T18	32		T20	2
valid_sources[0x01]	6438	1			T9	13		T18	28		T20	1
valid_sources[0x02]	5343	1			T9	14		T18	15		T20	3
valid_sources[0x03]	6756	1			T9	8		T18	22		T20	5
valid_sources[0x04]	5370	1			T9	15		T18	21		T20	8
valid_sources[0x05]	5305	1			T9	8		T18	20		T20	5
valid_sources[0x06]	5481	1			T9	11		T18	7		T20	5
valid_sources[0x07]	6239	1			T9	9		T18	18		T20	1
valid_sources[0x08]	6039	1			T9	8		T18	17		T20	7
valid_sources[0x09]	5824	1			T9	11		T18	9		T20	3
valid_sources[0x0a]	5322	1			T9	12		T18	13		T20	4
valid_sources[0x0b]	5299	1			T9	10		T18	21		T20	6
valid_sources[0x0c]	5773	1			T9	7		T18	30		T20	9
valid_sources[0x0d]	5588	1			T9	7		T18	65		T20	7
valid_sources[0x0e]	6274	1			T9	8		T18	24		T20	1
valid_sources[0x0f]	6092	1			T9	14		T18	16		T20	8
valid_sources[0x10]	5467	1			T9	10		T18	18		T20	5
valid_sources[0x11]	11812	1			T9	14		T18	21		T20	4
valid_sources[0x12]	5672	1			T9	9		T18	16		T20	3
valid_sources[0x13]	43646	1			T9	16		T18	24		T20	2
valid_sources[0x14]	5557	1			T9	7		T18	10		T20	9
valid_sources[0x15]	6481	1			T9	12		T18	14		T20	6
valid_sources[0x16]	5346	1			T9	11		T18	19		T20	3
valid_sources[0x17]	5556	1			T9	18		T18	34		T20	7
valid_sources[0x18]	5713	1			T9	7		T18	13		T20	3
valid_sources[0x19]	6724	1			T9	6		T18	11		T20	4
valid_sources[0x1a]	6486	1			T9	15		T18	17		T20	4
valid_sources[0x1b]	5645	1			T9	9		T18	28		T20	2
valid_sources[0x1c]	5521	1			T9	12		T18	18		T20	7
valid_sources[0x1d]	5448	1			T9	12		T18	16		T20	10
valid_sources[0x1e]	5726	1			T9	15		T18	20		T20	6
valid_sources[0x1f]	5282	1			T9	9		T18	14		T20	7
valid_sources[0x20]	5323	1			T9	5		T18	35		T20	7
valid_sources[0x21]	6533	1			T9	5		T18	24		T20	6
valid_sources[0x22]	6684	1			T9	8		T18	34		T20	3
valid_sources[0x23]	5916	1			T9	13		T18	27		T20	6
valid_sources[0x24]	5571	1			T9	6		T18	20		T20	5
valid_sources[0x25]	6434	1			T9	7		T18	14		T19	2
valid_sources[0x26]	6418	1			T9	16		T18	1		T20	5
valid_sources[0x27]	5296	1			T9	17		T18	15		T20	8
valid_sources[0x28]	7119	1			T9	7		T18	28		T20	5
valid_sources[0x29]	6272	1			T9	11		T18	53		T20	10
valid_sources[0x2a]	5830	1			T9	8		T18	13		T20	6
valid_sources[0x2b]	5515	1			T9	8		T18	11		T20	7
valid_sources[0x2c]	15838	1			T9	10		T18	28		T20	2
valid_sources[0x2d]	6816	1			T9	11		T18	11		T20	5
valid_sources[0x2e]	5972	1			T9	17		T18	19		T20	8
valid_sources[0x2f]	18499	1			T9	8		T18	26		T20	6
valid_sources[0x30]	6514	1			T9	10		T18	20		T20	7
valid_sources[0x31]	6384	1			T9	7		T18	23		T24	2
valid_sources[0x32]	5418	1			T9	5		T18	27		T20	2
valid_sources[0x33]	6858	1			T9	3		T18	26		T20	4
valid_sources[0x34]	14983	1			T9	13		T18	20		T20	4
valid_sources[0x35]	5506	1			T9	8		T18	36		T20	3
valid_sources[0x36]	5579	1			T9	15		T18	25		T20	4
valid_sources[0x37]	5694	1			T9	10		T18	15		T24	6
valid_sources[0x38]	6254	1			T9	8		T18	12		T20	3
valid_sources[0x39]	5337	1			T9	11		T18	19		T20	7
valid_sources[0x3a]	6625	1			T9	15		T18	14		T20	8
valid_sources[0x3b]	8939	1			T9	12		T18	22		T20	8
valid_sources[0x3c]	8239	1			T9	16		T18	18		T20	3
valid_sources[0x3d]	5619	1			T9	16		T18	26		T20	3
valid_sources[0x3e]	23271	1			T9	12		T18	31		T19	6
valid_sources[0x3f]	5503	1			T9	19		T18	21		T20	9
valid_sources[0x40]	8436	1			T9	10		T18	7		T19	1
valid_sources[0x41]	6221	1			T9	6		T18	17		T20	2
valid_sources[0x42]	8184	1			T9	5		T18	30		T24	7
valid_sources[0x43]	5800	1			T9	14		T18	22		T20	5
valid_sources[0x44]	5784	1			T9	11		T18	27		T20	5
valid_sources[0x45]	6809	1			T9	6		T18	18		T20	5
valid_sources[0x46]	13879	1			T9	8		T18	37		T20	4
valid_sources[0x47]	7055	1			T9	12		T18	38		T20	5
valid_sources[0x48]	5457	1			T9	13		T18	31		T20	6
valid_sources[0x49]	7700	1			T9	10		T18	27		T20	3
valid_sources[0x4a]	5219	1			T9	9		T18	9		T20	5
valid_sources[0x4b]	5433	1			T9	7		T18	36		T20	5
valid_sources[0x4c]	5456	1			T9	13		T18	23		T20	2
valid_sources[0x4d]	6701	1			T9	17		T18	11		T20	11
valid_sources[0x4e]	6164	1			T9	8		T18	32		T20	4
valid_sources[0x4f]	5624	1			T9	13		T18	23		T20	6
valid_sources[0x50]	13359	1			T9	12		T18	19		T20	3
valid_sources[0x51]	15409	1			T9	8		T18	11		T20	7
valid_sources[0x52]	5162	1			T9	4		T18	19		T20	2
valid_sources[0x53]	5848	1			T9	8		T18	12		T20	5
valid_sources[0x54]	15450	1			T9	6		T18	31		T20	5
valid_sources[0x55]	6669	1			T9	7		T18	25		T20	1
valid_sources[0x56]	72301	1			T9	17		T18	19		T20	14
valid_sources[0x57]	7621	1			T9	9		T18	22		T20	4
valid_sources[0x58]	5359	1			T9	18		T18	22		T20	5
valid_sources[0x59]	5887	1			T9	6		T18	28		T20	4
valid_sources[0x5a]	5128	1			T9	13		T18	33		T20	2
valid_sources[0x5b]	6392	1			T9	10		T18	24		T20	2
valid_sources[0x5c]	5807	1			T9	17		T18	16		T20	5
valid_sources[0x5d]	14003	1			T9	7		T18	15		T20	11
valid_sources[0x5e]	14304	1			T9	14		T18	15		T20	6
valid_sources[0x5f]	5509	1			T9	12		T18	20		T20	9
valid_sources[0x60]	8206	1			T9	11		T18	29		T20	4
valid_sources[0x61]	15548	1			T9	12		T18	33		T20	6
valid_sources[0x62]	5675	1			T9	6		T18	12		T20	2
valid_sources[0x63]	7185	1			T9	14		T18	39		T20	7
valid_sources[0x64]	5398	1			T9	13		T18	13		T20	1
valid_sources[0x65]	6263	1			T9	13		T18	20		T20	3
valid_sources[0x66]	5715	1			T9	12		T18	34		T20	8
valid_sources[0x67]	6415	1			T9	11		T18	17		T20	3
valid_sources[0x68]	5609	1			T9	12		T18	19		T20	7
valid_sources[0x69]	6437	1			T9	14		T18	9		T20	8
valid_sources[0x6a]	5974	1			T9	14		T18	24		T19	21
valid_sources[0x6b]	9683	1			T9	10		T18	44		T20	5
valid_sources[0x6c]	6007	1			T9	14		T18	20		T20	5
valid_sources[0x6d]	12694	1			T9	8		T18	36		T20	5
valid_sources[0x6e]	6448	1			T9	16		T18	32		T20	6
valid_sources[0x6f]	8486	1			T9	16		T18	16		T20	4
valid_sources[0x70]	5857	1			T9	5		T18	7		T20	5
valid_sources[0x71]	6175	1			T9	11		T18	20		T20	3
valid_sources[0x72]	5638	1			T9	9		T18	29		T20	4
valid_sources[0x73]	5321	1			T9	5		T18	15		T20	5
valid_sources[0x74]	11793	1			T9	17		T18	12		T20	7
valid_sources[0x75]	5494	1			T9	12		T18	9		T20	3
valid_sources[0x76]	31091	1			T9	13		T18	29		T20	6
valid_sources[0x77]	5524	1			T9	17		T18	16		T20	5
valid_sources[0x78]	6180	1			T9	14		T18	34		T20	6
valid_sources[0x79]	5902	1			T9	9		T18	23		T20	2
valid_sources[0x7a]	5857	1			T9	13		T18	11		T19	3
valid_sources[0x7b]	5295	1			T9	17		T18	25		T20	7
valid_sources[0x7c]	5213	1			T9	5		T18	32		T19	4
valid_sources[0x7d]	7525	1			T9	5		T18	30		T20	5
valid_sources[0x7e]	8523	1			T9	7		T18	6		T19	11
valid_sources[0x7f]	5088	1			T9	16		T18	35		T20	4
valid_sources[0x80]	8502	1			T9	11		T18	23		T20	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29355

1

T9

21

T18

13

T19

53

values[0x0]

all_enables

biggest_size

39374

1

T9

16

T18

11

T19

27

values[0x1]

all_enables

biggest_size

37805

1

T9

14

T18

5

T19

17