Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

10356435

1

T23

425

T26

70

T1

16315

full_word

43389458

1

T9

40

T18

20

T23

352

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	53745683	1			T9	40		T18	20		T23	777
auto[TlIntgErrCmd]	68	1			T93	4		T94	4		T95	1
auto[TlIntgErrData]	72	1			T93	3		T94	5		T95	5
auto[TlIntgErrBoth]	70	1			T93	3		T94	1		T95	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24695523

1

T9

40

T18

20

T23

177

auto[1]

29050370

1

T23

600

T26

90

T1

112156

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4941665	1			T23	93		T26	20		T1	6040
auto[TlIntgErrNone]	partial	auto[1]	5414579	1			T23	332		T26	50		T1	10275
auto[TlIntgErrNone]	full_word	auto[0]	19753770	1			T9	40		T18	20		T23	84
auto[TlIntgErrNone]	full_word	auto[1]	23635669	1			T23	268		T26	40		T1	101881
auto[TlIntgErrCmd]	partial	auto[0]	24	1			T94	2		T104	1		T105	1
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T93	4		T94	2		T95	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T104	1		T105	1		T106	1
auto[TlIntgErrData]	partial	auto[0]	29	1			T95	1		T104	6		T105	2
auto[TlIntgErrData]	partial	auto[1]	35	1			T93	3		T94	4		T95	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T94	1		T107	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T95	2		T106	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T95	1		T104	2		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	35	1			T94	1		T95	3		T104	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T93	1		T107	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T93	2		T110	1		T111	1