Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	339576	1			T1	2780		T12	672		T15	263
auto[1]	8439994	1			T1	684		T2	3652		T3	8
auto[2]	280448	1			T1	2506		T12	438		T15	188
auto[3]	8391863	1			T1	411		T2	3568		T3	10

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11331132	1			T1	4985		T2	7220		T3	15
auto[1]	1686218	1			T1	714		T3	1		T4	36
auto[2]	1688716	1			T1	607		T3	2		T4	43
auto[3]	2745815	1			T1	75		T4	6		T11	55

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6583486

1

T1

6375

T2

7215

T3

18

auto[1]

10868395

1

T1

6

T2

5

T11

13

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	192760	1			T1	2293		T12	559		T117	1218
auto[0]	auto[0]	auto[1]	19646	1			T1	241		T12	51		T117	107
auto[0]	auto[0]	auto[2]	19300	1			T1	230		T12	57		T15	2
auto[0]	auto[0]	auto[3]	4812	1			T1	14		T12	5		T15	260
auto[0]	auto[1]	auto[0]	2513539	1			T1	376		T2	3648		T3	7
auto[0]	auto[1]	auto[1]	265047	1			T1	238		T4	27		T11	248
auto[0]	auto[1]	auto[2]	254737	1			T1	46		T3	1		T4	15
auto[0]	auto[1]	auto[3]	56559	1			T1	23		T4	2		T11	29
auto[0]	auto[2]	auto[0]	160434	1			T1	2111		T12	341		T15	1
auto[0]	auto[2]	auto[1]	16357	1			T1	213		T12	40		T15	20
auto[0]	auto[2]	auto[2]	16670	1			T1	162		T12	53		T117	104
auto[0]	auto[2]	auto[3]	3974	1			T1	17		T12	4		T15	166
auto[0]	auto[3]	auto[0]	2484456	1			T1	200		T2	3567		T3	8
auto[0]	auto[3]	auto[1]	251975	1			T1	22		T3	1		T4	9
auto[0]	auto[3]	auto[2]	263899	1			T1	169		T3	1		T4	28
auto[0]	auto[3]	auto[3]	59321	1			T1	20		T4	4		T11	25
auto[1]	auto[0]	auto[0]	3569	1			T1	1		T62	846		T117	1
auto[1]	auto[0]	auto[1]	15432	1			T62	3802		T57	1		T101	1
auto[1]	auto[0]	auto[2]	15260	1			T62	3880		T118	1		T101	2
auto[1]	auto[0]	auto[3]	68797	1			T1	1		T15	1		T62	16967
auto[1]	auto[1]	auto[0]	2986728	1			T1	1		T2	4		T11	3
auto[1]	auto[1]	auto[1]	551188	1			T11	1		T13	1		T17	5716
auto[1]	auto[1]	auto[2]	557083	1			T11	2		T17	6380		T84	1
auto[1]	auto[1]	auto[3]	1255113	1			T17	536		T60	1		T62	17379
auto[1]	auto[2]	auto[0]	2898	1			T1	3		T62	805		T57	6
auto[1]	auto[2]	auto[1]	12745	1			T62	3579		T57	1		T119	1
auto[1]	auto[2]	auto[2]	12090	1			T62	2589		T57	1		T120	1
auto[1]	auto[2]	auto[3]	55280	1			T15	1		T62	11742		T116	1
auto[1]	auto[3]	auto[0]	2986748	1			T2	1		T11	5		T13	3
auto[1]	auto[3]	auto[1]	553828	1			T13	1		T16	1		T17	6407
auto[1]	auto[3]	auto[2]	549677	1			T11	1		T13	1		T16	1
auto[1]	auto[3]	auto[3]	1241959	1			T11	1		T13	1		T17	559