Unified Coverage Report :: Module :: sram_ctrl_regs_reg_top

Module : sram_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.91	100.00	99.55	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_init	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00	100.00			100.00
u_ctrl_renew_scr_key	100.00	100.00	100.00			100.00
u_exec	100.00	100.00	100.00			100.00
u_exec_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00	100.00			100.00
u_status_escalated	100.00	100.00	100.00			100.00
u_status_init_done	100.00	100.00	100.00			100.00
u_status_init_error	100.00	100.00	100.00			100.00
u_status_scr_key_seed_valid	100.00	100.00	100.00			100.00
u_status_scr_key_valid	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
ALWAYS	495	7	7	100.00
CONT_ASSIGN	504	1	1	100.00
ALWAYS	508	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
ALWAYS	538	7	7	100.00
ALWAYS	549	14	14	100.00
CONT_ASSIGN	592	0	0
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
152	1	1
166	1	1
364	1	1
434	1	1
461	1	1
489	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
504	1	1
508	1	1
518	1	1
520	1	1
521	1	1
523	1	1
524	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534	1	1
538	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
544	1	1
549	1	1
550	1	1
552	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
565	1	1
569	1	1
573	1	1
577	1	1
578	1	1
592		unreachable
600	1	1
601	1	1

---

Cond Coverage for Module : sram_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	87	87	100.00
Logical	87	87	100.00
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T19
1	0	Covered	T40,T41,T51
1	1	Covered	T9,T18,T19

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T9,T18,T19
0	1	Covered	T8,T33,T34
1	0	Covered	T93,T94,T95

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T9,T18,T19
0	0	1	Covered	T8,T33,T34
0	1	0	Covered	T93,T94,T95
1	0	0	Covered	T8,T33,T34

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T9,T18,T19
0	0	1	Covered	T93,T94,T95
0	1	0	Covered	T40,T41,T51
1	0	0	Covered	T40,T41,T51

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T9,T18,T19
1	1	Covered	T40,T41,T51

 LINE       364
 EXPRESSION (exec_we & exec_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T19
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T19

 LINE       434
 EXPRESSION (ctrl_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T19
1	0	Covered	T11,T13,T16
1	1	Covered	T9,T18,T21

 LINE       496
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       497
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       498
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       499
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       500
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       501
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       504
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T9,T18,T19
1	Covered	T9,T18,T19

 LINE       504
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T9,T18,T19
0	1	Covered	T9,T18,T19
1	0	Covered	T9,T18,T19

 LINE       508
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T40,T41,T51

 LINE       508
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T9,T18,T19
0	0	0	0	0	1	Covered	T9,T22,T23
0	0	0	0	1	0	Covered	T9,T18,T20
0	0	0	1	0	0	Covered	T9,T18,T20
0	0	1	0	0	0	Covered	T9,T18,T20
0	1	0	0	0	0	Covered	T9,T18,T20
1	0	0	0	0	0	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T18,T20

 LINE       508
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T9,T18,T20
1	0	Covered	T9,T18,T19
1	1	Covered	T9,T22,T23

 LINE       518
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T18,T19
1	0	1	Covered	T9,T18,T19
1	1	0	Covered	T40,T41,T51
1	1	1	Covered	T9,T18,T19

 LINE       521
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T18,T19
1	0	1	Covered	T9,T18,T19
1	1	0	Covered	T40,T41,T52
1	1	1	Covered	T9,T18,T19

 LINE       524
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T18,T19
1	0	1	Covered	T9,T18,T19
1	1	0	Covered	T40,T41,T51
1	1	1	Covered	T9,T18,T19

 LINE       527
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T18,T19
1	0	1	Covered	T9,T18,T19
1	1	0	Covered	T40,T41,T51
1	1	1	Covered	T9,T18,T19

 LINE       530
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T18,T19
1	0	1	Covered	T9,T18,T19
1	1	0	Covered	T40,T41,T52
1	1	1	Covered	T9,T18,T21

---

Branch Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	504	2	2	100.00
IF	71	3	3	100.00
CASE	550	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	504	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T18,T19
0	Covered	T9,T18,T19

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T18,T19
0	1	Covered	T8,T33,T34
0	0	Covered	T9,T18,T19

	LineNo.	Expression
-1-:	550	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T9,T18,T19
addr_hit[1]	Covered	T9,T18,T19
addr_hit[2]	Covered	T9,T18,T19
addr_hit[3]	Covered	T9,T18,T19
addr_hit[4]	Covered	T9,T18,T19
addr_hit[5]	Covered	T9,T18,T19
default	Covered	T9,T18,T19

---

Assert Coverage for Module : sram_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	253785985	1876905	0	0
reAfterRv	253785985	1876890	0	0
rePulse	253785985	1856064	0	0
wePulse	253785985	20826	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	1876905	0	0
T1	0	2226	0	0
T9	48412	2786	0	0
T18	19875	5849	0	0
T19	2080	97	0	0
T20	14663	1279	0	0
T21	929	12	0	0
T22	1616	12	0	0
T23	5495	0	0	0
T24	14662	1280	0	0
T25	1562	52	0	0
T26	3862	240	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	1876890	0	0
T1	0	2226	0	0
T9	48412	2786	0	0
T18	19875	5849	0	0
T19	2080	97	0	0
T20	14663	1279	0	0
T21	929	12	0	0
T22	1616	12	0	0
T23	5495	0	0	0
T24	14662	1280	0	0
T25	1562	52	0	0
T26	3862	240	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	1856064	0	0
T1	0	2198	0	0
T9	48412	2669	0	0
T18	19875	5789	0	0
T19	2080	53	0	0
T20	14663	640	0	0
T21	929	6	0	0
T22	1616	6	0	0
T23	5495	0	0	0
T24	14662	640	0	0
T25	1562	31	0	0
T26	3862	237	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	20826	0	0
T1	0	28	0	0
T9	48412	117	0	0
T18	19875	60	0	0
T19	2080	44	0	0
T20	14663	639	0	0
T21	929	6	0	0
T22	1616	6	0	0
T23	5495	0	0	0
T24	14662	640	0	0
T25	1562	21	0	0
T26	3862	3	0	0