Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	253785985	125542	0	0
ctrl_regwen_rd_A	253785985	7522	0	0
exec_rd_A	253785985	6722	0	0
exec_regwen_rd_A	253785985	7322	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	125542	0	0
T23	5495	174	0	0
T24	14662	0	0	0
T25	1562	0	0	0
T26	3862	21	0	0
T37	0	1373	0	0
T40	192174	4743	0	0
T41	50556	2792	0	0
T49	169473	0	0	0
T50	0	2205	0	0
T51	0	1970	0	0
T52	0	2117	0	0
T53	0	1821	0	0
T54	0	1931	0	0
T56	626230	0	0	0
T57	148914	0	0	0
T58	384787	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	7522	0	0
T9	48412	40	0	0
T18	19875	0	0	0
T19	2080	0	0	0
T20	14663	387	0	0
T21	929	5	0	0
T22	1616	6	0	0
T23	5495	0	0	0
T24	14662	416	0	0
T25	1562	43	0	0
T26	3862	0	0	0
T50	0	467	0	0
T52	0	665	0	0
T96	0	700	0	0
T97	0	457	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	6722	0	0
T9	48412	38	0	0
T18	19875	0	0	0
T19	2080	0	0	0
T20	14663	498	0	0
T21	929	4	0	0
T22	1616	0	0	0
T23	5495	0	0	0
T24	14662	484	0	0
T25	1562	24	0	0
T26	3862	0	0	0
T50	0	408	0	0
T52	0	508	0	0
T96	0	532	0	0
T97	0	586	0	0
T98	0	378	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253785985	7322	0	0
T9	48412	44	0	0
T18	19875	0	0	0
T19	2080	0	0	0
T20	14663	474	0	0
T21	929	8	0	0
T22	1616	0	0	0
T23	5495	0	0	0
T24	14662	431	0	0
T25	1562	0	0	0
T26	3862	0	0	0
T50	0	472	0	0
T52	0	500	0	0
T96	0	586	0	0
T97	0	538	0	0
T98	0	379	0	0
T99	0	166	0	0