Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145671014	1			T1	2038		T2	24576		T3	115047
instr_valid_dis	112715809	1			T1	2038		T2	24576		T3	719520
instr_en	23452370	1			T3	12392		T5	64050		T14	6087

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10171066	1			T3	116494		T5	28362		T14	6087
sram_ifetch_valid_disable	114718017	1			T1	2038		T2	24576		T3	900258
sram_ifetch_enable	20781931	1			T3	133724		T5	16130		T22	102194

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145671014	1			T1	2038		T2	24576		T3	115047
hw_debug_en_valid_off	114343950	1			T1	2038		T2	24576		T3	793064
hw_debug_en_on	22096359	1			T3	283720		T5	35420		T22	97454

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114718017	1			T1	2038		T2	24576		T3	900258
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100485398	1			T1	2038		T2	24576		T3	611516
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10199599	1			T5	61346		T22	50288		T117	181468
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3805580	1			T3	2396		T5	28362		T14	6087
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1607956	1			T3	2396		T5	28362		T117	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1428670	1			T14	6087		T116	13194		T129	19496
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4567525	1			T3	71752		T22	49610		T117	22364
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1911129	1			T3	13682		T117	22364		T116	32342
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1636572	1			T22	49610		T116	37688		T121	1384
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8873392	1			T3	120042		T5	19290		T22	10626
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3371609	1			T3	62324		T5	19290		T117	14284
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3814512	1			T22	10580		T117	139094		T115	80578

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9299239	1			T5	2704		T22	102194		T24	13845
lc_exec_en	8655442	1			T3	91926		T5	16130		T22	37218
valid_exec_dis	110364528	1			T1	2038		T2	24576		T3	847204
invalid_exec_dis	30952997	1			T3	250218		T5	44492		T14	6087