| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4151580472 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3875971698 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1104876653 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.540799235 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2047584199 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1235284271 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.322520766 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.72690563 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4167993927 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2923173625 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4114689663 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1123076573 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1553146061 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1409695062 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.544671239 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1892199489 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1879610754 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1723181906 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.351980302 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3634803261 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1678390914 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1627793282 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3830145040 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2781962985 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3427244994 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.816013930 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1502379705 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3026836590 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3271016471 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1241142508 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2109883088 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2127361022 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3013019624 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3927527186 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4065819809 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3415321689 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.77170305 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3794621582 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3177333760 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3990827407 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3031730371 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3080215598 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2222303622 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.204866650 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3914649961 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4194227310 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1832807261 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4113123069 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2576179733 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.256991969 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2090101524 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.725908838 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4107493143 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4226004267 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.851811002 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2461765082 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2421713882 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1033191243 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2510050443 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3662036577 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1719731434 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2289692720 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1272497428 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1838645547 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1574806226 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4156526436 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1833929354 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2722842572 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1046238494 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3629529720 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3427861158 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4074892766 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.244811397 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2347338940 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2457376492 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3942957875 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.587684782 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1096652163 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3603692832 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3051614739 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2530107398 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2389133375 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1612741433 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2597866442 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1482157090 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1268261167 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4239921738 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.592568193 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2959104452 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2765535499 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3178817056 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1468800892 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1975283626 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.210986448 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.624614035 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3881735253 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3667198514 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.776695564 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.564103106 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.702746544 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1300933513 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4092899563 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4095927406 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3656280147 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1756760529 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2583513088 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1573084557 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2781525809 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1381101247 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.484354806 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.171591270 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.309463780 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.222144046 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3921138406 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3240727650 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1564777983 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.417651389 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.334338005 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1059363993 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1483408324 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3047944510 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4175591502 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1775785825 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2556034554 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2452685833 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2340262825 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3445782892 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3501956196 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1887891431 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1531283878 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.776838844 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2160555381 |
| /workspace/coverage/default/0.sram_ctrl_bijection.3216933717 |
| /workspace/coverage/default/0.sram_ctrl_executable.4189536244 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.1995690641 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1956937963 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2658479705 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.291789798 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3964978736 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3203691621 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1418812343 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.2833815044 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4082155153 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.1874155723 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3729586283 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.1730558736 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.755607393 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2208898087 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.520497590 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.34882054 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.4097444124 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2962314575 |
| /workspace/coverage/default/1.sram_ctrl_executable.1475452673 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3837407906 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1438671105 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3703725804 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2932494401 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2567966874 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2373789178 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1047805119 |
| /workspace/coverage/default/1.sram_ctrl_regwen.417066783 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.229458472 |
| /workspace/coverage/default/1.sram_ctrl_smoke.104308439 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3298145679 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2785073028 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1769982941 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2456495958 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2574919825 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3126597243 |
| /workspace/coverage/default/10.sram_ctrl_bijection.762142880 |
| /workspace/coverage/default/10.sram_ctrl_executable.2374836374 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.2464620801 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.4144259181 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1783875848 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.146378050 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.2405085078 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3971820643 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.732165380 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1660169117 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1889056578 |
| /workspace/coverage/default/10.sram_ctrl_smoke.4038018880 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.2619143311 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3208050536 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1016988751 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2355261931 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2932031600 |
| /workspace/coverage/default/11.sram_ctrl_bijection.4204621182 |
| /workspace/coverage/default/11.sram_ctrl_executable.2295228352 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.560805295 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1028131492 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3624820539 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.3796687097 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2759839163 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1693482517 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2894633706 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.4191846136 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1089766814 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2235354305 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4087181692 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3028701954 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1948825072 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1904895651 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3274481857 |
| /workspace/coverage/default/12.sram_ctrl_bijection.874358145 |
| /workspace/coverage/default/12.sram_ctrl_executable.4059303429 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1998223161 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.2525365336 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2366658677 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.1453753103 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.758506952 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.994951952 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4189697794 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.2498189084 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3193141794 |
| /workspace/coverage/default/12.sram_ctrl_smoke.828226200 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.109652303 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1769010910 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2821311463 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1589845517 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3676724735 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.4134888125 |
| /workspace/coverage/default/13.sram_ctrl_bijection.300167005 |
| /workspace/coverage/default/13.sram_ctrl_executable.2743853644 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.3328480597 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3345703077 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3209543890 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.623127546 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.877737939 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.500657833 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1035990358 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.2516476653 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1390026387 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1953093780 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.395256292 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.88964431 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1150270875 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.889500998 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.4187188819 |
| /workspace/coverage/default/14.sram_ctrl_bijection.566136637 |
| /workspace/coverage/default/14.sram_ctrl_executable.892368981 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1899815836 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.822026593 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1169337466 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.60832758 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2620437195 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.3214540959 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.213576133 |
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| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2790944484 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3564842212 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.2231628028 |
| /workspace/coverage/default/43.sram_ctrl_bijection.869207703 |
| /workspace/coverage/default/43.sram_ctrl_executable.2502239634 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.1880147015 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.616928966 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3193528352 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.1171903830 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.61085723 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.2325204854 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3995830453 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.1756769466 |
| /workspace/coverage/default/43.sram_ctrl_regwen.897219986 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1306270947 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1586944992 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2199206597 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1652023603 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.88584914 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.1915249577 |
| /workspace/coverage/default/44.sram_ctrl_bijection.4144930451 |
| /workspace/coverage/default/44.sram_ctrl_executable.997159792 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3844154062 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2224240647 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.444117086 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3034720952 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.183484032 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.4243919981 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1606498948 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.1032553210 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3505696352 |
| /workspace/coverage/default/44.sram_ctrl_smoke.151808046 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.2753655526 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2387206800 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2630841492 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2129797235 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1584017773 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.2034246039 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2384072444 |
| /workspace/coverage/default/45.sram_ctrl_executable.217979869 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.226359542 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3953995616 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1067488005 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.394790748 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.966942030 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.4218255930 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.285564975 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.8352123 |
| /workspace/coverage/default/45.sram_ctrl_regwen.805398380 |
| /workspace/coverage/default/45.sram_ctrl_smoke.954353455 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.3310052120 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1846659677 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3025191366 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1860364537 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1489480482 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.791626611 |
| /workspace/coverage/default/46.sram_ctrl_bijection.434986662 |
| /workspace/coverage/default/46.sram_ctrl_executable.3364647832 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1144285236 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.268331806 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.3004023465 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.4192315969 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.3012373655 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.209376668 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.1181820544 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3518315285 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2719572801 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3102575941 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4245902834 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3542118034 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3731688316 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3252961967 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.243440258 |
| /workspace/coverage/default/47.sram_ctrl_bijection.436795581 |
| /workspace/coverage/default/47.sram_ctrl_executable.2365839042 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1638977904 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.2444925811 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1238982613 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1589484120 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3931115716 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3317544851 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.622686144 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.1901616097 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3778641788 |
| /workspace/coverage/default/47.sram_ctrl_smoke.751743756 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.496147647 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1452364707 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3457284020 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3772631769 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2431516787 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.3505414656 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3296164268 |
| /workspace/coverage/default/48.sram_ctrl_executable.2515495776 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1431178711 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3611426643 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2646156573 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.606905085 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2908728225 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.261577394 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.488381886 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3989137485 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3647894050 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3494823985 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.80474892 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2914106458 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3531658764 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3710849660 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.2663339530 |
| /workspace/coverage/default/49.sram_ctrl_bijection.248122411 |
| /workspace/coverage/default/49.sram_ctrl_executable.2419040102 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3200527969 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2845927819 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3957644444 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1428505098 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1534496239 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2690390905 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3622707062 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.3019126279 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3252398396 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3900155508 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.756965951 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.156994911 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.580946701 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2308172219 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2123159014 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.794177866 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3239709215 |
| /workspace/coverage/default/5.sram_ctrl_executable.1836131167 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.827005408 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2426240849 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3180416802 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2429503572 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.690668824 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.3284029120 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2717832697 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1348079899 |
| /workspace/coverage/default/5.sram_ctrl_smoke.4137363076 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.4135281850 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2636930653 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.644432217 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.471299626 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3692809555 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3213311747 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3870790987 |
| /workspace/coverage/default/6.sram_ctrl_executable.1342843016 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3115968452 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.344944621 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.216828061 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.4119102497 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3786630100 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.325987848 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4143914275 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.1060691553 |
| /workspace/coverage/default/6.sram_ctrl_regwen.296656636 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3635616616 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1052100499 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2248138106 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2486024574 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2236472747 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1883037967 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.38620291 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2764791746 |
| /workspace/coverage/default/7.sram_ctrl_executable.762943417 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3233930387 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2346675264 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2970990364 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.641176898 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.630193907 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2674418487 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.557099087 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2254215097 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1639503938 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2842786944 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2841106021 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3545131133 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.811589907 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3286654451 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.756291044 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3187249073 |
| /workspace/coverage/default/8.sram_ctrl_executable.757384916 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3437286200 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.395763143 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1822276977 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.4038970316 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.3452102377 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.2099626959 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1538706935 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2430163408 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1070187834 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2895233619 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.251196009 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1419300055 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4044416011 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1009306236 |
| /workspace/coverage/default/9.sram_ctrl_bijection.494024416 |
| /workspace/coverage/default/9.sram_ctrl_executable.1560067263 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.696035143 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.740135358 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2673510984 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.79810913 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.2857919886 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.4034987305 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3452498169 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.3826533135 |
| /workspace/coverage/default/9.sram_ctrl_regwen.852017182 |
| /workspace/coverage/default/9.sram_ctrl_smoke.407711743 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3426542357 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.273212828 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1571808952 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3662283822 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3703725804 |
|
|
Jan 14 12:35:05 PM PST 24 |
Jan 14 12:35:12 PM PST 24 |
192515544 ps |
| T2 |
/workspace/coverage/default/31.sram_ctrl_bijection.2257621717 |
|
|
Jan 14 12:37:08 PM PST 24 |
Jan 14 12:37:27 PM PST 24 |
576284463 ps |
| T3 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3353739988 |
|
|
Jan 14 12:35:29 PM PST 24 |
Jan 14 01:39:28 PM PST 24 |
305504992809 ps |
| T4 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1096138000 |
|
|
Jan 14 12:36:54 PM PST 24 |
Jan 14 12:37:04 PM PST 24 |
343744580 ps |
| T5 |
/workspace/coverage/default/35.sram_ctrl_stress_all.682539473 |
|
|
Jan 14 12:37:34 PM PST 24 |
Jan 14 12:54:05 PM PST 24 |
129659682621 ps |
| T6 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1756769466 |
|
|
Jan 14 12:38:25 PM PST 24 |
Jan 14 12:38:27 PM PST 24 |
28867892 ps |
| T7 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2749993876 |
|
|
Jan 14 12:38:19 PM PST 24 |
Jan 14 12:38:29 PM PST 24 |
604061044 ps |
| T8 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1529917528 |
|
|
Jan 14 12:37:43 PM PST 24 |
Jan 14 12:43:55 PM PST 24 |
2051907513 ps |
| T9 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.317158198 |
|
|
Jan 14 12:35:10 PM PST 24 |
Jan 14 12:51:51 PM PST 24 |
15320111370 ps |
| T10 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1356795522 |
|
|
Jan 14 12:36:50 PM PST 24 |
Jan 14 12:36:52 PM PST 24 |
168111550 ps |
| T11 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2195012939 |
|
|
Jan 14 12:36:01 PM PST 24 |
Jan 14 12:36:02 PM PST 24 |
36467887 ps |
| T12 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3574015427 |
|
|
Jan 14 12:35:37 PM PST 24 |
Jan 14 12:51:38 PM PST 24 |
11403379362 ps |
| T13 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2954259220 |
|
|
Jan 14 12:36:19 PM PST 24 |
Jan 14 12:36:22 PM PST 24 |
421754373 ps |
| T63 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.236819268 |
|
|
Jan 14 12:34:54 PM PST 24 |
Jan 14 12:39:07 PM PST 24 |
12170366989 ps |
| T87 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.230720479 |
|
|
Jan 14 12:38:01 PM PST 24 |
Jan 14 12:42:21 PM PST 24 |
3673125575 ps |
| T88 |
/workspace/coverage/default/41.sram_ctrl_bijection.3909947216 |
|
|
Jan 14 12:38:03 PM PST 24 |
Jan 14 12:39:17 PM PST 24 |
15172631700 ps |
| T89 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.740135358 |
|
|
Jan 14 12:35:35 PM PST 24 |
Jan 14 12:35:41 PM PST 24 |
50574859 ps |
| T90 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.732165380 |
|
|
Jan 14 12:35:36 PM PST 24 |
Jan 14 12:43:48 PM PST 24 |
18550933020 ps |
| T91 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3665629943 |
|
|
Jan 14 12:35:58 PM PST 24 |
Jan 14 12:36:29 PM PST 24 |
93867596 ps |
| T92 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1573087970 |
|
|
Jan 14 12:37:44 PM PST 24 |
Jan 14 12:37:59 PM PST 24 |
286870083 ps |
| T131 |
/workspace/coverage/default/20.sram_ctrl_smoke.680493584 |
|
|
Jan 14 12:36:14 PM PST 24 |
Jan 14 12:37:34 PM PST 24 |
117371548 ps |
| T15 |
/workspace/coverage/default/26.sram_ctrl_alert_test.790172495 |
|
|
Jan 14 12:36:47 PM PST 24 |
Jan 14 12:36:51 PM PST 24 |
46503776 ps |
| T132 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.2739312339 |
|
|
Jan 14 12:36:20 PM PST 24 |
Jan 14 12:54:53 PM PST 24 |
25584534515 ps |
| T133 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.4038970316 |
|
|
Jan 14 12:35:30 PM PST 24 |
Jan 14 12:35:36 PM PST 24 |
940385987 ps |
| T14 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.348677811 |
|
|
Jan 14 12:35:37 PM PST 24 |
Jan 14 01:51:54 PM PST 24 |
757308618 ps |
| T23 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2896584391 |
|
|
Jan 14 12:37:04 PM PST 24 |
Jan 14 01:29:21 PM PST 24 |
930378753 ps |
| T25 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1186178478 |
|
|
Jan 14 12:36:29 PM PST 24 |
Jan 14 12:36:30 PM PST 24 |
358636259 ps |
| T47 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3612494013 |
|
|
Jan 14 12:37:08 PM PST 24 |
Jan 14 12:37:17 PM PST 24 |
540311678 ps |
| T22 |
/workspace/coverage/default/9.sram_ctrl_regwen.852017182 |
|
|
Jan 14 12:35:29 PM PST 24 |
Jan 14 12:46:39 PM PST 24 |
13456373587 ps |
| T48 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3624820539 |
|
|
Jan 14 12:35:37 PM PST 24 |
Jan 14 12:35:44 PM PST 24 |
181523823 ps |
| T49 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1734455049 |
|
|
Jan 14 12:36:38 PM PST 24 |
Jan 14 12:36:53 PM PST 24 |
2134632052 ps |
| T50 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1273793090 |
|
|
Jan 14 12:36:06 PM PST 24 |
Jan 14 12:53:24 PM PST 24 |
3239910198 ps |
| T51 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2155349211 |
|
|
Jan 14 12:36:17 PM PST 24 |
Jan 14 12:39:31 PM PST 24 |
2388692438 ps |
| T24 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.263678555 |
|
|
Jan 14 12:36:18 PM PST 24 |
Jan 14 01:13:13 PM PST 24 |
979783900 ps |
| T101 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1348079899 |
|
|
Jan 14 12:35:17 PM PST 24 |
Jan 14 12:35:19 PM PST 24 |
32653073 ps |
| T95 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1476135999 |
|
|
Jan 14 12:36:03 PM PST 24 |
Jan 14 12:41:35 PM PST 24 |
12749032452 ps |
| T134 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.616928966 |
|
|
Jan 14 12:38:10 PM PST 24 |
Jan 14 12:38:13 PM PST 24 |
119801078 ps |
| T135 |
/workspace/coverage/default/17.sram_ctrl_bijection.2807260285 |
|
|
Jan 14 12:35:56 PM PST 24 |
Jan 14 12:36:35 PM PST 24 |
2450403207 ps |
| T71 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2548578103 |
|
|
Jan 14 12:36:42 PM PST 24 |
Jan 14 12:36:48 PM PST 24 |
301257757 ps |
| T16 |
/workspace/coverage/default/47.sram_ctrl_alert_test.243440258 |
|
|
Jan 14 12:38:46 PM PST 24 |
Jan 14 12:38:48 PM PST 24 |
22492690 ps |
| T96 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3867486296 |
|
|
Jan 14 12:37:09 PM PST 24 |
Jan 14 12:40:37 PM PST 24 |
2190291466 ps |
| T117 |
/workspace/coverage/default/48.sram_ctrl_executable.2515495776 |
|
|
Jan 14 12:38:47 PM PST 24 |
Jan 14 01:01:39 PM PST 24 |
27942684272 ps |
| T115 |
/workspace/coverage/default/7.sram_ctrl_executable.762943417 |
|
|
Jan 14 12:35:22 PM PST 24 |
Jan 14 01:04:23 PM PST 24 |
3930297099 ps |
| T72 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2332763762 |
|
|
Jan 14 12:38:05 PM PST 24 |
Jan 14 12:38:09 PM PST 24 |
102981553 ps |
| T73 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2673510984 |
|
|
Jan 14 12:35:29 PM PST 24 |
Jan 14 12:35:35 PM PST 24 |
174380396 ps |
| T136 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1948825072 |
|
|
Jan 14 12:35:37 PM PST 24 |
Jan 14 12:37:55 PM PST 24 |
166479074 ps |
| T97 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3036036809 |
|
|
Jan 14 12:37:01 PM PST 24 |
Jan 14 12:41:17 PM PST 24 |
4174784297 ps |
| T137 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2430163408 |
|
|
Jan 14 12:35:37 PM PST 24 |
Jan 14 12:35:39 PM PST 24 |
52606667 ps |
| T138 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1899882138 |
|
|
Jan 14 12:36:23 PM PST 24 |
Jan 14 12:36:24 PM PST 24 |
36052151 ps |
| T40 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1213641219 |
|
|
Jan 14 12:37:24 PM PST 24 |
Jan 14 01:22:17 PM PST 24 |
405083270 ps |
| T139 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4264239023 |
|
|
Jan 14 12:36:40 PM PST 24 |
Jan 14 12:36:42 PM PST 24 |
89180407 ps |
| T140 |
/workspace/coverage/default/9.sram_ctrl_bijection.494024416 |
|
|
Jan 14 12:35:29 PM PST 24 |
Jan 14 12:36:03 PM PST 24 |
531300029 ps |
| T116 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3310052120 |
|
|
Jan 14 12:38:30 PM PST 24 |
Jan 14 01:38:23 PM PST 24 |
132647552670 ps |
| T18 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3639485189 |
|
|
Jan 14 12:36:45 PM PST 24 |
Jan 14 12:36:51 PM PST 24 |
70067174 ps |
| T141 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2429503572 |
|
|
Jan 14 12:35:14 PM PST 24 |
Jan 14 12:35:20 PM PST 24 |
944476949 ps |
| T74 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3676724735 |
|
|
Jan 14 12:35:48 PM PST 24 |
Jan 14 12:55:43 PM PST 24 |
2970635373 ps |
| T142 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1118999060 |
|
|
Jan 14 12:37:58 PM PST 24 |
Jan 14 12:47:43 PM PST 24 |
4940262275 ps |
| T143 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.471299626 |
|
|
Jan 14 12:35:12 PM PST 24 |
Jan 14 12:36:01 PM PST 24 |
478041683 ps |
| T144 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.89595786 |
|
|
Jan 14 12:36:04 PM PST 24 |
Jan 14 12:36:05 PM PST 24 |
104568628 ps |
| T98 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2630841492 |
|
|
Jan 14 12:38:23 PM PST 24 |
Jan 14 12:43:42 PM PST 24 |
3126367281 ps |
| T129 |
/workspace/coverage/default/40.sram_ctrl_executable.3396007076 |
|
|
Jan 14 12:38:02 PM PST 24 |
Jan 14 12:54:55 PM PST 24 |
17608590710 ps |
| T145 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1317676855 |
|
|
Jan 14 12:37:49 PM PST 24 |
Jan 14 12:37:52 PM PST 24 |
115724441 ps |
| T146 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3025191366 |
|
|
Jan 14 12:38:27 PM PST 24 |
Jan 14 12:43:46 PM PST 24 |
4875680535 ps |
| T147 |
/workspace/coverage/default/19.sram_ctrl_regwen.563683289 |
|
|
Jan 14 12:36:11 PM PST 24 |
Jan 14 12:47:46 PM PST 24 |
7142718272 ps |
| T121 |
/workspace/coverage/default/45.sram_ctrl_executable.217979869 |
|
|
Jan 14 12:38:30 PM PST 24 |
Jan 14 01:04:26 PM PST 24 |
15642877399 ps |
| T148 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2143634712 |
|
|
Jan 14 12:37:47 PM PST 24 |
Jan 14 12:42:11 PM PST 24 |
3383414678 ps |
| T149 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1816663541 |
|
|
Jan 14 12:37:21 PM PST 24 |
Jan 14 12:38:16 PM PST 24 |
468359509 ps |
| T17 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2924929671 |
|
|
Jan 14 12:36:28 PM PST 24 |
Jan 14 12:36:30 PM PST 24 |
17240449 ps |
| T150 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2232877515 |
|
|
Jan 14 12:36:14 PM PST 24 |
Jan 14 12:41:10 PM PST 24 |
6026736914 ps |
| T41 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3208050536 |
|
|
Jan 14 12:35:32 PM PST 24 |
Jan 14 01:21:22 PM PST 24 |
497708012 ps |
| T151 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2298935615 |
|
|
Jan 14 12:36:59 PM PST 24 |
Jan 14 12:37:10 PM PST 24 |
589886526 ps |
| T123 |
/workspace/coverage/default/15.sram_ctrl_regwen.2956813839 |
|
|
Jan 14 12:35:55 PM PST 24 |
Jan 14 12:51:39 PM PST 24 |
13732435994 ps |
| T152 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2224240647 |
|
|
Jan 14 12:38:27 PM PST 24 |
Jan 14 12:38:45 PM PST 24 |
76800665 ps |
| T153 |
/workspace/coverage/default/43.sram_ctrl_bijection.869207703 |
|
|
Jan 14 12:38:09 PM PST 24 |
Jan 14 12:38:34 PM PST 24 |
1507258254 ps |
| T154 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3082288732 |
|
|
Jan 14 12:36:00 PM PST 24 |
Jan 14 12:36:09 PM PST 24 |
186152806 ps |
| T155 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2542718903 |
|
|
Jan 14 12:36:08 PM PST 24 |
Jan 14 12:36:12 PM PST 24 |
168081699 ps |
| T156 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.5534620 |
|
|
Jan 14 12:38:03 PM PST 24 |
Jan 14 12:38:08 PM PST 24 |
225024033 ps |
| T157 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2759839163 |
|
|
Jan 14 12:35:35 PM PST 24 |
Jan 14 12:56:27 PM PST 24 |
35484493025 ps |
| T158 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.661004827 |
|
|
Jan 14 12:37:39 PM PST 24 |
Jan 14 12:43:32 PM PST 24 |
4862661252 ps |
| T159 |
/workspace/coverage/default/36.sram_ctrl_partial_access.780911703 |
|
|
Jan 14 12:37:36 PM PST 24 |
Jan 14 12:37:47 PM PST 24 |
521423937 ps |
| T160 |
/workspace/coverage/default/20.sram_ctrl_executable.504128477 |
|
|
Jan 14 12:36:20 PM PST 24 |
Jan 14 12:52:50 PM PST 24 |
17291130477 ps |
| T161 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.12161333 |
|
|
Jan 14 12:37:33 PM PST 24 |
Jan 14 12:37:35 PM PST 24 |
39789280 ps |
| T162 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3229911255 |
|
|
Jan 14 12:37:27 PM PST 24 |
Jan 14 12:37:35 PM PST 24 |
404432763 ps |
| T163 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2309794167 |
|
|
Jan 14 12:36:20 PM PST 24 |
Jan 14 01:02:49 PM PST 24 |
12190691383 ps |
| T164 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.4121051465 |
|
|
Jan 14 12:37:27 PM PST 24 |
Jan 14 12:40:21 PM PST 24 |
503495042 ps |
| T165 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.171711071 |
|
|
Jan 14 12:35:15 PM PST 24 |
Jan 14 12:35:22 PM PST 24 |
168503690 ps |
| T166 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2626770976 |
|
|
Jan 14 12:37:33 PM PST 24 |
Jan 14 12:37:38 PM PST 24 |
76499503 ps |
| T167 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1991662458 |
|
|
Jan 14 12:36:56 PM PST 24 |
Jan 14 12:39:18 PM PST 24 |
1457809633 ps |
| T118 |
/workspace/coverage/default/47.sram_ctrl_executable.2365839042 |
|
|
Jan 14 12:38:47 PM PST 24 |
Jan 14 12:44:09 PM PST 24 |
2185207839 ps |
| T42 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2452685833 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:28 PM PST 24 |
54632629 ps |
| T55 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4113123069 |
|
|
Jan 14 12:20:26 PM PST 24 |
Jan 14 12:20:27 PM PST 24 |
17466964 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3657483091 |
|
|
Jan 14 12:20:03 PM PST 24 |
Jan 14 12:20:04 PM PST 24 |
33273198 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.334338005 |
|
|
Jan 14 12:22:34 PM PST 24 |
Jan 14 12:22:35 PM PST 24 |
278853756 ps |
| T56 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1409695062 |
|
|
Jan 14 12:22:24 PM PST 24 |
Jan 14 12:22:25 PM PST 24 |
15293362 ps |
| T57 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1082073832 |
|
|
Jan 14 12:20:36 PM PST 24 |
Jan 14 12:20:42 PM PST 24 |
827002371 ps |
| T94 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2583513088 |
|
|
Jan 14 12:22:33 PM PST 24 |
Jan 14 12:22:34 PM PST 24 |
25745489 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.587684782 |
|
|
Jan 14 12:23:53 PM PST 24 |
Jan 14 12:23:55 PM PST 24 |
82814157 ps |
| T37 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4092899563 |
|
|
Jan 14 12:22:33 PM PST 24 |
Jan 14 12:22:34 PM PST 24 |
101988474 ps |
| T52 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4065819809 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
79139807 ps |
| T43 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3603692832 |
|
|
Jan 14 12:22:59 PM PST 24 |
Jan 14 12:23:02 PM PST 24 |
123355005 ps |
| T44 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2347338940 |
|
|
Jan 14 12:23:52 PM PST 24 |
Jan 14 12:23:56 PM PST 24 |
35749036 ps |
| T58 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.256991969 |
|
|
Jan 14 12:23:54 PM PST 24 |
Jan 14 12:23:55 PM PST 24 |
25373953 ps |
| T59 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2959104452 |
|
|
Jan 14 12:22:11 PM PST 24 |
Jan 14 12:22:12 PM PST 24 |
26549623 ps |
| T45 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.540799235 |
|
|
Jan 14 12:22:58 PM PST 24 |
Jan 14 12:23:00 PM PST 24 |
36771291 ps |
| T38 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1975283626 |
|
|
Jan 14 12:19:04 PM PST 24 |
Jan 14 12:19:06 PM PST 24 |
110207166 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2389133375 |
|
|
Jan 14 12:23:16 PM PST 24 |
Jan 14 12:23:22 PM PST 24 |
25331109 ps |
| T61 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1775785825 |
|
|
Jan 14 12:22:08 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
204670412 ps |
| T62 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.171591270 |
|
|
Jan 14 12:23:19 PM PST 24 |
Jan 14 12:23:29 PM PST 24 |
253501163 ps |
| T46 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3629529720 |
|
|
Jan 14 12:22:08 PM PST 24 |
Jan 14 12:22:09 PM PST 24 |
71112430 ps |
| T53 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2722842572 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:11 PM PST 24 |
81130678 ps |
| T64 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.244811397 |
|
|
Jan 14 12:20:01 PM PST 24 |
Jan 14 12:20:02 PM PST 24 |
43833866 ps |
| T68 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3047944510 |
|
|
Jan 14 12:22:34 PM PST 24 |
Jan 14 12:22:35 PM PST 24 |
97053765 ps |
| T65 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3415321689 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:13 PM PST 24 |
100549230 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3178817056 |
|
|
Jan 14 12:19:09 PM PST 24 |
Jan 14 12:19:10 PM PST 24 |
41146957 ps |
| T70 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2556034554 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:37 PM PST 24 |
22031261 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.851811002 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:10 PM PST 24 |
239421036 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1564777983 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:27 PM PST 24 |
12887260 ps |
| T39 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.34103507 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:29 PM PST 24 |
826249959 ps |
| T107 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.725908838 |
|
|
Jan 14 12:22:34 PM PST 24 |
Jan 14 12:22:36 PM PST 24 |
72868191 ps |
| T168 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2923173625 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:07 PM PST 24 |
26390089 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2576179733 |
|
|
Jan 14 12:22:34 PM PST 24 |
Jan 14 12:22:37 PM PST 24 |
829524239 ps |
| T169 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1123076573 |
|
|
Jan 14 12:18:45 PM PST 24 |
Jan 14 12:18:47 PM PST 24 |
14094595 ps |
| T54 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2090101524 |
|
|
Jan 14 12:23:24 PM PST 24 |
Jan 14 12:23:29 PM PST 24 |
137908250 ps |
| T170 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3656280147 |
|
|
Jan 14 12:23:19 PM PST 24 |
Jan 14 12:23:23 PM PST 24 |
42620958 ps |
| T171 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2510050443 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
12425294 ps |
| T172 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.592568193 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:10 PM PST 24 |
60226337 ps |
| T173 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3501956196 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:37 PM PST 24 |
33622894 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.564103106 |
|
|
Jan 14 12:22:09 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
701223893 ps |
| T174 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.702746544 |
|
|
Jan 14 12:23:19 PM PST 24 |
Jan 14 12:23:23 PM PST 24 |
13576859 ps |
| T175 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4156526436 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:13 PM PST 24 |
1538561119 ps |
| T176 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.72690563 |
|
|
Jan 14 12:22:37 PM PST 24 |
Jan 14 12:22:40 PM PST 24 |
26605110 ps |
| T177 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.351980302 |
|
|
Jan 14 12:19:52 PM PST 24 |
Jan 14 12:19:55 PM PST 24 |
98181693 ps |
| T102 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1795444639 |
|
|
Jan 14 12:21:40 PM PST 24 |
Jan 14 12:21:43 PM PST 24 |
503595673 ps |
| T178 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3240727650 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:27 PM PST 24 |
87502544 ps |
| T179 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3026836590 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:14 PM PST 24 |
20916691 ps |
| T180 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3013019624 |
|
|
Jan 14 12:20:26 PM PST 24 |
Jan 14 12:20:27 PM PST 24 |
19942396 ps |
| T181 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1879610754 |
|
|
Jan 14 12:18:46 PM PST 24 |
Jan 14 12:18:49 PM PST 24 |
77515950 ps |
| T182 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2109883088 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
43656769 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2597866442 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:08 PM PST 24 |
282669879 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4074892766 |
|
|
Jan 14 12:23:52 PM PST 24 |
Jan 14 12:23:55 PM PST 24 |
800462749 ps |
| T183 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3927527186 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
36866864 ps |
| T105 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1241142508 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
361951586 ps |
| T184 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1553146061 |
|
|
Jan 14 12:18:49 PM PST 24 |
Jan 14 12:18:56 PM PST 24 |
116491411 ps |
| T185 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.210986448 |
|
|
Jan 14 12:22:33 PM PST 24 |
Jan 14 12:22:34 PM PST 24 |
71576349 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.77170305 |
|
|
Jan 14 12:22:15 PM PST 24 |
Jan 14 12:22:19 PM PST 24 |
257762256 ps |
| T186 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3634803261 |
|
|
Jan 14 12:22:13 PM PST 24 |
Jan 14 12:22:14 PM PST 24 |
38522912 ps |
| T187 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2765535499 |
|
|
Jan 14 12:18:50 PM PST 24 |
Jan 14 12:18:57 PM PST 24 |
886327584 ps |
| T188 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.322520766 |
|
|
Jan 14 12:18:50 PM PST 24 |
Jan 14 12:18:55 PM PST 24 |
21457777 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4167993927 |
|
|
Jan 14 12:18:36 PM PST 24 |
Jan 14 12:18:38 PM PST 24 |
1117099994 ps |
| T189 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3271016471 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:18 PM PST 24 |
221336622 ps |
| T190 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1033191243 |
|
|
Jan 14 12:20:40 PM PST 24 |
Jan 14 12:20:41 PM PST 24 |
95826354 ps |
| T77 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.417651389 |
|
|
Jan 14 12:19:07 PM PST 24 |
Jan 14 12:19:12 PM PST 24 |
843094291 ps |
| T104 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2781962985 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:38 PM PST 24 |
636056703 ps |
| T191 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1627793282 |
|
|
Jan 14 12:22:13 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
73252607 ps |
| T192 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4107493143 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:08 PM PST 24 |
47228156 ps |
| T193 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1531283878 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:20 PM PST 24 |
499815957 ps |
| T194 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3794621582 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
35161876 ps |
| T195 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.816013930 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
28723304 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3080215598 |
|
|
Jan 14 12:22:59 PM PST 24 |
Jan 14 12:23:00 PM PST 24 |
19462942 ps |
| T196 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.309463780 |
|
|
Jan 14 12:20:29 PM PST 24 |
Jan 14 12:20:30 PM PST 24 |
23805604 ps |
| T197 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3445782892 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:38 PM PST 24 |
128660527 ps |
| T198 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1723181906 |
|
|
Jan 14 12:23:50 PM PST 24 |
Jan 14 12:23:53 PM PST 24 |
260633462 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3942957875 |
|
|
Jan 14 12:22:24 PM PST 24 |
Jan 14 12:22:25 PM PST 24 |
38731879 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4239921738 |
|
|
Jan 14 12:22:29 PM PST 24 |
Jan 14 12:22:30 PM PST 24 |
45934835 ps |
| T84 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1502379705 |
|
|
Jan 14 12:19:31 PM PST 24 |
Jan 14 12:19:42 PM PST 24 |
2682339460 ps |
| T199 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1059363993 |
|
|
Jan 14 12:23:42 PM PST 24 |
Jan 14 12:23:47 PM PST 24 |
138801720 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.544671239 |
|
|
Jan 14 12:18:45 PM PST 24 |
Jan 14 12:18:52 PM PST 24 |
507919254 ps |
| T200 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3914649961 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:11 PM PST 24 |
152085168 ps |
| T201 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1468800892 |
|
|
Jan 14 12:22:29 PM PST 24 |
Jan 14 12:22:33 PM PST 24 |
125969368 ps |
| T202 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2047584199 |
|
|
Jan 14 12:22:59 PM PST 24 |
Jan 14 12:23:00 PM PST 24 |
21582897 ps |
| T203 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1381101247 |
|
|
Jan 14 12:22:09 PM PST 24 |
Jan 14 12:22:11 PM PST 24 |
40364768 ps |
| T204 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3177333760 |
|
|
Jan 14 12:19:54 PM PST 24 |
Jan 14 12:19:58 PM PST 24 |
88181374 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1483408324 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:28 PM PST 24 |
103182321 ps |
| T205 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3881735253 |
|
|
Jan 14 12:23:33 PM PST 24 |
Jan 14 12:23:34 PM PST 24 |
20935667 ps |
| T206 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3830145040 |
|
|
Jan 14 12:23:21 PM PST 24 |
Jan 14 12:23:30 PM PST 24 |
121053661 ps |
| T207 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4194227310 |
|
|
Jan 14 12:19:37 PM PST 24 |
Jan 14 12:19:39 PM PST 24 |
135423419 ps |
| T208 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1300933513 |
|
|
Jan 14 12:23:42 PM PST 24 |
Jan 14 12:23:47 PM PST 24 |
133120301 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1756760529 |
|
|
Jan 14 12:22:09 PM PST 24 |
Jan 14 12:22:12 PM PST 24 |
918066098 ps |
| T110 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3921138406 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
445193476 ps |
| T209 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1887891431 |
|
|
Jan 14 12:22:57 PM PST 24 |
Jan 14 12:22:58 PM PST 24 |
239478955 ps |
| T210 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2127361022 |
|
|
Jan 14 12:22:15 PM PST 24 |
Jan 14 12:22:19 PM PST 24 |
324477417 ps |
| T211 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.222144046 |
|
|
Jan 14 12:19:16 PM PST 24 |
Jan 14 12:19:23 PM PST 24 |
71680721 ps |
| T212 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4151580472 |
|
|
Jan 14 12:23:16 PM PST 24 |
Jan 14 12:23:22 PM PST 24 |
144141581 ps |
| T213 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1104876653 |
|
|
Jan 14 12:20:40 PM PST 24 |
Jan 14 12:20:41 PM PST 24 |
29262254 ps |
| T214 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1096652163 |
|
|
Jan 14 12:23:53 PM PST 24 |
Jan 14 12:23:54 PM PST 24 |
84644700 ps |
| T215 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1833929354 |
|
|
Jan 14 12:21:48 PM PST 24 |
Jan 14 12:21:49 PM PST 24 |
53278535 ps |
| T216 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1268261167 |
|
|
Jan 14 12:18:56 PM PST 24 |
Jan 14 12:18:59 PM PST 24 |
23205633 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3990827407 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:14 PM PST 24 |
105415622 ps |
| T112 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2457376492 |
|
|
Jan 14 12:22:08 PM PST 24 |
Jan 14 12:22:11 PM PST 24 |
408959042 ps |
| T217 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1678390914 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:47 PM PST 24 |
411526343 ps |
| T218 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2461765082 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:16 PM PST 24 |
23964424 ps |
| T219 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.624614035 |
|
|
Jan 14 12:23:32 PM PST 24 |
Jan 14 12:23:35 PM PST 24 |
201361405 ps |
| T220 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1574806226 |
|
|
Jan 14 12:20:40 PM PST 24 |
Jan 14 12:20:41 PM PST 24 |
13267876 ps |
| T221 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1482157090 |
|
|
Jan 14 12:22:54 PM PST 24 |
Jan 14 12:22:56 PM PST 24 |
39807636 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1427276634 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:17 PM PST 24 |
266665691 ps |
| T222 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3875971698 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:09 PM PST 24 |
317083067 ps |
| T223 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2530107398 |
|
|
Jan 14 12:22:32 PM PST 24 |
Jan 14 12:22:38 PM PST 24 |
589244374 ps |
| T224 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3667198514 |
|
|
Jan 14 12:23:32 PM PST 24 |
Jan 14 12:23:34 PM PST 24 |
74197375 ps |
| T225 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3051614739 |
|
|
Jan 14 12:22:50 PM PST 24 |
Jan 14 12:22:53 PM PST 24 |
23069944 ps |
| T106 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2781525809 |
|
|
Jan 14 12:23:33 PM PST 24 |
Jan 14 12:23:36 PM PST 24 |
246331676 ps |
| T226 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3427244994 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:14 PM PST 24 |
128549624 ps |
| T227 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1235284271 |
|
|
Jan 14 12:22:36 PM PST 24 |
Jan 14 12:22:39 PM PST 24 |
935169939 ps |
| T228 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.204866650 |
|
|
Jan 14 12:19:45 PM PST 24 |
Jan 14 12:19:46 PM PST 24 |
43837253 ps |
| T229 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1573084557 |
|
|
Jan 14 12:23:42 PM PST 24 |
Jan 14 12:23:45 PM PST 24 |
54512989 ps |
| T230 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4114689663 |
|
|
Jan 14 12:19:15 PM PST 24 |
Jan 14 12:19:21 PM PST 24 |
35125728 ps |
| T231 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1838645547 |
|
|
Jan 14 12:22:13 PM PST 24 |
Jan 14 12:22:17 PM PST 24 |
49715825 ps |
| T232 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4175591502 |
|
|
Jan 14 12:22:57 PM PST 24 |
Jan 14 12:22:58 PM PST 24 |
16875735 ps |
| T114 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1046238494 |
|
|
Jan 14 12:23:50 PM PST 24 |
Jan 14 12:23:52 PM PST 24 |
186987714 ps |
| T233 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3662036577 |
|
|
Jan 14 12:23:54 PM PST 24 |
Jan 14 12:23:59 PM PST 24 |
4276749063 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1719731434 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
27453348 ps |
| T235 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1272497428 |
|
|
Jan 14 12:22:13 PM PST 24 |
Jan 14 12:22:15 PM PST 24 |
316625898 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1892199489 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:08 PM PST 24 |
24019589 ps |
| T237 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.484354806 |
|
|
Jan 14 12:22:12 PM PST 24 |
Jan 14 12:22:13 PM PST 24 |
48653265 ps |
| T238 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2340262825 |
|
|
Jan 14 12:19:25 PM PST 24 |
Jan 14 12:19:28 PM PST 24 |
975815175 ps |
| T239 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.776695564 |
|
|
Jan 14 12:23:42 PM PST 24 |
Jan 14 12:23:43 PM PST 24 |
14927864 ps |
| T240 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2289692720 |
|
|
Jan 14 12:20:26 PM PST 24 |
Jan 14 12:20:29 PM PST 24 |
121352212 ps |
| T241 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4095927406 |
|
|
Jan 14 12:19:31 PM PST 24 |
Jan 14 12:19:33 PM PST 24 |
76703991 ps |
| T242 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2222303622 |
|
|
Jan 14 12:21:47 PM PST 24 |
Jan 14 12:21:53 PM PST 24 |
815325147 ps |
| T243 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1612741433 |
|
|
Jan 14 12:18:36 PM PST 24 |
Jan 14 12:18:41 PM PST 24 |
133131043 ps |
| T244 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1832807261 |
|
|
Jan 14 12:22:06 PM PST 24 |
Jan 14 12:22:09 PM PST 24 |
120693849 ps |
| T245 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3031730371 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:10 PM PST 24 |
134015070 ps |
| T246 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2421713882 |
|
|
Jan 14 12:22:14 PM PST 24 |
Jan 14 12:22:19 PM PST 24 |
117379199 ps |
| T247 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4226004267 |
|
|
Jan 14 12:22:07 PM PST 24 |
Jan 14 12:22:08 PM PST 24 |
18494802 ps |
| T248 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3427861158 |
|
|
Jan 14 12:22:08 PM PST 24 |
Jan 14 12:22:09 PM PST 24 |
14704116 ps |
| T249 |
/workspace/coverage/default/11.sram_ctrl_regwen.894489319 |
|
|
Jan 14 12:35:40 PM PST 24 |
Jan 14 12:41:45 PM PST 24 |
1656685438 ps |
| T250 |
/workspace/coverage/default/5.sram_ctrl_alert_test.794177866 |
|
|
Jan 14 12:35:19 PM PST 24 |
Jan 14 12:35:21 PM PST 24 |
12910616 ps |
| T251 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.301043030 |
|
|
Jan 14 12:38:03 PM PST 24 |
Jan 14 12:38:06 PM PST 24 |
47571635 ps |
| T252 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.677386803 |
|
|
Jan 14 12:37:58 PM PST 24 |
Jan 14 12:38:00 PM PST 24 |
42789204 ps |
| T253 |
/workspace/coverage/default/16.sram_ctrl_smoke.3569872727 |
|
|
Jan 14 12:35:59 PM PST 24 |
Jan 14 12:36:15 PM PST 24 |
732441048 ps |
| T254 |
/workspace/coverage/default/36.sram_ctrl_alert_test.827799685 |
|
|
Jan 14 12:37:44 PM PST 24 |
Jan 14 12:37:45 PM PST 24 |
47054099 ps |
| T255 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2325204854 |
|
|
Jan 14 12:38:18 PM PST 24 |
Jan 14 12:38:29 PM PST 24 |
953202747 ps |
| T256 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3740456438 |
|
|
Jan 14 12:36:08 PM PST 24 |
Jan 14 12:37:23 PM PST 24 |
120148174 ps |
| T257 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3350386053 |
|
|
Jan 14 12:36:36 PM PST 24 |
Jan 14 12:36:38 PM PST 24 |
63787555 ps |
| T122 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4015596722 |
|
|
Jan 14 12:38:00 PM PST 24 |
Jan 14 01:31:20 PM PST 24 |
409252883697 ps |
| T258 |
/workspace/coverage/default/12.sram_ctrl_bijection.874358145 |
|
|
Jan 14 12:35:42 PM PST 24 |
Jan 14 12:36:44 PM PST 24 |
3790082213 ps |
| T259 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1396234835 |
|
|
Jan 14 12:36:44 PM PST 24 |
Jan 14 12:43:15 PM PST 24 |
30975632159 ps |
| T260 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3642198597 |
|
|
Jan 14 12:35:54 PM PST 24 |
Jan 14 12:41:47 PM PST 24 |
7975825782 ps |
| T261 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1282210487 |
|
|
Jan 14 12:37:48 PM PST 24 |
Jan 14 12:37:58 PM PST 24 |
71899662 ps |
| T262 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.488037435 |
|
|
Jan 14 12:37:27 PM PST 24 |
Jan 14 01:37:47 PM PST 24 |
1462437806 ps |
| T263 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3102395548 |
|
|
Jan 14 12:36:29 PM PST 24 |
Jan 14 12:36:35 PM PST 24 |
646763953 ps |
| T264 |
/workspace/coverage/default/27.sram_ctrl_regwen.372420384 |
|
|
Jan 14 12:36:52 PM PST 24 |
Jan 14 12:50:09 PM PST 24 |
3775088890 ps |
| T265 |
/workspace/coverage/default/4.sram_ctrl_executable.1719212076 |
|
|
Jan 14 12:35:15 PM PST 24 |
Jan 14 01:05:53 PM PST 24 |
28626817075 ps |
| T266 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2134981329 |
|
|
Jan 14 12:36:52 PM PST 24 |
Jan 14 12:36:59 PM PST 24 |
1148900946 ps |
| T267 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3575866531 |
|
|
Jan 14 12:37:45 PM PST 24 |
Jan 14 12:37:47 PM PST 24 |
177693564 ps |
| T268 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1317349232 |
|
|
Jan 14 12:37:06 PM PST 24 |
Jan 14 12:56:54 PM PST 24 |
753751521 ps |
| T269 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2155241607 |
|
|
Jan 14 12:37:07 PM PST 24 |
Jan 14 12:51:56 PM PST 24 |
10410547095 ps |
| T270 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1571808952 |
|
|
Jan 14 12:35:28 PM PST 24 |
Jan 14 12:40:30 PM PST 24 |
2975849472 ps |
| T271 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3328480597 |
|
|
Jan 14 12:35:49 PM PST 24 |
Jan 14 12:35:56 PM PST 24 |
1611165955 ps |
| T272 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3786630100 |
|
|
Jan 14 12:35:18 PM PST 24 |
Jan 14 12:54:16 PM PST 24 |
2315092719 ps |
| T125 |
/workspace/coverage/default/13.sram_ctrl_executable.2743853644 |
|
|
Jan 14 12:35:48 PM PST 24 |
Jan 14 12:47:22 PM PST 24 |
25568011060 ps |