Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43951101	1			T1	53		T2	12288		T3	315012
triple_byte_access	2490766	1			T1	147		T3	5829		T4	11
halfword_access	3732763	1			T1	244		T3	8741		T4	20
byte_access	4987808	1			T1	394		T3	11718		T4	24
zero_access	1254708	1			T1	181		T3	2942		T4	6

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28160914

1

T1

384

T2

6144

T3

172221

auto[1]

28256232

1

T1

635

T2

6144

T3

172021

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21932660	1			T1	3		T2	6144		T3	157626
auto[0]	triple_byte_access	1240959	1			T1	22		T3	2910		T4	8
auto[0]	halfword_access	1863760	1			T1	60		T3	4347		T4	9
auto[0]	byte_access	2492137	1			T1	172		T3	5859		T4	16
auto[0]	zero_access	631398	1			T1	127		T3	1479		T5	489
auto[1]	word_access	22018441	1			T1	50		T2	6144		T3	157386
auto[1]	triple_byte_access	1249807	1			T1	125		T3	2919		T4	3
auto[1]	halfword_access	1869003	1			T1	184		T3	4394		T4	11
auto[1]	byte_access	2495671	1			T1	222		T3	5859		T4	8
auto[1]	zero_access	623310	1			T1	54		T3	1463		T4	6