Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140145377	1			T1	2376		T2	3978		T3	299698
instr_valid_dis	113035188	1			T1	2376		T2	3978		T3	299698
instr_en	20449168	1			T6	103236		T5	115508		T47	239878

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9677263	1			T6	82420		T9	3532		T47	78414
sram_ifetch_valid_disable	111526762	1			T1	2376		T2	3978		T3	299698
sram_ifetch_enable	18941352	1			T4	8426		T6	136436		T5	12222

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140145377	1			T1	2376		T2	3978		T3	299698
hw_debug_en_valid_off	111951424	1			T1	2376		T2	3978		T3	299698
hw_debug_en_on	18390205	1			T4	8426		T6	169728		T5	123862

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111526762	1			T1	2376		T2	3978		T3	299698
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100156361	1			T1	2376		T2	3978		T3	299698
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8259272	1			T6	32486		T5	113574		T47	114800
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4203911	1			T6	82420		T47	70906		T21	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1981208	1			T6	82420		T21	20000		T118	58502
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1655983	1			T47	70906		T18	108440		T34	2508
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4029237	1			T9	3532		T47	7508		T103	76702
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2088477	1			T47	7508		T103	76702		T21	16222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1402972	1			T124	26696		T125	56092		T126	6138
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7412937	1			T6	108940		T5	113574		T47	27228
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3543291	1			T6	108940		T47	27228		T103	67332
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2915213	1			T5	113574		T18	97840		T34	37914

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8672634	1			T6	70750		T5	1934		T47	54172
lc_exec_en	6948031	1			T4	8426		T6	60788		T5	10288
valid_exec_dis	107759763	1			T1	2376		T2	3978		T3	299698
invalid_exec_dis	28618615	1			T4	8426		T6	218856		T5	12222