Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3734065768 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.630625349 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4148843846 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.386756981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1307830027 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.397433955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4157794109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3906529416 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.272155627 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1263614307 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2511781707 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1096167042 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1381424293 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2391325465 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1371034951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1797339065 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4194379190 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3417193521 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.526335737 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3708665003 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2482179792 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1791164971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3695482493 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.781230507 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2344096587 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.887010521 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.397145924 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.800332486 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2490769739 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.144668888 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.563566117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3464723142 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3051489805 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.960468238 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2223237746 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.529226843 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3999311659 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1570448178 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3683289312 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1568199545 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1658225285 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.944103992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.871639375 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3126350453 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3072265215 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4155208169 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2291833088 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2218437225 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1331435149 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2478605770 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1966961803 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1079035077 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3149535528 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.993350663 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1380143288 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3252377449 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2642027839 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1384953218 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2632324118 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1930724100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.249024693 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1392947332 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.36047618 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1077002803 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2219379865 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3411129427 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3171380841 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1408672599 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4029022366 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1764736060 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1402320033 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1154433127 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1235341044 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3832034208 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2298539903 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1146943512 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2423214803 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.161573506 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2408657273 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2900610558 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2849347969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.168216705 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3909466161 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3058765667 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3503653332 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2035967257 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2450436 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3035986541 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1591224350 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1267421845 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.569460802 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.720458682 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2973543220 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.920744477 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3413447687 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3615478444 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.227876218 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1589309326 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3337270199 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3278989986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2319258517 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.615266267 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1483958982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1705207362 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3739012617 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2687676458 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.620191273 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3824774417 |
/workspace/coverage/default/0.sram_ctrl_bijection.3126183452 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1042365400 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3760425187 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2877340143 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2738655086 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1582128320 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3955516337 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3796169274 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4196920160 |
/workspace/coverage/default/0.sram_ctrl_regwen.1124609 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2703347932 |
/workspace/coverage/default/0.sram_ctrl_smoke.4022092423 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1855388296 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2499825494 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3494105576 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4188499263 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2330985216 |
/workspace/coverage/default/1.sram_ctrl_alert_test.4075202635 |
/workspace/coverage/default/1.sram_ctrl_bijection.1965979872 |
/workspace/coverage/default/1.sram_ctrl_executable.1637689004 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3445241794 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1380157051 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2477943956 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.193183796 |
/workspace/coverage/default/1.sram_ctrl_partial_access.4273438838 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1114075892 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2878212397 |
/workspace/coverage/default/1.sram_ctrl_regwen.1483322711 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2379515588 |
/workspace/coverage/default/1.sram_ctrl_smoke.3844767156 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.300113568 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2528902395 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2921361525 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.102223985 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1444374844 |
/workspace/coverage/default/10.sram_ctrl_bijection.3484651255 |
/workspace/coverage/default/10.sram_ctrl_executable.3167603515 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.4239792915 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3939448022 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2431108297 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4050283327 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1436960761 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.64220973 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3467631221 |
/workspace/coverage/default/10.sram_ctrl_regwen.2874156026 |
/workspace/coverage/default/10.sram_ctrl_smoke.3337207976 |
/workspace/coverage/default/10.sram_ctrl_stress_all.945048976 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.409931850 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2883897085 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2024740299 |
/workspace/coverage/default/11.sram_ctrl_alert_test.818325944 |
/workspace/coverage/default/11.sram_ctrl_bijection.4178356523 |
/workspace/coverage/default/11.sram_ctrl_executable.67704934 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3580946233 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3392316826 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2592448509 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.40104095 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.582939089 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1092955200 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3749597591 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2625838596 |
/workspace/coverage/default/11.sram_ctrl_regwen.3226051217 |
/workspace/coverage/default/11.sram_ctrl_smoke.453429078 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1679597701 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2766722967 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2702137615 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2954756582 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.705891698 |
/workspace/coverage/default/12.sram_ctrl_alert_test.876496948 |
/workspace/coverage/default/12.sram_ctrl_bijection.310279781 |
/workspace/coverage/default/12.sram_ctrl_executable.1100721324 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3083741241 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1998321208 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.230372464 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.914331389 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.63622154 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2882189741 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.142636903 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2631480524 |
/workspace/coverage/default/12.sram_ctrl_regwen.3690040331 |
/workspace/coverage/default/12.sram_ctrl_smoke.1074974856 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4135745849 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4161576085 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3137721157 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1044779757 |
/workspace/coverage/default/13.sram_ctrl_alert_test.564051596 |
/workspace/coverage/default/13.sram_ctrl_bijection.978585205 |
/workspace/coverage/default/13.sram_ctrl_executable.2845786735 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2306093618 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3058376043 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.726476265 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2906142558 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.4279695792 |
/workspace/coverage/default/13.sram_ctrl_partial_access.424591526 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.785201508 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.4276346560 |
/workspace/coverage/default/13.sram_ctrl_regwen.488465423 |
/workspace/coverage/default/13.sram_ctrl_smoke.2362293130 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1880861150 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.846843708 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2619462467 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4002571429 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.657536035 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3297209284 |
/workspace/coverage/default/14.sram_ctrl_bijection.1347687833 |
/workspace/coverage/default/14.sram_ctrl_executable.4063076413 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.923251925 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.149338042 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1402691087 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2623793935 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1627666462 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1092010954 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.920815739 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3931798393 |
/workspace/coverage/default/14.sram_ctrl_regwen.2069266209 |
/workspace/coverage/default/14.sram_ctrl_smoke.369387591 |
/workspace/coverage/default/14.sram_ctrl_stress_all.306834676 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2389042417 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.410639200 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2853521897 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2031725396 |
/workspace/coverage/default/15.sram_ctrl_alert_test.356553973 |
/workspace/coverage/default/15.sram_ctrl_bijection.2512905337 |
/workspace/coverage/default/15.sram_ctrl_executable.1345034655 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1110367289 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1560467545 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1761700895 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3549412101 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2467812832 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1519451503 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2404299021 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1677480447 |
/workspace/coverage/default/15.sram_ctrl_regwen.4246069123 |
/workspace/coverage/default/15.sram_ctrl_smoke.814301786 |
/workspace/coverage/default/15.sram_ctrl_stress_all.4047645479 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3098258988 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.445769997 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2367955171 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.178536254 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3929748231 |
/workspace/coverage/default/16.sram_ctrl_bijection.2324367613 |
/workspace/coverage/default/16.sram_ctrl_executable.3658929536 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2101367050 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3431790164 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4176209072 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.4093895454 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.871792762 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3765835977 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.722401789 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.4009871431 |
/workspace/coverage/default/16.sram_ctrl_regwen.2595072645 |
/workspace/coverage/default/16.sram_ctrl_smoke.1631477237 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3179854952 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2074696232 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2886730301 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3398884527 |
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/workspace/coverage/default/46.sram_ctrl_stress_all.3471806606 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3405773284 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.666233063 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3673493510 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2445872272 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2074887107 |
/workspace/coverage/default/47.sram_ctrl_bijection.3898944301 |
/workspace/coverage/default/47.sram_ctrl_executable.3419104523 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3966862052 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1497411505 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.958270205 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1089867715 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3443361920 |
/workspace/coverage/default/47.sram_ctrl_partial_access.4112543715 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4277737473 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1857292696 |
/workspace/coverage/default/47.sram_ctrl_regwen.3193374902 |
/workspace/coverage/default/47.sram_ctrl_smoke.4034586899 |
/workspace/coverage/default/47.sram_ctrl_stress_all.4086821239 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3806141635 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.964406185 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2897590032 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2859586633 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4107913659 |
/workspace/coverage/default/48.sram_ctrl_bijection.3604740060 |
/workspace/coverage/default/48.sram_ctrl_executable.3286733171 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.545829374 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1426781522 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1850524544 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3759825849 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2737682040 |
/workspace/coverage/default/48.sram_ctrl_partial_access.855091626 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4288515954 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3865109882 |
/workspace/coverage/default/48.sram_ctrl_regwen.2338554227 |
/workspace/coverage/default/48.sram_ctrl_smoke.3874941643 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1155453220 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2271519742 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2247336784 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1474077997 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3662473909 |
/workspace/coverage/default/49.sram_ctrl_bijection.1731047384 |
/workspace/coverage/default/49.sram_ctrl_executable.1737667048 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2370160180 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2962083724 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2644548771 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3428730924 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3870249074 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2416884889 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4074088063 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1913648624 |
/workspace/coverage/default/49.sram_ctrl_regwen.79509719 |
/workspace/coverage/default/49.sram_ctrl_smoke.1669995906 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3523957182 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3784160791 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.297527573 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2882116012 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4062057858 |
/workspace/coverage/default/5.sram_ctrl_alert_test.445370460 |
/workspace/coverage/default/5.sram_ctrl_bijection.2734841199 |
/workspace/coverage/default/5.sram_ctrl_executable.323908679 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2370758278 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1770896316 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1947220003 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.400169249 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2583436177 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1530817155 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1861222010 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1282801549 |
/workspace/coverage/default/5.sram_ctrl_regwen.4141919588 |
/workspace/coverage/default/5.sram_ctrl_smoke.3589653843 |
/workspace/coverage/default/5.sram_ctrl_stress_all.4000808285 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4194201146 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.736594194 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4074554095 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3617233716 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3806136355 |
/workspace/coverage/default/6.sram_ctrl_bijection.1268414149 |
/workspace/coverage/default/6.sram_ctrl_executable.3987232735 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3373195986 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.328488457 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.780825902 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2433178143 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.431805638 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1609113101 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3650921134 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3882462003 |
/workspace/coverage/default/6.sram_ctrl_regwen.1424079 |
/workspace/coverage/default/6.sram_ctrl_smoke.644362354 |
/workspace/coverage/default/6.sram_ctrl_stress_all.94921496 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.999697044 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2095368812 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3142861572 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4171372347 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3648875 |
/workspace/coverage/default/7.sram_ctrl_bijection.3191305485 |
/workspace/coverage/default/7.sram_ctrl_executable.3305584017 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2777389433 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.997784885 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1086001210 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3992253381 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3570848231 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1198685604 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.232163052 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2493578406 |
/workspace/coverage/default/7.sram_ctrl_regwen.733529102 |
/workspace/coverage/default/7.sram_ctrl_smoke.1391704389 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3114845449 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1242360339 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3858581756 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1496144753 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2260744858 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1169369190 |
/workspace/coverage/default/8.sram_ctrl_bijection.18218322 |
/workspace/coverage/default/8.sram_ctrl_executable.2438759085 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.152753262 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3075190382 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.547029303 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1040889442 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1636333400 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1556667508 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4243906469 |
/workspace/coverage/default/8.sram_ctrl_regwen.2659632179 |
/workspace/coverage/default/8.sram_ctrl_smoke.2741180039 |
/workspace/coverage/default/8.sram_ctrl_stress_all.706506741 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2792540643 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1757838552 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3075489729 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.480170071 |
/workspace/coverage/default/9.sram_ctrl_alert_test.73698446 |
/workspace/coverage/default/9.sram_ctrl_bijection.1154496399 |
/workspace/coverage/default/9.sram_ctrl_executable.2546847213 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3369727752 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4142415131 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.857335518 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4271490215 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3936099690 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1216488922 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3885432783 |
/workspace/coverage/default/9.sram_ctrl_regwen.616450629 |
/workspace/coverage/default/9.sram_ctrl_smoke.3634363124 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1182461482 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1385380217 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.648317023 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2284088509 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3398884527 |
|
|
Jan 21 01:11:10 PM PST 24 |
Jan 21 01:11:17 PM PST 24 |
189010864 ps |
T2 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2877340143 |
|
|
Jan 21 01:08:17 PM PST 24 |
Jan 21 01:08:27 PM PST 24 |
315087992 ps |
T3 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3300222808 |
|
|
Jan 21 01:49:12 PM PST 24 |
Jan 21 01:59:10 PM PST 24 |
5961992607 ps |
T8 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3232205348 |
|
|
Jan 21 01:51:10 PM PST 24 |
Jan 21 01:51:12 PM PST 24 |
33826564 ps |
T4 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2054620668 |
|
|
Jan 21 01:11:46 PM PST 24 |
Jan 21 03:29:10 PM PST 24 |
5441378999 ps |
T6 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3005061864 |
|
|
Jan 21 01:11:54 PM PST 24 |
Jan 21 01:30:47 PM PST 24 |
14657264616 ps |
T5 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2275515368 |
|
|
Jan 21 01:10:20 PM PST 24 |
Jan 21 01:27:18 PM PST 24 |
20452211310 ps |
T9 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4194201146 |
|
|
Jan 21 01:09:09 PM PST 24 |
Jan 21 02:41:44 PM PST 24 |
3428949931 ps |
T10 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2024740299 |
|
|
Jan 21 01:10:06 PM PST 24 |
Jan 21 01:10:32 PM PST 24 |
125155993 ps |
T11 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2456558195 |
|
|
Jan 21 01:22:12 PM PST 24 |
Jan 21 01:22:43 PM PST 24 |
437537103 ps |
T7 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.595269266 |
|
|
Jan 21 01:20:11 PM PST 24 |
Jan 21 01:20:17 PM PST 24 |
1169618121 ps |
T46 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1353199202 |
|
|
Jan 21 01:15:19 PM PST 24 |
Jan 21 01:16:34 PM PST 24 |
187306434 ps |
T47 |
/workspace/coverage/default/3.sram_ctrl_executable.4250275931 |
|
|
Jan 21 01:08:47 PM PST 24 |
Jan 21 01:30:50 PM PST 24 |
66451578478 ps |
T22 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2847191923 |
|
|
Jan 21 02:03:03 PM PST 24 |
Jan 21 02:03:15 PM PST 24 |
6167503617 ps |
T57 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1947220003 |
|
|
Jan 21 01:09:14 PM PST 24 |
Jan 21 01:09:20 PM PST 24 |
154341768 ps |
T58 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.958270205 |
|
|
Jan 21 01:23:16 PM PST 24 |
Jan 21 01:23:20 PM PST 24 |
992497113 ps |
T103 |
/workspace/coverage/default/49.sram_ctrl_regwen.79509719 |
|
|
Jan 21 01:24:09 PM PST 24 |
Jan 21 01:35:53 PM PST 24 |
49477980497 ps |
T83 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3758837441 |
|
|
Jan 21 01:52:35 PM PST 24 |
Jan 21 01:57:18 PM PST 24 |
11009292658 ps |
T84 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3312725223 |
|
|
Jan 21 01:14:42 PM PST 24 |
Jan 21 01:20:32 PM PST 24 |
39911982472 ps |
T85 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1568202281 |
|
|
Jan 21 01:15:19 PM PST 24 |
Jan 21 01:15:25 PM PST 24 |
836159700 ps |
T128 |
/workspace/coverage/default/25.sram_ctrl_smoke.2794128494 |
|
|
Jan 21 01:13:36 PM PST 24 |
Jan 21 01:15:33 PM PST 24 |
151361343 ps |
T24 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1051840959 |
|
|
Jan 21 02:30:18 PM PST 24 |
Jan 21 02:30:20 PM PST 24 |
30036836 ps |
T21 |
/workspace/coverage/default/6.sram_ctrl_regwen.1424079 |
|
|
Jan 21 01:09:11 PM PST 24 |
Jan 21 01:10:23 PM PST 24 |
16124682360 ps |
T71 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.780825902 |
|
|
Jan 21 01:09:12 PM PST 24 |
Jan 21 01:09:18 PM PST 24 |
365193573 ps |
T12 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1474077997 |
|
|
Jan 21 01:24:06 PM PST 24 |
Jan 21 01:35:22 PM PST 24 |
2719677801 ps |
T129 |
/workspace/coverage/default/5.sram_ctrl_bijection.2734841199 |
|
|
Jan 21 01:09:08 PM PST 24 |
Jan 21 01:09:52 PM PST 24 |
1401665550 ps |
T13 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.910642383 |
|
|
Jan 21 01:15:50 PM PST 24 |
Jan 21 01:52:35 PM PST 24 |
20966304209 ps |
T130 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1436960761 |
|
|
Jan 21 01:09:49 PM PST 24 |
Jan 21 01:09:59 PM PST 24 |
158312780 ps |
T131 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.159726007 |
|
|
Jan 21 01:08:57 PM PST 24 |
Jan 21 01:09:05 PM PST 24 |
518072118 ps |
T132 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3183442258 |
|
|
Jan 21 01:08:35 PM PST 24 |
Jan 21 01:10:21 PM PST 24 |
133106259 ps |
T133 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.863252979 |
|
|
Jan 21 01:20:48 PM PST 24 |
Jan 21 01:25:44 PM PST 24 |
3274213800 ps |
T86 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2723344630 |
|
|
Jan 21 01:19:07 PM PST 24 |
Jan 21 01:23:31 PM PST 24 |
13524691833 ps |
T87 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2738655086 |
|
|
Jan 21 02:27:00 PM PST 24 |
Jan 21 02:27:05 PM PST 24 |
75970146 ps |
T88 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2883897085 |
|
|
Jan 21 01:09:48 PM PST 24 |
Jan 21 01:13:56 PM PST 24 |
10324397530 ps |
T89 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4277737473 |
|
|
Jan 21 01:23:06 PM PST 24 |
Jan 21 01:28:13 PM PST 24 |
54722988757 ps |
T25 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3639654017 |
|
|
Jan 21 01:21:02 PM PST 24 |
Jan 21 01:21:05 PM PST 24 |
83239013 ps |
T90 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2623793935 |
|
|
Jan 21 01:10:39 PM PST 24 |
Jan 21 01:10:47 PM PST 24 |
146262321 ps |
T91 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3966862052 |
|
|
Jan 21 01:40:22 PM PST 24 |
Jan 21 01:40:31 PM PST 24 |
1062780847 ps |
T19 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2532296977 |
|
|
Jan 21 01:11:36 PM PST 24 |
Jan 21 01:11:37 PM PST 24 |
150115590 ps |
T110 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3390567289 |
|
|
Jan 21 01:08:37 PM PST 24 |
Jan 21 01:08:48 PM PST 24 |
843833611 ps |
T134 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3083741241 |
|
|
Jan 21 01:10:15 PM PST 24 |
Jan 21 01:10:23 PM PST 24 |
1048836696 ps |
T122 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3870249074 |
|
|
Jan 21 01:24:01 PM PST 24 |
Jan 21 01:41:04 PM PST 24 |
19550660570 ps |
T135 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.394851165 |
|
|
Jan 21 01:47:03 PM PST 24 |
Jan 21 01:51:03 PM PST 24 |
718064163 ps |
T136 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2543737627 |
|
|
Jan 21 01:15:47 PM PST 24 |
Jan 21 01:18:29 PM PST 24 |
132120497 ps |
T118 |
/workspace/coverage/default/1.sram_ctrl_regwen.1483322711 |
|
|
Jan 21 01:08:33 PM PST 24 |
Jan 21 01:29:57 PM PST 24 |
60241186493 ps |
T137 |
/workspace/coverage/default/8.sram_ctrl_smoke.2741180039 |
|
|
Jan 21 01:09:23 PM PST 24 |
Jan 21 01:09:37 PM PST 24 |
1039366366 ps |
T15 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1043951916 |
|
|
Jan 21 01:09:05 PM PST 24 |
Jan 21 01:09:09 PM PST 24 |
196824800 ps |
T18 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3349237487 |
|
|
Jan 21 01:11:20 PM PST 24 |
Jan 21 02:51:09 PM PST 24 |
75465402118 ps |
T29 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4161576085 |
|
|
Jan 21 01:10:14 PM PST 24 |
Jan 21 01:12:53 PM PST 24 |
1761439410 ps |
T30 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3955516337 |
|
|
Jan 21 01:08:17 PM PST 24 |
Jan 21 01:08:22 PM PST 24 |
54942806 ps |
T31 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1850524544 |
|
|
Jan 21 01:23:40 PM PST 24 |
Jan 21 01:23:44 PM PST 24 |
95373723 ps |
T32 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3250561675 |
|
|
Jan 21 01:22:10 PM PST 24 |
Jan 21 01:22:19 PM PST 24 |
223152793 ps |
T33 |
/workspace/coverage/default/24.sram_ctrl_bijection.2673919735 |
|
|
Jan 21 01:13:17 PM PST 24 |
Jan 21 01:14:26 PM PST 24 |
6818838983 ps |
T34 |
/workspace/coverage/default/8.sram_ctrl_executable.2438759085 |
|
|
Jan 21 01:37:29 PM PST 24 |
Jan 21 01:58:59 PM PST 24 |
12404818219 ps |
T35 |
/workspace/coverage/default/39.sram_ctrl_executable.1729593637 |
|
|
Jan 21 01:54:25 PM PST 24 |
Jan 21 02:18:32 PM PST 24 |
13802417627 ps |
T36 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2747071364 |
|
|
Jan 21 01:20:54 PM PST 24 |
Jan 21 01:20:58 PM PST 24 |
210046067 ps |
T124 |
/workspace/coverage/default/20.sram_ctrl_stress_all.761220599 |
|
|
Jan 21 01:12:17 PM PST 24 |
Jan 21 02:31:33 PM PST 24 |
53363785584 ps |
T138 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1372612703 |
|
|
Jan 21 01:17:29 PM PST 24 |
Jan 21 01:17:36 PM PST 24 |
71924413 ps |
T94 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1954079997 |
|
|
Jan 21 01:15:48 PM PST 24 |
Jan 21 01:20:23 PM PST 24 |
15579702492 ps |
T14 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.866881104 |
|
|
Jan 21 01:10:26 PM PST 24 |
Jan 21 01:17:49 PM PST 24 |
7823129196 ps |
T139 |
/workspace/coverage/default/32.sram_ctrl_partial_access.703670127 |
|
|
Jan 21 01:16:26 PM PST 24 |
Jan 21 01:16:39 PM PST 24 |
8134447395 ps |
T140 |
/workspace/coverage/default/37.sram_ctrl_smoke.4198106130 |
|
|
Jan 21 01:18:28 PM PST 24 |
Jan 21 01:18:39 PM PST 24 |
503760809 ps |
T127 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2253153061 |
|
|
Jan 21 01:11:19 PM PST 24 |
Jan 21 01:11:27 PM PST 24 |
577300234 ps |
T141 |
/workspace/coverage/default/3.sram_ctrl_partial_access.4046285659 |
|
|
Jan 21 01:08:45 PM PST 24 |
Jan 21 01:09:16 PM PST 24 |
1738125388 ps |
T20 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2471642338 |
|
|
Jan 21 01:20:17 PM PST 24 |
Jan 21 01:20:18 PM PST 24 |
46308240 ps |
T142 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3648875 |
|
|
Jan 21 01:09:21 PM PST 24 |
Jan 21 01:09:22 PM PST 24 |
23719282 ps |
T95 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.764624668 |
|
|
Jan 21 01:16:42 PM PST 24 |
Jan 21 01:19:47 PM PST 24 |
3821395082 ps |
T96 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1556667508 |
|
|
Jan 21 01:09:34 PM PST 24 |
Jan 21 01:19:48 PM PST 24 |
26010318652 ps |
T72 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1734449017 |
|
|
Jan 21 01:42:00 PM PST 24 |
Jan 21 01:50:46 PM PST 24 |
4040753975 ps |
T97 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.666233063 |
|
|
Jan 21 01:22:32 PM PST 24 |
Jan 21 01:26:54 PM PST 24 |
11646161103 ps |
T143 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2767906134 |
|
|
Jan 21 01:20:36 PM PST 24 |
Jan 21 01:29:59 PM PST 24 |
13464841375 ps |
T125 |
/workspace/coverage/default/40.sram_ctrl_regwen.3828002146 |
|
|
Jan 21 01:20:12 PM PST 24 |
Jan 21 01:40:02 PM PST 24 |
11044257987 ps |
T23 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1550074739 |
|
|
Jan 21 01:12:15 PM PST 24 |
Jan 21 02:08:59 PM PST 24 |
3351804449 ps |
T105 |
/workspace/coverage/default/23.sram_ctrl_regwen.2405800054 |
|
|
Jan 21 01:13:05 PM PST 24 |
Jan 21 01:32:39 PM PST 24 |
20771227213 ps |
T106 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2842043139 |
|
|
Jan 21 01:08:46 PM PST 24 |
Jan 21 01:08:49 PM PST 24 |
110637656 ps |
T107 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2250847109 |
|
|
Jan 21 01:12:05 PM PST 24 |
Jan 21 01:15:41 PM PST 24 |
2293952906 ps |
T26 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3594747276 |
|
|
Jan 21 01:22:48 PM PST 24 |
Jan 21 01:22:50 PM PST 24 |
45140333 ps |
T108 |
/workspace/coverage/default/46.sram_ctrl_smoke.1976638804 |
|
|
Jan 21 01:22:32 PM PST 24 |
Jan 21 01:22:45 PM PST 24 |
177511946 ps |
T39 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3440114409 |
|
|
Jan 21 01:47:32 PM PST 24 |
Jan 21 03:01:00 PM PST 24 |
656338830 ps |
T109 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2445872272 |
|
|
Jan 21 01:23:05 PM PST 24 |
Jan 21 01:35:05 PM PST 24 |
1474827815 ps |
T144 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1117865 |
|
|
Jan 21 01:17:27 PM PST 24 |
Jan 21 01:17:29 PM PST 24 |
40398276 ps |
T145 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1549488175 |
|
|
Jan 21 01:13:27 PM PST 24 |
Jan 21 01:13:28 PM PST 24 |
33347228 ps |
T146 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2164258581 |
|
|
Jan 21 01:14:35 PM PST 24 |
Jan 21 01:19:41 PM PST 24 |
3196158032 ps |
T147 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2853521897 |
|
|
Jan 21 01:49:45 PM PST 24 |
Jan 21 01:50:19 PM PST 24 |
118508339 ps |
T148 |
/workspace/coverage/default/21.sram_ctrl_bijection.1777459108 |
|
|
Jan 21 01:12:14 PM PST 24 |
Jan 21 01:12:47 PM PST 24 |
2763378789 ps |
T149 |
/workspace/coverage/default/16.sram_ctrl_smoke.1631477237 |
|
|
Jan 21 01:11:12 PM PST 24 |
Jan 21 01:13:40 PM PST 24 |
571930207 ps |
T150 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2012881223 |
|
|
Jan 21 01:08:37 PM PST 24 |
Jan 21 01:13:45 PM PST 24 |
24640981188 ps |
T151 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.582939089 |
|
|
Jan 21 01:09:57 PM PST 24 |
Jan 21 01:29:05 PM PST 24 |
20771865664 ps |
T152 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2306093618 |
|
|
Jan 21 01:10:28 PM PST 24 |
Jan 21 01:10:39 PM PST 24 |
1167693773 ps |
T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2219379865 |
|
|
Jan 21 08:57:31 PM PST 24 |
Jan 21 08:58:00 PM PST 24 |
25185812 ps |
T37 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.281566925 |
|
|
Jan 21 08:58:01 PM PST 24 |
Jan 21 08:58:27 PM PST 24 |
447335145 ps |
T50 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.739764406 |
|
|
Jan 21 08:58:43 PM PST 24 |
Jan 21 08:59:12 PM PST 24 |
15728923 ps |
T38 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1380143288 |
|
|
Jan 21 08:58:36 PM PST 24 |
Jan 21 08:59:08 PM PST 24 |
479037778 ps |
T40 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.237424985 |
|
|
Jan 21 08:57:36 PM PST 24 |
Jan 21 08:58:07 PM PST 24 |
347841238 ps |
T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1408672599 |
|
|
Jan 21 08:57:46 PM PST 24 |
Jan 21 08:58:13 PM PST 24 |
44108195 ps |
T93 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3149535528 |
|
|
Jan 21 08:58:43 PM PST 24 |
Jan 21 08:59:12 PM PST 24 |
17891318 ps |
T51 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3126350453 |
|
|
Jan 21 08:58:32 PM PST 24 |
Jan 21 08:59:01 PM PST 24 |
40405438 ps |
T41 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1568199545 |
|
|
Jan 21 08:58:25 PM PST 24 |
Jan 21 08:58:56 PM PST 24 |
62694880 ps |
T42 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2478605770 |
|
|
Jan 21 08:58:34 PM PST 24 |
Jan 21 08:59:07 PM PST 24 |
230956873 ps |
T43 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2291833088 |
|
|
Jan 21 08:58:36 PM PST 24 |
Jan 21 08:59:08 PM PST 24 |
70045960 ps |
T52 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3337270199 |
|
|
Jan 21 08:57:56 PM PST 24 |
Jan 21 08:58:21 PM PST 24 |
22179814 ps |
T44 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2319258517 |
|
|
Jan 21 08:57:56 PM PST 24 |
Jan 21 08:58:22 PM PST 24 |
72031810 ps |
T45 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3035986541 |
|
|
Jan 21 08:57:55 PM PST 24 |
Jan 21 08:58:22 PM PST 24 |
29489689 ps |
T53 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1381424293 |
|
|
Jan 21 08:57:28 PM PST 24 |
Jan 21 08:57:58 PM PST 24 |
86882030 ps |
T48 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.161573506 |
|
|
Jan 21 08:57:50 PM PST 24 |
Jan 21 08:58:16 PM PST 24 |
29936106 ps |
T54 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.781230507 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:35 PM PST 24 |
52881234 ps |
T55 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1930724100 |
|
|
Jan 21 08:58:41 PM PST 24 |
Jan 21 08:59:12 PM PST 24 |
240989546 ps |
T56 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.800332486 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:38 PM PST 24 |
190888810 ps |
T153 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1077002803 |
|
|
Jan 21 09:11:31 PM PST 24 |
Jan 21 09:11:35 PM PST 24 |
51381761 ps |
T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3278989986 |
|
|
Jan 21 09:23:16 PM PST 24 |
Jan 21 09:23:28 PM PST 24 |
71675803 ps |
T49 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2687676458 |
|
|
Jan 21 08:57:59 PM PST 24 |
Jan 21 08:58:24 PM PST 24 |
139944132 ps |
T154 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.397433955 |
|
|
Jan 21 08:57:23 PM PST 24 |
Jan 21 08:57:55 PM PST 24 |
237379188 ps |
T155 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2391325465 |
|
|
Jan 21 08:57:31 PM PST 24 |
Jan 21 08:58:05 PM PST 24 |
983735042 ps |
T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1115394611 |
|
|
Jan 21 08:57:28 PM PST 24 |
Jan 21 08:57:59 PM PST 24 |
174852780 ps |
T99 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3413447687 |
|
|
Jan 21 08:57:58 PM PST 24 |
Jan 21 08:58:23 PM PST 24 |
14581595 ps |
T156 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1371034951 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:37 PM PST 24 |
44163848 ps |
T157 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3832034208 |
|
|
Jan 21 08:57:36 PM PST 24 |
Jan 21 08:58:10 PM PST 24 |
125518340 ps |
T158 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.993350663 |
|
|
Jan 21 08:58:41 PM PST 24 |
Jan 21 08:59:13 PM PST 24 |
40468319 ps |
T59 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1483958982 |
|
|
Jan 21 08:58:01 PM PST 24 |
Jan 21 08:58:25 PM PST 24 |
12645552 ps |
T66 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4281725319 |
|
|
Jan 21 08:57:58 PM PST 24 |
Jan 21 08:58:24 PM PST 24 |
666627697 ps |
T117 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4155208169 |
|
|
Jan 21 08:58:39 PM PST 24 |
Jan 21 08:59:10 PM PST 24 |
171512630 ps |
T159 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.944103992 |
|
|
Jan 21 08:58:39 PM PST 24 |
Jan 21 08:59:10 PM PST 24 |
89124186 ps |
T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1154456510 |
|
|
Jan 21 08:57:20 PM PST 24 |
Jan 21 08:57:50 PM PST 24 |
27148345 ps |
T160 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2223237746 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:37 PM PST 24 |
150151455 ps |
T161 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2408657273 |
|
|
Jan 21 08:57:54 PM PST 24 |
Jan 21 08:58:19 PM PST 24 |
35991313 ps |
T162 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2423214803 |
|
|
Jan 21 08:57:54 PM PST 24 |
Jan 21 08:58:19 PM PST 24 |
14693860 ps |
T163 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3906529416 |
|
|
Jan 21 09:36:15 PM PST 24 |
Jan 21 09:36:18 PM PST 24 |
15517191 ps |
T164 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.397145924 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:36 PM PST 24 |
629131828 ps |
T101 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1154433127 |
|
|
Jan 21 08:57:47 PM PST 24 |
Jan 21 08:58:13 PM PST 24 |
47738228 ps |
T165 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2900610558 |
|
|
Jan 21 08:57:51 PM PST 24 |
Jan 21 08:58:17 PM PST 24 |
19339921 ps |
T166 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2035967257 |
|
|
Jan 21 08:57:52 PM PST 24 |
Jan 21 08:58:19 PM PST 24 |
32214325 ps |
T167 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.569460802 |
|
|
Jan 21 08:57:56 PM PST 24 |
Jan 21 08:58:22 PM PST 24 |
263777172 ps |
T168 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3171380841 |
|
|
Jan 21 08:57:31 PM PST 24 |
Jan 21 08:58:04 PM PST 24 |
36534323 ps |
T169 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2511781707 |
|
|
Jan 21 08:57:36 PM PST 24 |
Jan 21 08:58:07 PM PST 24 |
79101123 ps |
T170 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3734065768 |
|
|
Jan 21 08:57:22 PM PST 24 |
Jan 21 08:57:51 PM PST 24 |
41870685 ps |
T171 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2642027839 |
|
|
Jan 21 08:58:42 PM PST 24 |
Jan 21 08:59:11 PM PST 24 |
13957032 ps |
T172 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.887010521 |
|
|
Jan 21 08:58:13 PM PST 24 |
Jan 21 08:58:39 PM PST 24 |
19355127 ps |
T173 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1791164971 |
|
|
Jan 21 08:58:08 PM PST 24 |
Jan 21 08:58:35 PM PST 24 |
308508859 ps |
T60 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2298539903 |
|
|
Jan 21 08:57:56 PM PST 24 |
Jan 21 08:58:21 PM PST 24 |
70649162 ps |
T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1764736060 |
|
|
Jan 21 08:57:43 PM PST 24 |
Jan 21 08:58:11 PM PST 24 |
16306470 ps |
T61 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1570448178 |
|
|
Jan 21 08:58:23 PM PST 24 |
Jan 21 08:58:53 PM PST 24 |
12380823 ps |
T62 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4194379190 |
|
|
Jan 21 08:58:02 PM PST 24 |
Jan 21 08:58:26 PM PST 24 |
43058971 ps |
T68 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.960468238 |
|
|
Jan 21 08:58:15 PM PST 24 |
Jan 21 08:58:42 PM PST 24 |
15058382 ps |
T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2849347969 |
|
|
Jan 21 08:57:42 PM PST 24 |
Jan 21 08:58:13 PM PST 24 |
40035365 ps |
T70 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.386756981 |
|
|
Jan 21 08:57:25 PM PST 24 |
Jan 21 08:57:55 PM PST 24 |
38006158 ps |
T80 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3999311659 |
|
|
Jan 21 08:58:27 PM PST 24 |
Jan 21 08:58:57 PM PST 24 |
40633409 ps |
T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1797339065 |
|
|
Jan 21 08:58:00 PM PST 24 |
Jan 21 08:58:23 PM PST 24 |
21169072 ps |
T64 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1267421845 |
|
|
Jan 21 08:57:54 PM PST 24 |
Jan 21 08:58:19 PM PST 24 |
31573600 ps |
T174 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3051489805 |
|
|
Jan 21 08:58:25 PM PST 24 |
Jan 21 08:58:55 PM PST 24 |
45208540 ps |
T65 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3411129427 |
|
|
Jan 21 10:55:55 PM PST 24 |
Jan 21 10:55:57 PM PST 24 |
36985377 ps |
T175 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3909466161 |
|
|
Jan 21 08:57:59 PM PST 24 |
Jan 21 08:58:24 PM PST 24 |
484491265 ps |
T176 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1307830027 |
|
|
Jan 21 08:57:21 PM PST 24 |
Jan 21 08:57:50 PM PST 24 |
12441339 ps |
T177 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.272155627 |
|
|
Jan 21 09:05:59 PM PST 24 |
Jan 21 09:06:34 PM PST 24 |
44892733 ps |
T178 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3683289312 |
|
|
Jan 21 08:58:30 PM PST 24 |
Jan 21 08:59:00 PM PST 24 |
69451325 ps |
T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1966961803 |
|
|
Jan 21 08:58:31 PM PST 24 |
Jan 21 08:59:01 PM PST 24 |
145447976 ps |
T111 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3695482493 |
|
|
Jan 21 08:58:07 PM PST 24 |
Jan 21 08:58:33 PM PST 24 |
304858395 ps |
T179 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2218437225 |
|
|
Jan 21 08:58:38 PM PST 24 |
Jan 21 08:59:09 PM PST 24 |
12002921 ps |
T180 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1096167042 |
|
|
Jan 21 09:22:45 PM PST 24 |
Jan 21 09:22:49 PM PST 24 |
26240660 ps |
T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.31136849 |
|
|
Jan 21 08:58:19 PM PST 24 |
Jan 21 08:58:48 PM PST 24 |
38960554 ps |
T77 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.720458682 |
|
|
Jan 21 08:57:55 PM PST 24 |
Jan 21 08:58:22 PM PST 24 |
636654216 ps |
T181 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.529226843 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:35 PM PST 24 |
310321237 ps |
T182 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1658225285 |
|
|
Jan 21 08:58:28 PM PST 24 |
Jan 21 08:58:59 PM PST 24 |
107019999 ps |
T183 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3615478444 |
|
|
Jan 21 08:57:55 PM PST 24 |
Jan 21 08:58:22 PM PST 24 |
90758510 ps |
T114 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.168216705 |
|
|
Jan 21 08:57:50 PM PST 24 |
Jan 21 08:58:17 PM PST 24 |
954274326 ps |
T184 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.526335737 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:38 PM PST 24 |
31773501 ps |
T185 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1589309326 |
|
|
Jan 21 08:58:00 PM PST 24 |
Jan 21 08:58:24 PM PST 24 |
109910600 ps |
T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2450436 |
|
|
Jan 21 08:57:56 PM PST 24 |
Jan 21 08:58:23 PM PST 24 |
275639792 ps |
T186 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3503653332 |
|
|
Jan 21 08:57:59 PM PST 24 |
Jan 21 08:58:23 PM PST 24 |
33869201 ps |
T187 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1705207362 |
|
|
Jan 21 08:58:03 PM PST 24 |
Jan 21 08:58:28 PM PST 24 |
63221772 ps |
T74 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.249024693 |
|
|
Jan 21 10:56:31 PM PST 24 |
Jan 21 10:56:33 PM PST 24 |
32843201 ps |
T78 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2482179792 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:35 PM PST 24 |
33272781 ps |
T79 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2632324118 |
|
|
Jan 21 08:58:42 PM PST 24 |
Jan 21 08:59:13 PM PST 24 |
63543786 ps |
T81 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3708665003 |
|
|
Jan 21 08:58:08 PM PST 24 |
Jan 21 08:58:33 PM PST 24 |
20162458 ps |
T82 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4157794109 |
|
|
Jan 21 09:49:53 PM PST 24 |
Jan 21 09:50:02 PM PST 24 |
350502943 ps |
T188 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.227876218 |
|
|
Jan 21 10:09:44 PM PST 24 |
Jan 21 10:09:51 PM PST 24 |
2334476855 ps |
T189 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1079035077 |
|
|
Jan 21 08:58:44 PM PST 24 |
Jan 21 08:59:14 PM PST 24 |
75704211 ps |
T190 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2490769739 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:38 PM PST 24 |
101734862 ps |
T191 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4029022366 |
|
|
Jan 21 08:57:39 PM PST 24 |
Jan 21 08:58:09 PM PST 24 |
124493669 ps |
T192 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4148843846 |
|
|
Jan 21 08:57:26 PM PST 24 |
Jan 21 08:57:55 PM PST 24 |
39151894 ps |
T193 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3058765667 |
|
|
Jan 21 08:57:54 PM PST 24 |
Jan 21 08:58:19 PM PST 24 |
14172274 ps |
T194 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.871639375 |
|
|
Jan 21 08:58:36 PM PST 24 |
Jan 21 08:59:06 PM PST 24 |
22537021 ps |
T195 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1402320033 |
|
|
Jan 21 08:57:41 PM PST 24 |
Jan 21 08:58:10 PM PST 24 |
35176008 ps |
T196 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1263614307 |
|
|
Jan 21 08:57:28 PM PST 24 |
Jan 21 08:57:57 PM PST 24 |
14590881 ps |
T197 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1146943512 |
|
|
Jan 21 08:57:51 PM PST 24 |
Jan 21 08:58:17 PM PST 24 |
256834002 ps |
T113 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3438029300 |
|
|
Jan 21 08:57:36 PM PST 24 |
Jan 21 08:58:08 PM PST 24 |
428264891 ps |
T198 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3417193521 |
|
|
Jan 21 08:58:02 PM PST 24 |
Jan 21 08:58:29 PM PST 24 |
58385445 ps |
T199 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.36047618 |
|
|
Jan 21 08:57:29 PM PST 24 |
Jan 21 08:57:58 PM PST 24 |
29276103 ps |
T200 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.630625349 |
|
|
Jan 21 08:57:24 PM PST 24 |
Jan 21 08:57:53 PM PST 24 |
49150553 ps |
T201 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.563566117 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:38 PM PST 24 |
41028925 ps |
T202 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3464723142 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:40 PM PST 24 |
40187041 ps |
T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1591224350 |
|
|
Jan 21 08:57:55 PM PST 24 |
Jan 21 08:58:20 PM PST 24 |
40152969 ps |
T203 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2344096587 |
|
|
Jan 21 08:58:13 PM PST 24 |
Jan 21 08:58:38 PM PST 24 |
14646413 ps |
T204 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1392947332 |
|
|
Jan 21 09:23:32 PM PST 24 |
Jan 21 09:23:45 PM PST 24 |
242683008 ps |
T205 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2973543220 |
|
|
Jan 21 08:57:59 PM PST 24 |
Jan 21 08:58:24 PM PST 24 |
43234160 ps |
T206 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1331435149 |
|
|
Jan 21 08:58:35 PM PST 24 |
Jan 21 08:59:06 PM PST 24 |
23117654 ps |
T207 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.615266267 |
|
|
Jan 21 08:58:01 PM PST 24 |
Jan 21 08:58:27 PM PST 24 |
30819311 ps |
T116 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2315517106 |
|
|
Jan 21 08:58:12 PM PST 24 |
Jan 21 08:58:39 PM PST 24 |
596976816 ps |
T208 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1384953218 |
|
|
Jan 21 09:38:52 PM PST 24 |
Jan 21 09:38:53 PM PST 24 |
22231371 ps |
T76 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.144668888 |
|
|
Jan 21 08:58:10 PM PST 24 |
Jan 21 08:58:35 PM PST 24 |
25162390 ps |
T209 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3252377449 |
|
|
Jan 21 08:58:41 PM PST 24 |
Jan 21 08:59:12 PM PST 24 |
51337084 ps |
T210 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3739012617 |
|
|
Jan 21 08:58:04 PM PST 24 |
Jan 21 08:58:31 PM PST 24 |
481294168 ps |
T211 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.920744477 |
|
|
Jan 21 08:57:55 PM PST 24 |
Jan 21 08:58:20 PM PST 24 |
20232862 ps |
T212 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1235341044 |
|
|
Jan 21 08:57:46 PM PST 24 |
Jan 21 08:58:13 PM PST 24 |
120452565 ps |
T213 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3072265215 |
|
|
Jan 21 08:58:35 PM PST 24 |
Jan 21 08:59:09 PM PST 24 |
442244275 ps |
T214 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3189267338 |
|
|
Jan 21 01:14:35 PM PST 24 |
Jan 21 01:14:36 PM PST 24 |
74890239 ps |
T215 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1861222010 |
|
|
Jan 21 01:08:58 PM PST 24 |
Jan 21 01:15:13 PM PST 24 |
98151508535 ps |
T216 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.178536254 |
|
|
Jan 21 01:11:11 PM PST 24 |
Jan 21 01:26:17 PM PST 24 |
61256239669 ps |
T217 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.321309606 |
|
|
Jan 21 01:14:44 PM PST 24 |
Jan 21 01:14:48 PM PST 24 |
176618929 ps |
T218 |
/workspace/coverage/default/33.sram_ctrl_smoke.1799782187 |
|
|
Jan 21 01:16:47 PM PST 24 |
Jan 21 01:19:21 PM PST 24 |
2593429952 ps |
T219 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3459939790 |
|
|
Jan 21 01:09:04 PM PST 24 |
Jan 21 01:09:06 PM PST 24 |
13398156 ps |
T220 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1275645729 |
|
|
Jan 21 01:12:35 PM PST 24 |
Jan 21 01:12:41 PM PST 24 |
64566405 ps |
T221 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2510246554 |
|
|
Jan 21 01:18:14 PM PST 24 |
Jan 21 01:18:17 PM PST 24 |
106382294 ps |
T222 |
/workspace/coverage/default/32.sram_ctrl_bijection.4274898873 |
|
|
Jan 21 01:16:15 PM PST 24 |
Jan 21 01:17:19 PM PST 24 |
7802313472 ps |
T223 |
/workspace/coverage/default/43.sram_ctrl_stress_all.414151731 |
|
|
Jan 21 01:21:32 PM PST 24 |
Jan 21 02:05:07 PM PST 24 |
42863703957 ps |
T224 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1044779757 |
|
|
Jan 21 01:10:20 PM PST 24 |
Jan 21 01:24:39 PM PST 24 |
6317219948 ps |
T225 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3010832678 |
|
|
Jan 21 01:22:48 PM PST 24 |
Jan 21 01:22:54 PM PST 24 |
97136139 ps |
T226 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3580946233 |
|
|
Jan 21 01:10:02 PM PST 24 |
Jan 21 01:10:14 PM PST 24 |
1651555048 ps |
T227 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.360292353 |
|
|
Jan 21 01:22:00 PM PST 24 |
Jan 21 01:41:18 PM PST 24 |
8199660465 ps |
T228 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3380230974 |
|
|
Jan 21 01:21:22 PM PST 24 |
Jan 21 01:35:29 PM PST 24 |
7863571187 ps |
T229 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1198685604 |
|
|
Jan 21 01:09:20 PM PST 24 |
Jan 21 01:10:12 PM PST 24 |
1718903517 ps |
T230 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2528902395 |
|
|
Jan 21 01:08:24 PM PST 24 |
Jan 21 01:09:50 PM PST 24 |
934530288 ps |
T231 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2962083724 |
|
|
Jan 21 01:23:58 PM PST 24 |
Jan 21 01:24:06 PM PST 24 |
83088216 ps |
T232 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3199141836 |
|
|
Jan 21 01:48:07 PM PST 24 |
Jan 21 01:48:26 PM PST 24 |
439732417 ps |
T233 |
/workspace/coverage/default/6.sram_ctrl_bijection.1268414149 |
|
|
Jan 21 01:09:12 PM PST 24 |
Jan 21 01:09:46 PM PST 24 |
8125421180 ps |
T234 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3656240102 |
|
|
Jan 21 01:15:57 PM PST 24 |
Jan 21 01:16:40 PM PST 24 |
382114154 ps |
T126 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3523957182 |
|
|
Jan 21 01:24:18 PM PST 24 |
Jan 21 01:57:22 PM PST 24 |
23973943925 ps |
T235 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.52839901 |
|
|
Jan 21 01:13:04 PM PST 24 |
Jan 21 01:37:17 PM PST 24 |
3047962257 ps |
T236 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.292130104 |
|
|
Jan 21 01:13:35 PM PST 24 |
Jan 21 01:13:46 PM PST 24 |
235529884 ps |
T237 |
/workspace/coverage/default/28.sram_ctrl_stress_all.526798626 |
|
|
Jan 21 01:15:02 PM PST 24 |
Jan 21 01:42:27 PM PST 24 |
33639414811 ps |
T238 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2714614415 |
|
|
Jan 21 01:14:04 PM PST 24 |
Jan 21 01:16:13 PM PST 24 |
1406271163 ps |
T239 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2272931861 |
|
|
Jan 21 01:14:24 PM PST 24 |
Jan 21 01:14:34 PM PST 24 |
521409324 ps |
T240 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2971632981 |
|
|
Jan 21 01:16:44 PM PST 24 |
Jan 21 01:24:41 PM PST 24 |
7591145512 ps |
T241 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2865663433 |
|
|
Jan 21 01:40:43 PM PST 24 |
Jan 21 01:41:05 PM PST 24 |
5790556930 ps |
T242 |
/workspace/coverage/default/0.sram_ctrl_executable.3735724335 |
|
|
Jan 21 02:57:01 PM PST 24 |
Jan 21 03:16:57 PM PST 24 |
60852321228 ps |
T243 |
/workspace/coverage/default/0.sram_ctrl_regwen.1124609 |
|
|
Jan 21 01:08:17 PM PST 24 |
Jan 21 01:10:25 PM PST 24 |
1707902726 ps |
T244 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3336086893 |
|
|
Jan 21 01:52:39 PM PST 24 |
Jan 21 01:58:20 PM PST 24 |
55913867249 ps |
T245 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2921361525 |
|
|
Jan 21 01:08:25 PM PST 24 |
Jan 21 01:10:10 PM PST 24 |
181220948 ps |
T246 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1747767683 |
|
|
Jan 21 01:14:25 PM PST 24 |
Jan 21 01:14:31 PM PST 24 |
235316376 ps |
T247 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2631476240 |
|
|
Jan 21 01:09:14 PM PST 24 |
Jan 21 01:09:16 PM PST 24 |
42761251 ps |
T248 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.4174929719 |
|
|
Jan 21 02:12:14 PM PST 24 |
Jan 21 02:12:19 PM PST 24 |
78492826 ps |
T249 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3673212537 |
|
|
Jan 21 01:17:45 PM PST 24 |
Jan 21 01:18:23 PM PST 24 |
189805918 ps |
T250 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1360903183 |
|
|
Jan 21 01:21:14 PM PST 24 |
Jan 21 01:21:20 PM PST 24 |
174841342 ps |
T251 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2101367050 |
|
|
Jan 21 01:47:11 PM PST 24 |
Jan 21 01:47:18 PM PST 24 |
2020070928 ps |
T252 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3428730924 |
|
|
Jan 21 02:08:27 PM PST 24 |
Jan 21 02:08:37 PM PST 24 |
860563762 ps |
T253 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1284974366 |
|
|
Jan 21 01:19:59 PM PST 24 |
Jan 21 01:20:03 PM PST 24 |
447851946 ps |
T254 |
/workspace/coverage/default/30.sram_ctrl_smoke.3649788850 |
|
|
Jan 21 01:15:25 PM PST 24 |
Jan 21 01:16:58 PM PST 24 |
1164552748 ps |
T255 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2013777006 |
|
|
Jan 21 01:44:20 PM PST 24 |
Jan 21 01:44:25 PM PST 24 |
37247038 ps |
T256 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1060430732 |
|
|
Jan 21 01:13:25 PM PST 24 |
Jan 21 01:13:33 PM PST 24 |
379824278 ps |
T257 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.997784885 |
|
|
Jan 21 01:09:18 PM PST 24 |
Jan 21 01:09:29 PM PST 24 |
65476667 ps |
T258 |
/workspace/coverage/default/29.sram_ctrl_smoke.2024700658 |
|
|
Jan 21 01:15:08 PM PST 24 |
Jan 21 01:15:25 PM PST 24 |
3358248286 ps |