Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42503379	1			T1	979		T2	122		T3	136037
triple_byte_access	2397195	1			T1	47		T2	233		T3	2773
halfword_access	3592355	1			T1	56		T2	446		T3	4086
byte_access	4799616	1			T1	85		T2	801		T3	5612
zero_access	1209388	1			T1	21		T2	387		T3	1341

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27201087

1

T1

589

T2

863

T3

74963

auto[1]

27300846

1

T1

599

T2

1126

T3

74886

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21204959	1			T1	507		T2	8		T3	68090
auto[0]	triple_byte_access	1195571	1			T1	17		T2	41		T3	1404
auto[0]	halfword_access	1792139	1			T1	17		T2	130		T3	2064
auto[0]	byte_access	2399687	1			T1	38		T2	396		T3	2766
auto[0]	zero_access	608731	1			T1	10		T2	288		T3	639
auto[1]	word_access	21298420	1			T1	472		T2	114		T3	67947
auto[1]	triple_byte_access	1201624	1			T1	30		T2	192		T3	1369
auto[1]	halfword_access	1800216	1			T1	39		T2	316		T3	2022
auto[1]	byte_access	2399929	1			T1	47		T2	405		T3	2846
auto[1]	zero_access	600657	1			T1	11		T2	99		T3	702