Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142147444	1			T1	26616		T2	3878		T4	291394
instr_valid_dis	108991949	1			T1	26616		T2	3878		T4	291394
instr_en	22242884	1			T11	78178		T6	127318		T7	280902

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9494875	1			T4	8504		T11	3376		T6	137640
sram_ifetch_valid_disable	110971302	1			T1	26616		T2	3878		T4	223092
sram_ifetch_enable	21681267	1			T4	59798		T11	98724		T6	126934

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142147444	1			T1	26616		T2	3878		T4	291394
hw_debug_en_valid_off	110635353	1			T1	26616		T2	3878		T4	114332
hw_debug_en_on	20490869	1			T4	143242		T11	92272		T6	131096

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110971302	1			T1	26616		T2	3878		T4	223092
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97624161	1			T1	26616		T2	3878		T4	223092
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9174246	1			T11	12314		T6	37158		T7	129460
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3262342	1			T6	29410		T21	45008		T102	48598
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1212682	1			T21	45008		T103	3212		T107	3248
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1518435	1			T102	48598		T103	80360		T108	75424
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4401466	1			T4	8504		T11	3376		T6	60610
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1355603	1			T4	8504		T11	3376		T6	18218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1975607	1			T6	42392		T7	34826		T102	39216
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7627912	1			T4	103738		T11	36530		T6	20768
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2903666	1			T4	103738		T11	36530		T6	16006
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3435444	1			T7	81750		T29	9743		T21	84

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8736386	1			T11	65864		T6	9610		T7	101738
lc_exec_en	8461491	1			T4	31000		T11	52366		T6	49718
valid_exec_dis	106874240	1			T1	26616		T2	3878		T4	145332
invalid_exec_dis	31176142	1			T4	68302		T11	102100		T6	264574