Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147006265	1			T1	522518		T2	512262		T3	24576
instr_valid_dis	117480083	1			T1	522518		T2	512262		T3	24576
instr_en	21401250	1			T15	80945		T14	489		T64	338920

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10405853	1			T15	21680		T16	68616		T64	17278
sram_ifetch_valid_disable	114394682	1			T1	522518		T2	512262		T3	24576
sram_ifetch_enable	22205730	1			T15	31908		T16	86576		T64	170282

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147006265	1			T1	522518		T2	512262		T3	24576
hw_debug_en_valid_off	114591629	1			T1	522518		T2	512262		T3	24576
hw_debug_en_on	22375431	1			T15	11964		T16	54262		T14	489

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114394682	1			T1	522518		T2	512262		T3	24576
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102869616	1			T1	522518		T2	512262		T3	24576
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8312678	1			T15	27357		T14	489		T64	151360
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4315135	1			T16	59366		T25	114114		T129	120478
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1902496	1			T16	59366		T25	83698		T135	10042
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1704795	1			T25	30416		T129	120478		T127	43936
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4375682	1			T64	17278		T111	36616		T25	184708
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2064774	1			T111	36616		T25	113964		T134	34688
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1922096	1			T64	17278		T25	70744		T135	19140
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9415137	1			T16	41584		T14	489		T64	107950
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3994036	1			T16	41584		T25	254842		T128	65818
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3761359	1			T14	489		T64	107950		T25	57162

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8624687	1			T15	31908		T64	170282		T25	139274
lc_exec_en	8584612	1			T15	11964		T16	12678		T111	5094
valid_exec_dis	110917319	1			T1	522518		T2	512262		T3	24576
invalid_exec_dis	32611583	1			T15	53588		T16	155192		T64	187560