Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.50	100.00	98.18	100.00	100.00	99.71	99.70	98.89

Total tests in report: 1011

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
83.96	83.96	96.79	96.79	77.45	77.45	93.13	93.13	71.43	71.43	88.18	88.18	95.80	95.80	64.94	64.94	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3701777451
91.57	7.61	98.35	1.55	85.71	8.26	93.63	0.50	100.00	28.57	94.24	6.05	95.80	0.00	73.28	8.35	/workspace/coverage/default/10.sram_ctrl_stress_all.1716265083
96.15	4.58	99.51	1.17	93.98	8.26	98.28	4.65	100.00	0.00	97.12	2.88	97.15	1.35	87.01	13.73	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1975076023
97.23	1.08	99.71	0.19	95.10	1.12	98.86	0.57	100.00	0.00	97.98	0.86	97.15	0.00	91.84	4.82	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4053080260
97.88	0.65	99.90	0.19	97.20	2.10	99.28	0.43	100.00	0.00	98.85	0.86	97.75	0.60	92.21	0.37	/workspace/coverage/default/0.sram_ctrl_sec_cm.4073705636
98.22	0.34	99.90	0.00	97.62	0.42	99.28	0.00	100.00	0.00	99.14	0.29	97.75	0.00	93.88	1.67	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1912180123
98.54	0.32	99.90	0.00	97.62	0.00	99.28	0.00	100.00	0.00	99.14	0.00	97.75	0.00	96.10	2.23	/workspace/coverage/default/20.sram_ctrl_stress_all.4003258043
98.73	0.19	99.90	0.00	97.62	0.00	99.28	0.00	100.00	0.00	99.14	0.00	97.75	0.00	97.40	1.30	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2916013653
98.88	0.15	99.90	0.00	97.62	0.00	99.28	0.00	100.00	0.00	99.14	0.00	98.80	1.05	97.40	0.00	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3506971759
99.02	0.15	99.90	0.00	97.62	0.00	99.28	0.00	100.00	0.00	99.71	0.58	99.25	0.45	97.40	0.00	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1535244776
99.14	0.12	100.00	0.10	97.62	0.00	100.00	0.72	100.00	0.00	99.71	0.00	99.25	0.00	97.40	0.00	/workspace/coverage/default/1.sram_ctrl_ram_cfg.677413496
99.22	0.08	100.00	0.00	97.62	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.25	0.00	97.96	0.56	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.101631382
99.27	0.05	100.00	0.00	97.62	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.40	0.15	98.14	0.19	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.728065183
99.31	0.05	100.00	0.00	97.76	0.14	100.00	0.00	100.00	0.00	99.71	0.00	99.40	0.00	98.33	0.19	/workspace/coverage/default/14.sram_ctrl_lc_escalation.3230398179
99.36	0.04	100.00	0.00	97.76	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.70	0.30	98.33	0.00	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.798740807
99.40	0.04	100.00	0.00	98.04	0.28	100.00	0.00	100.00	0.00	99.71	0.00	99.70	0.00	98.33	0.00	/workspace/coverage/default/22.sram_ctrl_alert_test.2310426122
99.42	0.03	100.00	0.00	98.04	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3119769513
99.45	0.03	100.00	0.00	98.04	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.70	0.00	98.70	0.19	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.455317861
99.48	0.03	100.00	0.00	98.04	0.00	100.00	0.00	100.00	0.00	99.71	0.00	99.70	0.00	98.89	0.19	/workspace/coverage/default/10.sram_ctrl_regwen.1206961418

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4231555872
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1348930971
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1292373832
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2128646984
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.736851171
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2286431013
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2712823297
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.562237431
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.80389996
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4076274051
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2075668805
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1647189557
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2115627961
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2667725226
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.53175560
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3471251336
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.917271949
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2964509710
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.271592623
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1515336256
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.170174568
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3448553575
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2151991131
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.331930934
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3932652631
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2193301617
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3383178166
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1919553188
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1492151468
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4191298553
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3080009361
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1526251898
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.718146302
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3029857593
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3608760388
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2578432606
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3696479902
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.947262895
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3922443002
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2467351696
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2443777029
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2845705774
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2405862054
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.83142282
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3104100281
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2930402898
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3385480494
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2295507580
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3383007204
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.442762268
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1626549524
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.552842052
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1410317193
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3918853739
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.10528608
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1862094396
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1862947181
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1108227522
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1973405445
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4285756734
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4048955922
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3215804072
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2748985741
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4124257461
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3224755358
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4229041274
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1713007456
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4217699178
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1922488708
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2610667602
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3531854612
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2620982577
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.290520258
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3509893367
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.12144303
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1408928261
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2813996472
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2988089947
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1568037255
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2944861551
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2420207035
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2922613015
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2620472308
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4283700336
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.69784156
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2562456165
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3221286346
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1542448893
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1164085530
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2543660402
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2192560297
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2818217096
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.352686741
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2140033903
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.854678289
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2911593271
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2545749950
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1077476897
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4208930791
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2099781059
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3515545630
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.632958954
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.162012284
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3934649949
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1162379123
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2506073394
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.474048902
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1165385725
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2354485900
/workspace/coverage/default/0.sram_ctrl_alert_test.4060827692
/workspace/coverage/default/0.sram_ctrl_bijection.1972959667
/workspace/coverage/default/0.sram_ctrl_executable.3799542551
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1014073938
/workspace/coverage/default/0.sram_ctrl_max_throughput.2987358554
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.126748443
/workspace/coverage/default/0.sram_ctrl_mem_walk.1890897208
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2059982214
/workspace/coverage/default/0.sram_ctrl_partial_access.1384812514
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.413847898
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3006452015
/workspace/coverage/default/0.sram_ctrl_regwen.4283286834
/workspace/coverage/default/0.sram_ctrl_smoke.687024129
/workspace/coverage/default/0.sram_ctrl_stress_all.3553243648
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.218744799
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2139731568
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3395491598
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2837687726
/workspace/coverage/default/1.sram_ctrl_alert_test.763187379
/workspace/coverage/default/1.sram_ctrl_bijection.3619277715
/workspace/coverage/default/1.sram_ctrl_executable.1755793134
/workspace/coverage/default/1.sram_ctrl_lc_escalation.4246250235
/workspace/coverage/default/1.sram_ctrl_max_throughput.1192416767
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2764058708
/workspace/coverage/default/1.sram_ctrl_mem_walk.1728313648
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2481986522
/workspace/coverage/default/1.sram_ctrl_partial_access.1839348578
/workspace/coverage/default/1.sram_ctrl_regwen.2350900867
/workspace/coverage/default/1.sram_ctrl_sec_cm.3670059471
/workspace/coverage/default/1.sram_ctrl_smoke.3879743846
/workspace/coverage/default/1.sram_ctrl_stress_all.4187834102
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.702753806
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3239630978
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2469708995
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.504402048
/workspace/coverage/default/10.sram_ctrl_alert_test.3284464695
/workspace/coverage/default/10.sram_ctrl_bijection.1750366494
/workspace/coverage/default/10.sram_ctrl_executable.102640857
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3699617966
/workspace/coverage/default/10.sram_ctrl_max_throughput.133361617
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2850391570
/workspace/coverage/default/10.sram_ctrl_mem_walk.2980230562
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2762807154
/workspace/coverage/default/10.sram_ctrl_partial_access.2754506558
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2474644494
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1532067918
/workspace/coverage/default/10.sram_ctrl_smoke.968282570
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3872044686
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3764513567
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2763005995
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1792709808
/workspace/coverage/default/11.sram_ctrl_alert_test.3272802903
/workspace/coverage/default/11.sram_ctrl_bijection.571247060
/workspace/coverage/default/11.sram_ctrl_executable.824668509
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2774712465
/workspace/coverage/default/11.sram_ctrl_max_throughput.2830424839
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.289101693
/workspace/coverage/default/11.sram_ctrl_mem_walk.3665240835
/workspace/coverage/default/11.sram_ctrl_multiple_keys.470427819
/workspace/coverage/default/11.sram_ctrl_partial_access.1407550350
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4152663736
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3546851863
/workspace/coverage/default/11.sram_ctrl_regwen.1615324965
/workspace/coverage/default/11.sram_ctrl_smoke.3810537076
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2066278147
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.314732979
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.814143143
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1448725115
/workspace/coverage/default/12.sram_ctrl_alert_test.3627707517
/workspace/coverage/default/12.sram_ctrl_bijection.782700750
/workspace/coverage/default/12.sram_ctrl_executable.1450109096
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1576251970
/workspace/coverage/default/12.sram_ctrl_max_throughput.2793234623
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1933616439
/workspace/coverage/default/12.sram_ctrl_mem_walk.2023988695
/workspace/coverage/default/12.sram_ctrl_multiple_keys.689713224
/workspace/coverage/default/12.sram_ctrl_partial_access.801687270
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1857873131
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2935603776
/workspace/coverage/default/12.sram_ctrl_regwen.2835149610
/workspace/coverage/default/12.sram_ctrl_smoke.2523430071
/workspace/coverage/default/12.sram_ctrl_stress_all.1042492314
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2910032572
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.348471284
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1627754774
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3664397937
/workspace/coverage/default/13.sram_ctrl_alert_test.1103459348
/workspace/coverage/default/13.sram_ctrl_bijection.3873893954
/workspace/coverage/default/13.sram_ctrl_executable.3410048607
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4182211822
/workspace/coverage/default/13.sram_ctrl_max_throughput.1837833155
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1323817892
/workspace/coverage/default/13.sram_ctrl_mem_walk.583458629
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/workspace/coverage/default/44.sram_ctrl_lc_escalation.3919789391
/workspace/coverage/default/44.sram_ctrl_max_throughput.2511504690
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4081083635
/workspace/coverage/default/44.sram_ctrl_mem_walk.2974704447
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4115489894
/workspace/coverage/default/44.sram_ctrl_partial_access.4294522375
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2915218652
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3862798017
/workspace/coverage/default/44.sram_ctrl_regwen.2576975849
/workspace/coverage/default/44.sram_ctrl_smoke.3278108491
/workspace/coverage/default/44.sram_ctrl_stress_all.2666049615
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3552002973
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1393055158
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1910310784
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2436156514
/workspace/coverage/default/45.sram_ctrl_alert_test.3276661364
/workspace/coverage/default/45.sram_ctrl_bijection.3499661425
/workspace/coverage/default/45.sram_ctrl_executable.4061708011
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2547897478
/workspace/coverage/default/45.sram_ctrl_max_throughput.2164362504
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2989151587
/workspace/coverage/default/45.sram_ctrl_mem_walk.3298456999
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1413336376
/workspace/coverage/default/45.sram_ctrl_partial_access.2117987380
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3174147027
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3789564632
/workspace/coverage/default/45.sram_ctrl_regwen.2167429916
/workspace/coverage/default/45.sram_ctrl_smoke.2186185073
/workspace/coverage/default/45.sram_ctrl_stress_all.1376723724
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1683543594
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.700166572
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.148611750
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.525909462
/workspace/coverage/default/46.sram_ctrl_alert_test.3612137841
/workspace/coverage/default/46.sram_ctrl_bijection.2745444695
/workspace/coverage/default/46.sram_ctrl_executable.4122818235
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1817933127
/workspace/coverage/default/46.sram_ctrl_max_throughput.3811889467
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2445271353
/workspace/coverage/default/46.sram_ctrl_mem_walk.4011686266
/workspace/coverage/default/46.sram_ctrl_multiple_keys.374226124
/workspace/coverage/default/46.sram_ctrl_partial_access.3866618278
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.16753828
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3242723721
/workspace/coverage/default/46.sram_ctrl_regwen.3673278018
/workspace/coverage/default/46.sram_ctrl_smoke.4166858700
/workspace/coverage/default/46.sram_ctrl_stress_all.3592327455
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.208480561
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3988511049
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.52569927
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.520289972
/workspace/coverage/default/47.sram_ctrl_alert_test.3251752617
/workspace/coverage/default/47.sram_ctrl_bijection.862051033
/workspace/coverage/default/47.sram_ctrl_executable.2358953047
/workspace/coverage/default/47.sram_ctrl_lc_escalation.765151981
/workspace/coverage/default/47.sram_ctrl_max_throughput.3846397989
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1932351031
/workspace/coverage/default/47.sram_ctrl_mem_walk.3785500917
/workspace/coverage/default/47.sram_ctrl_multiple_keys.80479839
/workspace/coverage/default/47.sram_ctrl_partial_access.4157200239
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2531979904
/workspace/coverage/default/47.sram_ctrl_ram_cfg.461524898
/workspace/coverage/default/47.sram_ctrl_regwen.3537852530
/workspace/coverage/default/47.sram_ctrl_smoke.2636801121
/workspace/coverage/default/47.sram_ctrl_stress_all.3483372665
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.387237328
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3584240044
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.611735969
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1708987301
/workspace/coverage/default/48.sram_ctrl_alert_test.2951846892
/workspace/coverage/default/48.sram_ctrl_bijection.2349167056
/workspace/coverage/default/48.sram_ctrl_executable.3521737225
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1155385489
/workspace/coverage/default/48.sram_ctrl_max_throughput.822862418
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2812620434
/workspace/coverage/default/48.sram_ctrl_mem_walk.4051165230
/workspace/coverage/default/48.sram_ctrl_multiple_keys.375155190
/workspace/coverage/default/48.sram_ctrl_partial_access.436554543
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.793310136
/workspace/coverage/default/48.sram_ctrl_ram_cfg.103372656
/workspace/coverage/default/48.sram_ctrl_regwen.2895633114
/workspace/coverage/default/48.sram_ctrl_smoke.1179726893
/workspace/coverage/default/48.sram_ctrl_stress_all.873967457
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2793473411
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2328175398
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1919840424
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1535871433
/workspace/coverage/default/49.sram_ctrl_alert_test.1472761178
/workspace/coverage/default/49.sram_ctrl_bijection.2945609644
/workspace/coverage/default/49.sram_ctrl_executable.3433774899
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2597441773
/workspace/coverage/default/49.sram_ctrl_max_throughput.2841463524
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2767984588
/workspace/coverage/default/49.sram_ctrl_mem_walk.534765465
/workspace/coverage/default/49.sram_ctrl_multiple_keys.493365759
/workspace/coverage/default/49.sram_ctrl_partial_access.2804986713
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1167204879
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2902610798
/workspace/coverage/default/49.sram_ctrl_regwen.2678944115
/workspace/coverage/default/49.sram_ctrl_smoke.1640972778
/workspace/coverage/default/49.sram_ctrl_stress_all.3848009146
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3042135032
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3559614250
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1953481491
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.170460629
/workspace/coverage/default/5.sram_ctrl_alert_test.1965933739
/workspace/coverage/default/5.sram_ctrl_bijection.1108514898
/workspace/coverage/default/5.sram_ctrl_executable.2978670894
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2055189899
/workspace/coverage/default/5.sram_ctrl_max_throughput.291049069
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.795353809
/workspace/coverage/default/5.sram_ctrl_mem_walk.1873645535
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3070264944
/workspace/coverage/default/5.sram_ctrl_partial_access.3144376928
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3877528876
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3309562466
/workspace/coverage/default/5.sram_ctrl_regwen.185343531
/workspace/coverage/default/5.sram_ctrl_smoke.2441884415
/workspace/coverage/default/5.sram_ctrl_stress_all.3284275346
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2735371300
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1326489640
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2049506406
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.103692533
/workspace/coverage/default/6.sram_ctrl_alert_test.3232925087
/workspace/coverage/default/6.sram_ctrl_bijection.463987233
/workspace/coverage/default/6.sram_ctrl_executable.46684231
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2075217472
/workspace/coverage/default/6.sram_ctrl_max_throughput.2791646418
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1770647629
/workspace/coverage/default/6.sram_ctrl_mem_walk.3554139698
/workspace/coverage/default/6.sram_ctrl_multiple_keys.760894940
/workspace/coverage/default/6.sram_ctrl_partial_access.901346936
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.603803278
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1118542471
/workspace/coverage/default/6.sram_ctrl_regwen.1470883764
/workspace/coverage/default/6.sram_ctrl_smoke.2990965355
/workspace/coverage/default/6.sram_ctrl_stress_all.2014372446
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1209820299
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1026572326
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.562157693
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.410080951
/workspace/coverage/default/7.sram_ctrl_alert_test.4042825000
/workspace/coverage/default/7.sram_ctrl_bijection.2740578115
/workspace/coverage/default/7.sram_ctrl_executable.3183778425
/workspace/coverage/default/7.sram_ctrl_lc_escalation.943236325
/workspace/coverage/default/7.sram_ctrl_max_throughput.2697057936
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1000485058
/workspace/coverage/default/7.sram_ctrl_mem_walk.3018559706
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3631591924
/workspace/coverage/default/7.sram_ctrl_partial_access.933004921
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3308885832
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1192127281
/workspace/coverage/default/7.sram_ctrl_regwen.4255714751
/workspace/coverage/default/7.sram_ctrl_smoke.2985220328
/workspace/coverage/default/7.sram_ctrl_stress_all.444966616
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1775344457
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1429548212
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2531604600
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2038514345
/workspace/coverage/default/8.sram_ctrl_alert_test.860056293
/workspace/coverage/default/8.sram_ctrl_bijection.907624557
/workspace/coverage/default/8.sram_ctrl_executable.3558377479
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1263723478
/workspace/coverage/default/8.sram_ctrl_max_throughput.2467294700
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4234301860
/workspace/coverage/default/8.sram_ctrl_mem_walk.3361749438
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3689826928
/workspace/coverage/default/8.sram_ctrl_partial_access.744959624
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1367035268
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3831144877
/workspace/coverage/default/8.sram_ctrl_regwen.2460886978
/workspace/coverage/default/8.sram_ctrl_smoke.3954091236
/workspace/coverage/default/8.sram_ctrl_stress_all.382202475
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2848424565
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.945817002
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.678634125
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1808634357
/workspace/coverage/default/9.sram_ctrl_alert_test.1296338845
/workspace/coverage/default/9.sram_ctrl_bijection.1522821629
/workspace/coverage/default/9.sram_ctrl_executable.3285798207
/workspace/coverage/default/9.sram_ctrl_lc_escalation.539248932
/workspace/coverage/default/9.sram_ctrl_max_throughput.2330782126
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3765048794
/workspace/coverage/default/9.sram_ctrl_mem_walk.4064760089
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3625868732
/workspace/coverage/default/9.sram_ctrl_partial_access.467301897
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3059156720
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1378064886
/workspace/coverage/default/9.sram_ctrl_regwen.3840189267
/workspace/coverage/default/9.sram_ctrl_smoke.1871289648
/workspace/coverage/default/9.sram_ctrl_stress_all.989898351
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2994233190
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.608450022
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1672163508

Total test records in report: 1011

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1364619448	Feb 04 03:08:15 PM PST 24	Feb 04 03:14:38 PM PST 24	10264112422 ps
T2	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1922268348	Feb 04 03:13:30 PM PST 24	Feb 04 03:18:14 PM PST 24	3060743848 ps
T3	/workspace/coverage/default/12.sram_ctrl_bijection.782700750	Feb 04 03:07:05 PM PST 24	Feb 04 03:07:32 PM PST 24	18776178454 ps
T4	/workspace/coverage/default/14.sram_ctrl_lc_escalation.3230398179	Feb 04 03:08:04 PM PST 24	Feb 04 03:08:14 PM PST 24	723430115 ps
T5	/workspace/coverage/default/8.sram_ctrl_bijection.907624557	Feb 04 03:05:33 PM PST 24	Feb 04 03:06:36 PM PST 24	28846075531 ps
T8	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3701777451	Feb 04 03:03:09 PM PST 24	Feb 04 03:08:06 PM PST 24	1172962834 ps
T9	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1703415542	Feb 04 03:16:23 PM PST 24	Feb 04 03:16:32 PM PST 24	479439993 ps
T10	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.410080951	Feb 04 03:05:12 PM PST 24	Feb 04 03:08:23 PM PST 24	1999009993 ps
T11	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.728065183	Feb 04 03:01:41 PM PST 24	Feb 04 03:06:39 PM PST 24	4106760971 ps
T12	/workspace/coverage/default/42.sram_ctrl_smoke.264454771	Feb 04 03:16:53 PM PST 24	Feb 04 03:16:58 PM PST 24	47663481 ps
T15	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1975076023	Feb 04 03:03:10 PM PST 24	Feb 04 04:33:21 PM PST 24	3285149556 ps
T29	/workspace/coverage/default/21.sram_ctrl_ram_cfg.224791954	Feb 04 03:10:48 PM PST 24	Feb 04 03:10:49 PM PST 24	44320210 ps
T6	/workspace/coverage/default/10.sram_ctrl_lc_escalation.3699617966	Feb 04 03:06:27 PM PST 24	Feb 04 03:06:34 PM PST 24	933035302 ps
T16	/workspace/coverage/default/26.sram_ctrl_regwen.2388817593	Feb 04 03:12:23 PM PST 24	Feb 04 03:29:58 PM PST 24	2369030181 ps
T22	/workspace/coverage/default/31.sram_ctrl_alert_test.1352532269	Feb 04 03:14:04 PM PST 24	Feb 04 03:14:08 PM PST 24	19103129 ps
T52	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3023333348	Feb 04 03:14:04 PM PST 24	Feb 04 03:21:44 PM PST 24	18301349439 ps
T13	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1535244776	Feb 04 03:13:32 PM PST 24	Feb 04 03:46:05 PM PST 24	3308961255 ps
T53	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.4257856340	Feb 04 03:02:30 PM PST 24	Feb 04 03:02:35 PM PST 24	93001322 ps
T7	/workspace/coverage/default/34.sram_ctrl_lc_escalation.3292350005	Feb 04 03:14:48 PM PST 24	Feb 04 03:14:57 PM PST 24	315094980 ps
T54	/workspace/coverage/default/6.sram_ctrl_max_throughput.2791646418	Feb 04 03:04:42 PM PST 24	Feb 04 03:05:58 PM PST 24	124739769 ps
T63	/workspace/coverage/default/0.sram_ctrl_multiple_keys.2059982214	Feb 04 03:00:43 PM PST 24	Feb 04 03:06:02 PM PST 24	5620018794 ps
T142	/workspace/coverage/default/19.sram_ctrl_smoke.3610233225	Feb 04 03:09:31 PM PST 24	Feb 04 03:09:47 PM PST 24	1539052060 ps
T143	/workspace/coverage/default/0.sram_ctrl_bijection.1972959667	Feb 04 03:00:44 PM PST 24	Feb 04 03:01:27 PM PST 24	10841013268 ps
T144	/workspace/coverage/default/14.sram_ctrl_partial_access.1371332014	Feb 04 03:08:05 PM PST 24	Feb 04 03:08:28 PM PST 24	4248585762 ps
T14	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3271018112	Feb 04 03:14:47 PM PST 24	Feb 04 04:41:20 PM PST 24	2508723113 ps
T64	/workspace/coverage/default/25.sram_ctrl_regwen.3060498396	Feb 04 03:11:58 PM PST 24	Feb 04 03:39:40 PM PST 24	11647609226 ps
T104	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1676831301	Feb 04 03:11:30 PM PST 24	Feb 04 03:13:43 PM PST 24	1370451318 ps
T114	/workspace/coverage/default/37.sram_ctrl_mem_walk.228288572	Feb 04 03:15:39 PM PST 24	Feb 04 03:15:50 PM PST 24	606345536 ps
T115	/workspace/coverage/default/42.sram_ctrl_partial_access.2825202720	Feb 04 03:16:59 PM PST 24	Feb 04 03:17:20 PM PST 24	990657114 ps
T116	/workspace/coverage/default/40.sram_ctrl_smoke.3899357881	Feb 04 03:16:25 PM PST 24	Feb 04 03:16:51 PM PST 24	298740675 ps
T145	/workspace/coverage/default/21.sram_ctrl_smoke.2302669248	Feb 04 03:10:16 PM PST 24	Feb 04 03:11:29 PM PST 24	1525806992 ps
T105	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1167204879	Feb 04 03:19:12 PM PST 24	Feb 04 03:24:14 PM PST 24	4322571100 ps
T146	/workspace/coverage/default/32.sram_ctrl_multiple_keys.4270180001	Feb 04 03:14:06 PM PST 24	Feb 04 03:15:39 PM PST 24	5269249726 ps
T147	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.950134418	Feb 04 03:12:12 PM PST 24	Feb 04 03:12:19 PM PST 24	74874190 ps
T30	/workspace/coverage/default/23.sram_ctrl_ram_cfg.707191465	Feb 04 03:11:29 PM PST 24	Feb 04 03:11:31 PM PST 24	88237394 ps
T82	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2934670467	Feb 04 03:15:57 PM PST 24	Feb 04 03:16:00 PM PST 24	163838223 ps
T106	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.834210148	Feb 04 03:15:00 PM PST 24	Feb 04 03:18:58 PM PST 24	2500137123 ps
T111	/workspace/coverage/default/10.sram_ctrl_regwen.1206961418	Feb 04 03:06:28 PM PST 24	Feb 04 03:21:39 PM PST 24	34687141068 ps
T83	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2870829543	Feb 04 03:11:43 PM PST 24	Feb 04 03:11:49 PM PST 24	93481164 ps
T25	/workspace/coverage/default/20.sram_ctrl_stress_all.4003258043	Feb 04 03:10:21 PM PST 24	Feb 04 04:49:08 PM PST 24	57013690187 ps
T136	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1912180123	Feb 04 03:13:19 PM PST 24	Feb 04 03:24:12 PM PST 24	263739004738 ps
T128	/workspace/coverage/default/10.sram_ctrl_executable.102640857	Feb 04 03:06:26 PM PST 24	Feb 04 03:26:24 PM PST 24	10790024811 ps
T23	/workspace/coverage/default/8.sram_ctrl_alert_test.860056293	Feb 04 03:06:05 PM PST 24	Feb 04 03:06:08 PM PST 24	28390848 ps
T27	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2075217472	Feb 04 03:04:40 PM PST 24	Feb 04 03:04:51 PM PST 24	1005899053 ps
T31	/workspace/coverage/default/3.sram_ctrl_ram_cfg.3253664892	Feb 04 03:03:07 PM PST 24	Feb 04 03:03:13 PM PST 24	122260979 ps
T148	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3406614767	Feb 04 03:08:27 PM PST 24	Feb 04 03:14:11 PM PST 24	39556590151 ps
T149	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3239630978	Feb 04 03:01:32 PM PST 24	Feb 04 03:05:16 PM PST 24	13667673558 ps
T150	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3762397889	Feb 04 03:08:11 PM PST 24	Feb 04 03:11:22 PM PST 24	1967691107 ps
T151	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1600133491	Feb 04 03:08:04 PM PST 24	Feb 04 03:09:06 PM PST 24	485129772 ps
T152	/workspace/coverage/default/7.sram_ctrl_multiple_keys.3631591924	Feb 04 03:04:55 PM PST 24	Feb 04 03:07:15 PM PST 24	1426144512 ps
T153	/workspace/coverage/default/26.sram_ctrl_max_throughput.3267976153	Feb 04 03:12:17 PM PST 24	Feb 04 03:12:19 PM PST 24	39258593 ps
T129	/workspace/coverage/default/38.sram_ctrl_regwen.3449434046	Feb 04 03:15:51 PM PST 24	Feb 04 03:30:42 PM PST 24	17973062950 ps
T154	/workspace/coverage/default/22.sram_ctrl_smoke.2509505305	Feb 04 03:10:42 PM PST 24	Feb 04 03:10:53 PM PST 24	466239188 ps
T139	/workspace/coverage/default/45.sram_ctrl_multiple_keys.1413336376	Feb 04 03:17:58 PM PST 24	Feb 04 03:19:27 PM PST 24	7211994491 ps
T155	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1841119208	Feb 04 03:14:05 PM PST 24	Feb 04 03:16:43 PM PST 24	3228636561 ps
T140	/workspace/coverage/default/6.sram_ctrl_smoke.2990965355	Feb 04 03:04:08 PM PST 24	Feb 04 03:05:29 PM PST 24	1990765635 ps
T156	/workspace/coverage/default/17.sram_ctrl_bijection.2548667391	Feb 04 03:08:57 PM PST 24	Feb 04 03:10:23 PM PST 24	5690258219 ps
T45	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1683543594	Feb 04 03:18:12 PM PST 24	Feb 04 04:30:05 PM PST 24	4300514117 ps
T28	/workspace/coverage/default/8.sram_ctrl_lc_escalation.1263723478	Feb 04 03:05:33 PM PST 24	Feb 04 03:05:44 PM PST 24	2659211060 ps
T84	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4077476156	Feb 04 03:08:12 PM PST 24	Feb 04 03:08:23 PM PST 24	126861063 ps
T157	/workspace/coverage/default/28.sram_ctrl_mem_walk.1021586466	Feb 04 03:13:05 PM PST 24	Feb 04 03:13:13 PM PST 24	97416992 ps
T158	/workspace/coverage/default/47.sram_ctrl_max_throughput.3846397989	Feb 04 03:18:45 PM PST 24	Feb 04 03:20:31 PM PST 24	467367799 ps
T26	/workspace/coverage/default/31.sram_ctrl_stress_all.4098224434	Feb 04 03:14:03 PM PST 24	Feb 04 03:49:30 PM PST 24	256859457155 ps
T127	/workspace/coverage/default/30.sram_ctrl_executable.3655785922	Feb 04 03:13:30 PM PST 24	Feb 04 03:23:47 PM PST 24	39622153853 ps
T159	/workspace/coverage/default/17.sram_ctrl_max_throughput.1848890775	Feb 04 03:09:10 PM PST 24	Feb 04 03:10:07 PM PST 24	186069879 ps
T160	/workspace/coverage/default/10.sram_ctrl_mem_walk.2980230562	Feb 04 03:06:33 PM PST 24	Feb 04 03:06:43 PM PST 24	1755639479 ps
T161	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4212180218	Feb 04 03:12:08 PM PST 24	Feb 04 03:14:53 PM PST 24	531461275 ps
T135	/workspace/coverage/default/39.sram_ctrl_executable.337354021	Feb 04 03:16:23 PM PST 24	Feb 04 03:17:36 PM PST 24	9977343842 ps
T17	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2244755497	Feb 04 03:16:51 PM PST 24	Feb 04 03:19:59 PM PST 24	4227230254 ps
T21	/workspace/coverage/default/10.sram_ctrl_stress_all.1716265083	Feb 04 03:06:36 PM PST 24	Feb 04 03:43:32 PM PST 24	106071512527 ps
T162	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1352601037	Feb 04 03:13:29 PM PST 24	Feb 04 03:13:33 PM PST 24	112555280 ps
T46	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1566793577	Feb 04 03:13:18 PM PST 24	Feb 04 03:46:37 PM PST 24	2041024810 ps
T47	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2848424565	Feb 04 03:05:40 PM PST 24	Feb 04 03:21:21 PM PST 24	172490112 ps
T24	/workspace/coverage/default/33.sram_ctrl_alert_test.4220879411	Feb 04 03:14:28 PM PST 24	Feb 04 03:14:30 PM PST 24	175928511 ps
T163	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2039837852	Feb 04 03:08:12 PM PST 24	Feb 04 03:08:26 PM PST 24	261459119 ps
T164	/workspace/coverage/default/30.sram_ctrl_smoke.3598164256	Feb 04 03:13:18 PM PST 24	Feb 04 03:13:28 PM PST 24	513610268 ps
T165	/workspace/coverage/default/30.sram_ctrl_mem_walk.125161587	Feb 04 03:13:29 PM PST 24	Feb 04 03:13:35 PM PST 24	533566231 ps
T166	/workspace/coverage/default/31.sram_ctrl_regwen.4129600395	Feb 04 03:13:56 PM PST 24	Feb 04 03:19:11 PM PST 24	413428442 ps
T130	/workspace/coverage/default/6.sram_ctrl_executable.46684231	Feb 04 03:04:40 PM PST 24	Feb 04 03:21:47 PM PST 24	53033299623 ps
T48	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.327802655	Feb 04 03:09:14 PM PST 24	Feb 04 03:27:33 PM PST 24	293453133 ps
T167	/workspace/coverage/default/33.sram_ctrl_ram_cfg.4278591903	Feb 04 03:14:35 PM PST 24	Feb 04 03:14:37 PM PST 24	43238690 ps
T168	/workspace/coverage/default/0.sram_ctrl_max_throughput.2987358554	Feb 04 03:00:52 PM PST 24	Feb 04 03:02:03 PM PST 24	101285030 ps
T169	/workspace/coverage/default/22.sram_ctrl_partial_access.3622599208	Feb 04 03:10:49 PM PST 24	Feb 04 03:10:59 PM PST 24	609534511 ps
T170	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2469708995	Feb 04 03:01:41 PM PST 24	Feb 04 03:02:34 PM PST 24	120751779 ps
T171	/workspace/coverage/default/24.sram_ctrl_bijection.2961684323	Feb 04 03:11:30 PM PST 24	Feb 04 03:11:59 PM PST 24	924356811 ps
T172	/workspace/coverage/default/22.sram_ctrl_bijection.353115178	Feb 04 03:10:47 PM PST 24	Feb 04 03:12:01 PM PST 24	14338122848 ps
T173	/workspace/coverage/default/35.sram_ctrl_max_throughput.4026230681	Feb 04 03:14:59 PM PST 24	Feb 04 03:17:06 PM PST 24	142880842 ps
T85	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1792709808	Feb 04 03:06:49 PM PST 24	Feb 04 03:14:30 PM PST 24	10572688717 ps
T174	/workspace/coverage/default/40.sram_ctrl_mem_walk.4086548624	Feb 04 03:16:24 PM PST 24	Feb 04 03:16:36 PM PST 24	544511990 ps
T175	/workspace/coverage/default/13.sram_ctrl_mem_walk.583458629	Feb 04 03:07:26 PM PST 24	Feb 04 03:07:32 PM PST 24	295439194 ps
T176	/workspace/coverage/default/43.sram_ctrl_smoke.1638922010	Feb 04 03:17:14 PM PST 24	Feb 04 03:18:13 PM PST 24	1797514372 ps
T49	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1000625277	Feb 04 03:14:36 PM PST 24	Feb 04 04:08:44 PM PST 24	151451374 ps
T177	/workspace/coverage/default/35.sram_ctrl_smoke.1978572845	Feb 04 03:14:48 PM PST 24	Feb 04 03:15:04 PM PST 24	2807662736 ps
T178	/workspace/coverage/default/7.sram_ctrl_lc_escalation.943236325	Feb 04 03:05:12 PM PST 24	Feb 04 03:05:16 PM PST 24	244656808 ps
T179	/workspace/coverage/default/28.sram_ctrl_smoke.832315999	Feb 04 03:12:34 PM PST 24	Feb 04 03:13:21 PM PST 24	847507423 ps
T134	/workspace/coverage/default/49.sram_ctrl_regwen.2678944115	Feb 04 03:19:35 PM PST 24	Feb 04 03:33:20 PM PST 24	6726730361 ps
T100	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.798740807	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:44 PM PST 24	37209897 ps
T50	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4208930791	Feb 04 12:49:46 PM PST 24	Feb 04 12:49:48 PM PST 24	140643543 ps
T42	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1526251898	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:48 PM PST 24	292662856 ps
T101	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3509893367	Feb 04 12:49:22 PM PST 24	Feb 04 12:49:25 PM PST 24	65801793 ps
T55	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1108227522	Feb 04 12:49:50 PM PST 24	Feb 04 12:49:52 PM PST 24	12406513 ps
T56	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.83142282	Feb 04 12:49:36 PM PST 24	Feb 04 12:49:41 PM PST 24	93724018 ps
T51	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1077476897	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:32 PM PST 24	143804574 ps
T43	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4053080260	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:46 PM PST 24	180839429 ps
T57	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2192560297	Feb 04 12:49:25 PM PST 24	Feb 04 12:49:28 PM PST 24	31833670 ps
T58	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3221286346	Feb 04 12:49:15 PM PST 24	Feb 04 12:49:18 PM PST 24	19900815 ps
T59	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2506073394	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	34282880 ps
T60	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4191298553	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:45 PM PST 24	31464392 ps
T61	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2405862054	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:46 PM PST 24	26019023 ps
T62	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4285756734	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:50 PM PST 24	78771478 ps
T102	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1348930971	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:29 PM PST 24	466023080 ps
T103	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.290520258	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:31 PM PST 24	39723771 ps
T44	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.562237431	Feb 04 12:49:22 PM PST 24	Feb 04 12:49:27 PM PST 24	74174732 ps
T110	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2964509710	Feb 04 12:49:37 PM PST 24	Feb 04 12:49:42 PM PST 24	33440408 ps
T107	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3104100281	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:47 PM PST 24	24806957 ps
T65	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3029857593	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:50 PM PST 24	42522204 ps
T112	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2443777029	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:50 PM PST 24	468170775 ps
T108	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2818217096	Feb 04 12:49:15 PM PST 24	Feb 04 12:49:17 PM PST 24	45819030 ps
T109	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1973405445	Feb 04 12:49:46 PM PST 24	Feb 04 12:49:48 PM PST 24	56019516 ps
T113	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2578432606	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:48 PM PST 24	52709366 ps
T66	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2099781059	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	15692917 ps
T67	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3515545630	Feb 04 12:49:34 PM PST 24	Feb 04 12:49:36 PM PST 24	40883983 ps
T180	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3383178166	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:48 PM PST 24	339514280 ps
T181	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2543660402	Feb 04 12:49:21 PM PST 24	Feb 04 12:49:25 PM PST 24	130313487 ps
T182	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3918853739	Feb 04 12:49:50 PM PST 24	Feb 04 12:49:52 PM PST 24	59647937 ps
T183	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.53175560	Feb 04 12:49:17 PM PST 24	Feb 04 12:49:21 PM PST 24	62230634 ps
T184	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3215804072	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:31 PM PST 24	55155341 ps
T185	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1410317193	Feb 04 12:49:46 PM PST 24	Feb 04 12:49:48 PM PST 24	38892770 ps
T186	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1919553188	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	114821957 ps
T187	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.917271949	Feb 04 12:49:37 PM PST 24	Feb 04 12:49:43 PM PST 24	83043790 ps
T188	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3608760388	Feb 04 12:49:40 PM PST 24	Feb 04 12:49:43 PM PST 24	81983759 ps
T120	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2845705774	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:49 PM PST 24	620619710 ps
T189	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.69784156	Feb 04 12:49:17 PM PST 24	Feb 04 12:49:20 PM PST 24	30281684 ps
T190	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2193301617	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:45 PM PST 24	21929481 ps
T68	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2988089947	Feb 04 12:49:22 PM PST 24	Feb 04 12:49:27 PM PST 24	42507071 ps
T92	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3471251336	Feb 04 12:49:25 PM PST 24	Feb 04 12:49:29 PM PST 24	516011594 ps
T93	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.10528608	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:50 PM PST 24	227036559 ps
T94	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.162012284	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:44 PM PST 24	1802746797 ps
T95	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.101631382	Feb 04 12:49:32 PM PST 24	Feb 04 12:49:36 PM PST 24	149205774 ps
T96	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4217699178	Feb 04 12:49:30 PM PST 24	Feb 04 12:49:34 PM PST 24	384230868 ps
T191	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.474048902	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:49 PM PST 24	45073739 ps
T69	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4231555872	Feb 04 12:49:25 PM PST 24	Feb 04 12:49:28 PM PST 24	17760819 ps
T73	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2467351696	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:46 PM PST 24	48835055 ps
T74	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.718146302	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:47 PM PST 24	46581383 ps
T75	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2712823297	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:25 PM PST 24	288790409 ps
T76	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3531854612	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:31 PM PST 24	33330594 ps
T77	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.331930934	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:50 PM PST 24	311803680 ps
T78	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2286431013	Feb 04 12:49:21 PM PST 24	Feb 04 12:49:24 PM PST 24	28397948 ps
T79	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2140033903	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:30 PM PST 24	4271871136 ps
T80	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.632958954	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:48 PM PST 24	80941387 ps
T81	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.736851171	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:22 PM PST 24	42672745 ps
T192	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2075668805	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:22 PM PST 24	13005061 ps
T193	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1542448893	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:29 PM PST 24	28189790 ps
T70	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3448553575	Feb 04 12:49:37 PM PST 24	Feb 04 12:49:43 PM PST 24	22477621 ps
T194	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4229041274	Feb 04 12:49:17 PM PST 24	Feb 04 12:49:19 PM PST 24	20943583 ps
T195	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.12144303	Feb 04 12:49:18 PM PST 24	Feb 04 12:49:23 PM PST 24	59263952 ps
T117	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2916013653	Feb 04 12:49:40 PM PST 24	Feb 04 12:49:44 PM PST 24	136932139 ps
T196	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.271592623	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:48 PM PST 24	130624783 ps
T71	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1492151468	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:45 PM PST 24	18174665 ps
T98	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2545749950	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	17045383 ps
T121	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1408928261	Feb 04 12:49:21 PM PST 24	Feb 04 12:49:25 PM PST 24	165645736 ps
T197	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2813996472	Feb 04 12:49:20 PM PST 24	Feb 04 12:49:23 PM PST 24	28131834 ps
T198	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3385480494	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:51 PM PST 24	83225588 ps
T72	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3506971759	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:31 PM PST 24	28765871 ps
T99	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1713007456	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:34 PM PST 24	76000303 ps
T199	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2944861551	Feb 04 12:49:22 PM PST 24	Feb 04 12:49:26 PM PST 24	110297616 ps
T200	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2922613015	Feb 04 12:49:22 PM PST 24	Feb 04 12:49:25 PM PST 24	33432212 ps
T201	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2128646984	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:34 PM PST 24	264568774 ps
T202	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4076274051	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:34 PM PST 24	132356950 ps
T203	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.854678289	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:51 PM PST 24	90440384 ps
T86	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2911593271	Feb 04 12:49:40 PM PST 24	Feb 04 12:49:43 PM PST 24	21873049 ps
T204	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2620472308	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:26 PM PST 24	130848736 ps
T205	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3922443002	Feb 04 12:49:36 PM PST 24	Feb 04 12:49:42 PM PST 24	12376207 ps
T206	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.352686741	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:24 PM PST 24	355750270 ps
T122	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3119769513	Feb 04 12:49:47 PM PST 24	Feb 04 12:49:51 PM PST 24	208318652 ps
T87	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2295507580	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:47 PM PST 24	17404863 ps
T207	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3080009361	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:48 PM PST 24	75114983 ps
T208	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1862094396	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:51 PM PST 24	169941904 ps
T209	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.170174568	Feb 04 12:49:37 PM PST 24	Feb 04 12:49:43 PM PST 24	24427383 ps
T210	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1862947181	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:48 PM PST 24	35901415 ps
T211	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2610667602	Feb 04 12:49:23 PM PST 24	Feb 04 12:49:28 PM PST 24	66944482 ps
T212	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1515336256	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	33617535 ps
T213	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3383007204	Feb 04 12:49:50 PM PST 24	Feb 04 12:49:52 PM PST 24	155903045 ps
T214	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.442762268	Feb 04 12:49:51 PM PST 24	Feb 04 12:49:57 PM PST 24	482186612 ps
T215	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.552842052	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:48 PM PST 24	52377781 ps
T88	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2420207035	Feb 04 12:49:18 PM PST 24	Feb 04 12:49:21 PM PST 24	14759814 ps
T216	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3934649949	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:43 PM PST 24	27857230 ps
T118	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4283700336	Feb 04 12:49:15 PM PST 24	Feb 04 12:49:18 PM PST 24	543261080 ps
T217	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1647189557	Feb 04 12:49:23 PM PST 24	Feb 04 12:49:28 PM PST 24	124590437 ps
T218	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1162379123	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:45 PM PST 24	23631373 ps
T219	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2115627961	Feb 04 12:49:14 PM PST 24	Feb 04 12:49:17 PM PST 24	12688756 ps
T125	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.455317861	Feb 04 12:49:43 PM PST 24	Feb 04 12:49:48 PM PST 24	753811448 ps
T220	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2151991131	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:47 PM PST 24	78167652 ps
T221	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2930402898	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:44 PM PST 24	23247902 ps
T222	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4124257461	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:32 PM PST 24	23119129 ps
T124	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4048955922	Feb 04 12:49:46 PM PST 24	Feb 04 12:49:49 PM PST 24	468759047 ps
T223	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.80389996	Feb 04 12:49:16 PM PST 24	Feb 04 12:49:19 PM PST 24	15979874 ps
T224	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1164085530	Feb 04 12:49:21 PM PST 24	Feb 04 12:49:25 PM PST 24	248062870 ps
T119	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1165385725	Feb 04 12:49:38 PM PST 24	Feb 04 12:49:43 PM PST 24	197343872 ps
T123	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3696479902	Feb 04 12:49:44 PM PST 24	Feb 04 12:49:48 PM PST 24	84384423 ps
T225	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1922488708	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:31 PM PST 24	12707738 ps
T89	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1568037255	Feb 04 12:49:21 PM PST 24	Feb 04 12:49:24 PM PST 24	18823934 ps
T226	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.947262895	Feb 04 12:49:37 PM PST 24	Feb 04 12:49:44 PM PST 24	121388518 ps
T90	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3224755358	Feb 04 12:49:19 PM PST 24	Feb 04 12:49:22 PM PST 24	14193396 ps
T227	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2562456165	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:27 PM PST 24	13305278 ps
T126	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1626549524	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:51 PM PST 24	966297393 ps
T97	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2748985741	Feb 04 12:49:29 PM PST 24	Feb 04 12:49:32 PM PST 24	86966653 ps
T228	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2620982577	Feb 04 12:49:25 PM PST 24	Feb 04 12:49:28 PM PST 24	131876901 ps
T229	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2667725226	Feb 04 12:49:20 PM PST 24	Feb 04 12:49:24 PM PST 24	33135043 ps
T230	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3932652631	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:45 PM PST 24	16140981 ps
T231	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1292373832	Feb 04 12:49:24 PM PST 24	Feb 04 12:49:28 PM PST 24	37238759 ps
T91	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2989151587	Feb 04 03:18:09 PM PST 24	Feb 04 03:18:18 PM PST 24	92929051 ps
T232	/workspace/coverage/default/34.sram_ctrl_multiple_keys.1744407643	Feb 04 03:14:40 PM PST 24	Feb 04 03:27:02 PM PST 24	3150282442 ps
T233	/workspace/coverage/default/21.sram_ctrl_stress_all.1245935510	Feb 04 03:10:41 PM PST 24	Feb 04 03:42:20 PM PST 24	77000187236 ps
T234	/workspace/coverage/default/41.sram_ctrl_ram_cfg.2740365410	Feb 04 03:16:52 PM PST 24	Feb 04 03:16:54 PM PST 24	25847585 ps
T133	/workspace/coverage/default/43.sram_ctrl_stress_all.4268150532	Feb 04 03:17:33 PM PST 24	Feb 04 04:50:00 PM PST 24	68233098411 ps
T235	/workspace/coverage/default/13.sram_ctrl_ram_cfg.2855181301	Feb 04 03:07:31 PM PST 24	Feb 04 03:07:36 PM PST 24	49479240 ps
T236	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.678634125	Feb 04 03:05:36 PM PST 24	Feb 04 03:07:38 PM PST 24	584582958 ps
T237	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3469439406	Feb 04 03:10:40 PM PST 24	Feb 04 04:39:52 PM PST 24	2156845730 ps
T238	/workspace/coverage/default/28.sram_ctrl_partial_access.396596315	Feb 04 03:13:07 PM PST 24	Feb 04 03:13:23 PM PST 24	2072463779 ps
T239	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3765048794	Feb 04 03:06:13 PM PST 24	Feb 04 03:06:17 PM PST 24	86704065 ps
T240	/workspace/coverage/default/40.sram_ctrl_alert_test.3144189319	Feb 04 03:16:34 PM PST 24	Feb 04 03:16:36 PM PST 24	38775133 ps
T241	/workspace/coverage/default/32.sram_ctrl_mem_walk.1433203922	Feb 04 03:14:04 PM PST 24	Feb 04 03:14:12 PM PST 24	238856314 ps
T242	/workspace/coverage/default/3.sram_ctrl_executable.906966650	Feb 04 03:03:07 PM PST 24	Feb 04 03:04:46 PM PST 24	1910064751 ps
T131	/workspace/coverage/default/17.sram_ctrl_stress_all.1852948915	Feb 04 03:09:14 PM PST 24	Feb 04 04:46:06 PM PST 24	225099564983 ps
T243	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1320250412	Feb 04 03:09:16 PM PST 24	Feb 04 03:11:42 PM PST 24	309300853 ps
T244	/workspace/coverage/default/44.sram_ctrl_multiple_keys.4115489894	Feb 04 03:17:52 PM PST 24	Feb 04 03:33:25 PM PST 24	27182854408 ps
T245	/workspace/coverage/default/33.sram_ctrl_smoke.2283997761	Feb 04 03:14:17 PM PST 24	Feb 04 03:14:30 PM PST 24	483102250 ps
T246	/workspace/coverage/default/0.sram_ctrl_regwen.4283286834	Feb 04 03:01:19 PM PST 24	Feb 04 03:11:26 PM PST 24	1757743037 ps
T247	/workspace/coverage/default/31.sram_ctrl_ram_cfg.2982804960	Feb 04 03:13:53 PM PST 24	Feb 04 03:13:55 PM PST 24	101236501 ps
T248	/workspace/coverage/default/39.sram_ctrl_stress_all.1943327245	Feb 04 03:16:23 PM PST 24	Feb 04 03:48:12 PM PST 24	189315522376 ps
T249	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1429548212	Feb 04 03:04:54 PM PST 24	Feb 04 03:08:07 PM PST 24	7749140691 ps
T250	/workspace/coverage/default/19.sram_ctrl_partial_access.2981429762	Feb 04 03:09:38 PM PST 24	Feb 04 03:10:00 PM PST 24	1093957764 ps
T251	/workspace/coverage/default/47.sram_ctrl_mem_walk.3785500917	Feb 04 03:18:45 PM PST 24	Feb 04 03:18:59 PM PST 24	1839162260 ps
T252	/workspace/coverage/default/15.sram_ctrl_executable.4112221460	Feb 04 03:08:27 PM PST 24	Feb 04 03:31:47 PM PST 24	9631765041 ps
T253	/workspace/coverage/default/5.sram_ctrl_multiple_keys.3070264944	Feb 04 03:03:49 PM PST 24	Feb 04 03:26:39 PM PST 24	65178786639 ps
T254	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.517852438	Feb 04 03:08:49 PM PST 24	Feb 04 03:13:02 PM PST 24	168372063270 ps
T255	/workspace/coverage/default/18.sram_ctrl_max_throughput.2392514323	Feb 04 03:09:17 PM PST 24	Feb 04 03:10:53 PM PST 24	143025332 ps
T256	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3872044686	Feb 04 03:06:33 PM PST 24	Feb 04 03:36:11 PM PST 24	3166443306 ps
T141	/workspace/coverage/default/2.sram_ctrl_regwen.2723109633	Feb 04 03:02:18 PM PST 24	Feb 04 03:23:48 PM PST 24	33603175283 ps
T257	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4260855380	Feb 04 03:09:50 PM PST 24	Feb 04 03:29:45 PM PST 24	28524671820 ps
T258	/workspace/coverage/default/5.sram_ctrl_alert_test.1965933739	Feb 04 03:04:10 PM PST 24	Feb 04 03:04:11 PM PST 24	27402681 ps
T259	/workspace/coverage/default/33.sram_ctrl_partial_access.1868230628	Feb 04 03:14:19 PM PST 24	Feb 04 03:14:30 PM PST 24	178450058 ps
T260	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1153097092	Feb 04 03:11:22 PM PST 24	Feb 04 03:20:03 PM PST 24	1916797141 ps
T261	/workspace/coverage/default/19.sram_ctrl_multiple_keys.718840672	Feb 04 03:09:39 PM PST 24	Feb 04 03:30:55 PM PST 24	30731212578 ps
T262	/workspace/coverage/default/18.sram_ctrl_mem_walk.3717080334	Feb 04 03:09:36 PM PST 24	Feb 04 03:09:47 PM PST 24	230130814 ps
T263	/workspace/coverage/default/16.sram_ctrl_bijection.1316544944	Feb 04 03:08:27 PM PST 24	Feb 04 03:09:09 PM PST 24	2355280303 ps
T264	/workspace/coverage/default/1.sram_ctrl_bijection.3619277715	Feb 04 03:01:32 PM PST 24	Feb 04 03:02:07 PM PST 24	1838232847 ps
T265	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3552002973	Feb 04 03:18:00 PM PST 24	Feb 04 03:54:01 PM PST 24	223334605 ps
T266	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1740884294	Feb 04 03:09:27 PM PST 24	Feb 04 03:09:33 PM PST 24	370807624 ps