Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44113605	1			T1	47440		T2	233104		T3	12288
triple_byte_access	2615990	1			T1	42945		T2	4467		T4	2
halfword_access	3927955	1			T1	64120		T2	6970		T4	9
byte_access	5240733	1			T1	85402		T2	9229		T4	6
zero_access	1317436	1			T1	21352		T2	2361		T4	4

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28556035

1

T1

130382

T2

128603

T3

6144

auto[1]

28659684

1

T1

130877

T2

127528

T3

6144

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22007289	1			T1	23644		T2	117070		T3	6144
auto[0]	triple_byte_access	1305195	1			T1	21597		T2	2216		T8	561
auto[0]	halfword_access	1959487	1			T1	32010		T2	3479		T4	8
auto[0]	byte_access	2621573	1			T1	42544		T2	4600		T4	2
auto[0]	zero_access	662491	1			T1	10587		T2	1238		T4	1
auto[1]	word_access	22106316	1			T1	23796		T2	116034		T3	6144
auto[1]	triple_byte_access	1310795	1			T1	21348		T2	2251		T4	2
auto[1]	halfword_access	1968468	1			T1	32110		T2	3491		T4	1
auto[1]	byte_access	2619160	1			T1	42858		T2	4629		T4	4
auto[1]	zero_access	654945	1			T1	10765		T2	1123		T4	3