Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142674408	1			T1	11298		T2	4058		T3	300534
instr_valid_dis	115969892	1			T1	11298		T2	4058		T3	300534
instr_en	17482454	1			T10	34976		T12	152160		T126	10662

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9246281	1			T10	72692		T12	58282		T126	94878
sram_ifetch_valid_disable	113303901	1			T1	11298		T2	4058		T3	300534
sram_ifetch_enable	20124226	1			T10	129650		T12	38662		T126	59594

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142674408	1			T1	11298		T2	4058		T3	300534
hw_debug_en_valid_off	112223755	1			T1	11298		T2	4058		T3	300534
hw_debug_en_on	21090065	1			T10	173198		T12	129122		T13	531

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113303901	1			T1	11298		T2	4058		T3	300534
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102010644	1			T1	11298		T2	4058		T3	300534
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7514897	1			T10	20602		T12	70840		T30	492
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3543677	1			T10	14048		T126	73246		T27	175030
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1403512	1			T10	14048		T126	73246		T22	57232
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1485977	1			T27	94924		T44	4120		T131	18368
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3717884	1			T10	58644		T12	58282		T126	17128
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1954148	1			T10	58644		T12	15624		T126	17128
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1163360	1			T12	42658		T135	512		T143	12182
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8798752	1			T10	94554		T12	70840		T13	531
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3818057	1			T10	94554		T13	531		T126	38184
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3651686	1			T12	70840		T131	107122		T127	44302

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6711978	1			T10	14374		T12	38662		T126	10662
lc_exec_en	8573429	1			T10	20000		T126	33240		T26	78354
valid_exec_dis	110184387	1			T1	11298		T2	4058		T3	300534
invalid_exec_dis	29370507	1			T10	202342		T12	96944		T126	154472