Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.576284167 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.802317895 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1617863724 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1198617174 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.762053898 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.761055239 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2732801635 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2478843014 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3084573537 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1162237404 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2315017707 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2440879776 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3114310085 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1978980231 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3951766829 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3890445332 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2373787428 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2435470069 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3028111244 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1762296829 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2656639765 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3500244555 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.82368774 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.828479626 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3111890787 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.480347385 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3560536785 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1973290313 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2117988025 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2046150277 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3085707682 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2392069357 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1872769048 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1271165510 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2576028297 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2027242212 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2608496465 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2157451868 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1626140475 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3512279654 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2071240637 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1532131232 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3526991995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2442815379 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2140657267 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3749182107 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3409757276 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2879916848 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3331658483 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3706575795 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2665839930 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2285100304 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2969035899 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.825670669 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4142190420 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3485809669 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1589257554 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1434364909 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.617947865 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.316980596 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.371398415 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506454828 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.247739037 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3680092275 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1022318829 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3280935164 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4161132837 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.714142279 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1441388910 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2748501226 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1270442770 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.526411370 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.507392945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2746294086 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2469615479 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1027990237 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1416166913 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.152078396 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1471072777 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3531729728 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2650360565 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3254802886 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3599794896 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3440586762 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1350270730 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.880416314 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4018711008 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.71740887 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2829268216 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1566644783 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3946112139 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.483952384 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3656329684 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4149242088 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3221221424 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.285239692 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.365071920 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1155733242 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2182589551 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2339334301 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2359693896 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2440772917 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1434534311 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1188265939 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1555553464 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3076114345 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2393006644 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2335148299 |
/workspace/coverage/default/0.sram_ctrl_alert_test.4119069134 |
/workspace/coverage/default/0.sram_ctrl_bijection.548199608 |
/workspace/coverage/default/0.sram_ctrl_executable.1759200574 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1950744146 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.961102835 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.440007336 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1466878215 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2632579301 |
/workspace/coverage/default/0.sram_ctrl_partial_access.868247015 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2801712362 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1410239767 |
/workspace/coverage/default/0.sram_ctrl_regwen.175536516 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2036905923 |
/workspace/coverage/default/0.sram_ctrl_smoke.4274576351 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1907227533 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1585299565 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.341343271 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1407789022 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4284968006 |
/workspace/coverage/default/1.sram_ctrl_bijection.2026438557 |
/workspace/coverage/default/1.sram_ctrl_executable.4177116591 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.846557244 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.806307634 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1162450467 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.3303062392 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2174885644 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3137002111 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3653246102 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3441377770 |
/workspace/coverage/default/1.sram_ctrl_regwen.1758818344 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2458007914 |
/workspace/coverage/default/1.sram_ctrl_smoke.3016668244 |
/workspace/coverage/default/1.sram_ctrl_stress_all.4014295290 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.760862380 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1612968000 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.792520600 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2078962216 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2150276290 |
/workspace/coverage/default/10.sram_ctrl_bijection.2246434336 |
/workspace/coverage/default/10.sram_ctrl_executable.1289917705 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3303297055 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3479461071 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3224131457 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3050340647 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4082046955 |
/workspace/coverage/default/10.sram_ctrl_partial_access.603361856 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1745111887 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.4283303245 |
/workspace/coverage/default/10.sram_ctrl_regwen.868614646 |
/workspace/coverage/default/10.sram_ctrl_smoke.2331363259 |
/workspace/coverage/default/10.sram_ctrl_stress_all.751555861 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1134968175 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1255716178 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4130420014 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2819302947 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1690945556 |
/workspace/coverage/default/11.sram_ctrl_bijection.4077391736 |
/workspace/coverage/default/11.sram_ctrl_executable.2135982872 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.382795097 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.943070378 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2677695286 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2536182384 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1676192256 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1495675000 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1511738776 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1439981666 |
/workspace/coverage/default/11.sram_ctrl_smoke.3166609451 |
/workspace/coverage/default/11.sram_ctrl_stress_all.208344681 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2202859468 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1306556656 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1558582474 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3811192650 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2277271044 |
/workspace/coverage/default/12.sram_ctrl_bijection.1302370992 |
/workspace/coverage/default/12.sram_ctrl_executable.1152311571 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1898507955 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1635757190 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2319988833 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.691154192 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.941936966 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3114448950 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3678074042 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3989323232 |
/workspace/coverage/default/12.sram_ctrl_regwen.1577819504 |
/workspace/coverage/default/12.sram_ctrl_smoke.1698147428 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1689013076 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2866839912 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.568537914 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1747488845 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2782258672 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1022932122 |
/workspace/coverage/default/13.sram_ctrl_bijection.566509290 |
/workspace/coverage/default/13.sram_ctrl_executable.3572808105 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2789356083 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.467251970 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1333108453 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3799321741 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.645794011 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3248161734 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.462248909 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1714985013 |
/workspace/coverage/default/13.sram_ctrl_regwen.768789731 |
/workspace/coverage/default/13.sram_ctrl_smoke.3912187181 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2710789647 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.4170545601 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3617762356 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3238713700 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3151737514 |
/workspace/coverage/default/14.sram_ctrl_bijection.1485726015 |
/workspace/coverage/default/14.sram_ctrl_executable.2301630249 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.4113037496 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3315034206 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3877292280 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1035319380 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.210632294 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1970991387 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2256993842 |
/workspace/coverage/default/14.sram_ctrl_regwen.3147641563 |
/workspace/coverage/default/14.sram_ctrl_smoke.1399700841 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3278121392 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1550134200 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.4055005032 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3811271205 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1568303653 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3037909104 |
/workspace/coverage/default/15.sram_ctrl_bijection.1530880376 |
/workspace/coverage/default/15.sram_ctrl_executable.95566048 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.4195719622 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1400569601 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2639561872 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3831240088 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.29335189 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2953165160 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1245868170 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.340614599 |
/workspace/coverage/default/15.sram_ctrl_regwen.499273085 |
/workspace/coverage/default/15.sram_ctrl_smoke.3041338650 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2502327842 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3447578678 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1859142937 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3335667286 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.881504524 |
/workspace/coverage/default/16.sram_ctrl_alert_test.129032442 |
/workspace/coverage/default/16.sram_ctrl_bijection.1821953758 |
/workspace/coverage/default/16.sram_ctrl_executable.3355447358 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1899516491 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.778276944 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2394455479 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3185345077 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.139249727 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1172086424 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.86245963 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3833996170 |
/workspace/coverage/default/16.sram_ctrl_regwen.1693061755 |
/workspace/coverage/default/16.sram_ctrl_smoke.1646723644 |
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/workspace/coverage/default/46.sram_ctrl_mem_walk.3289869494 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3950764036 |
/workspace/coverage/default/46.sram_ctrl_partial_access.4275150241 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3010701480 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1089188639 |
/workspace/coverage/default/46.sram_ctrl_regwen.1403430868 |
/workspace/coverage/default/46.sram_ctrl_smoke.813238683 |
/workspace/coverage/default/46.sram_ctrl_stress_all.292971353 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3991577809 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.628020120 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3332823062 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2433882276 |
/workspace/coverage/default/47.sram_ctrl_alert_test.205050091 |
/workspace/coverage/default/47.sram_ctrl_bijection.3034313824 |
/workspace/coverage/default/47.sram_ctrl_executable.2976429831 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1927230588 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.4240248102 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1105393691 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1192447176 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1429398483 |
/workspace/coverage/default/47.sram_ctrl_partial_access.4279172853 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2347502449 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3871622170 |
/workspace/coverage/default/47.sram_ctrl_regwen.4057707593 |
/workspace/coverage/default/47.sram_ctrl_smoke.1129020822 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2402358958 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1891307627 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4262642145 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3637868811 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4177810578 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4170493656 |
/workspace/coverage/default/48.sram_ctrl_bijection.1150150376 |
/workspace/coverage/default/48.sram_ctrl_executable.2445007784 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3860368663 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3008422730 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4186971577 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.4074585728 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.924587506 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1632334550 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3308177297 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.327163058 |
/workspace/coverage/default/48.sram_ctrl_regwen.3290044708 |
/workspace/coverage/default/48.sram_ctrl_smoke.3371094646 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2048716606 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2382800902 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1354366926 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.93995114 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.4062688631 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3117405685 |
/workspace/coverage/default/49.sram_ctrl_bijection.499863337 |
/workspace/coverage/default/49.sram_ctrl_executable.3323487653 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3411122559 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2221864440 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1661192695 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3548411168 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2342582315 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2441090842 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2137084845 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.108044985 |
/workspace/coverage/default/49.sram_ctrl_regwen.3822374565 |
/workspace/coverage/default/49.sram_ctrl_smoke.2389631899 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2561005887 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4047359628 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.4219728212 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.357421300 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3889751850 |
/workspace/coverage/default/5.sram_ctrl_alert_test.4106744255 |
/workspace/coverage/default/5.sram_ctrl_bijection.542474295 |
/workspace/coverage/default/5.sram_ctrl_executable.3196633347 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3644540700 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2048764019 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2285693121 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3837655063 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2094005171 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1808258687 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1666883007 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.546080937 |
/workspace/coverage/default/5.sram_ctrl_regwen.2703405149 |
/workspace/coverage/default/5.sram_ctrl_smoke.4101585551 |
/workspace/coverage/default/5.sram_ctrl_stress_all.770971789 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3729571641 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.366324568 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2916895017 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1775861132 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1477758058 |
/workspace/coverage/default/6.sram_ctrl_bijection.1214858516 |
/workspace/coverage/default/6.sram_ctrl_executable.90626867 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3914683387 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3679737512 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2389746764 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.657333044 |
/workspace/coverage/default/6.sram_ctrl_partial_access.360450636 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1380142557 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.854987890 |
/workspace/coverage/default/6.sram_ctrl_regwen.5803383 |
/workspace/coverage/default/6.sram_ctrl_smoke.1972698295 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1202307140 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.690801269 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3849803850 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4238263083 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.625054937 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3768668470 |
/workspace/coverage/default/7.sram_ctrl_bijection.2255924200 |
/workspace/coverage/default/7.sram_ctrl_executable.4204756292 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1302056495 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3997739238 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2723188697 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.152830345 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1627917448 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1569202419 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3202122322 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1300358095 |
/workspace/coverage/default/7.sram_ctrl_regwen.1199699719 |
/workspace/coverage/default/7.sram_ctrl_smoke.1176122321 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3733537078 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1557905211 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2766926763 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2101569578 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1263199035 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2035838142 |
/workspace/coverage/default/8.sram_ctrl_bijection.465768970 |
/workspace/coverage/default/8.sram_ctrl_executable.2258445255 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1337848599 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.4146411639 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2356395448 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.4146742715 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.700172724 |
/workspace/coverage/default/8.sram_ctrl_partial_access.756551812 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2595752918 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.15304578 |
/workspace/coverage/default/8.sram_ctrl_regwen.2668336590 |
/workspace/coverage/default/8.sram_ctrl_smoke.3886604133 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1154726185 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3413545703 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.345460294 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2642760300 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1278254348 |
/workspace/coverage/default/9.sram_ctrl_alert_test.904979106 |
/workspace/coverage/default/9.sram_ctrl_bijection.2437229665 |
/workspace/coverage/default/9.sram_ctrl_executable.1862647634 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.603571633 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2587340185 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.444367154 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2879897634 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4202871237 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3030971022 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3260004960 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.4144883143 |
/workspace/coverage/default/9.sram_ctrl_smoke.1966058820 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1714735934 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.741914496 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2114828229 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1120765362 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1407789022 |
|
|
Feb 07 12:57:00 PM PST 24 |
Feb 07 12:57:33 PM PST 24 |
101263451 ps |
T2 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1600582164 |
|
|
Feb 07 01:05:14 PM PST 24 |
Feb 07 01:05:20 PM PST 24 |
559485727 ps |
T3 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1820155949 |
|
|
Feb 07 12:58:08 PM PST 24 |
Feb 07 01:21:45 PM PST 24 |
31695434271 ps |
T7 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.682790967 |
|
|
Feb 07 12:58:10 PM PST 24 |
Feb 07 01:00:14 PM PST 24 |
146659525 ps |
T8 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2709178079 |
|
|
Feb 07 12:59:26 PM PST 24 |
Feb 07 12:59:40 PM PST 24 |
79046213 ps |
T9 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1267268526 |
|
|
Feb 07 01:00:02 PM PST 24 |
Feb 07 01:00:17 PM PST 24 |
306750713 ps |
T10 |
/workspace/coverage/default/26.sram_ctrl_regwen.3162961224 |
|
|
Feb 07 12:58:19 PM PST 24 |
Feb 07 01:17:38 PM PST 24 |
11403319380 ps |
T4 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1667843764 |
|
|
Feb 07 01:00:38 PM PST 24 |
Feb 07 01:00:42 PM PST 24 |
1186728188 ps |
T11 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1930371016 |
|
|
Feb 07 12:59:48 PM PST 24 |
Feb 07 01:00:23 PM PST 24 |
364513478 ps |
T12 |
/workspace/coverage/default/36.sram_ctrl_executable.2828207722 |
|
|
Feb 07 12:59:06 PM PST 24 |
Feb 07 01:07:14 PM PST 24 |
55071278601 ps |
T23 |
/workspace/coverage/default/5.sram_ctrl_alert_test.4106744255 |
|
|
Feb 07 12:57:34 PM PST 24 |
Feb 07 12:57:40 PM PST 24 |
41338343 ps |
T107 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2536182384 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 12:57:44 PM PST 24 |
101385167 ps |
T15 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.890944518 |
|
|
Feb 07 12:58:09 PM PST 24 |
Feb 07 01:00:26 PM PST 24 |
147978976 ps |
T62 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3813798770 |
|
|
Feb 07 12:57:56 PM PST 24 |
Feb 07 01:04:28 PM PST 24 |
5547554537 ps |
T97 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.93995114 |
|
|
Feb 07 01:00:48 PM PST 24 |
Feb 07 01:00:53 PM PST 24 |
94648229 ps |
T98 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3151567671 |
|
|
Feb 07 12:58:15 PM PST 24 |
Feb 07 12:58:20 PM PST 24 |
144280962 ps |
T99 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.4059412815 |
|
|
Feb 07 12:57:18 PM PST 24 |
Feb 07 12:58:59 PM PST 24 |
1615362393 ps |
T13 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3561073682 |
|
|
Feb 07 12:59:57 PM PST 24 |
Feb 07 01:21:57 PM PST 24 |
1124169548 ps |
T51 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3308177297 |
|
|
Feb 07 01:00:41 PM PST 24 |
Feb 07 01:06:43 PM PST 24 |
20135458139 ps |
T52 |
/workspace/coverage/default/31.sram_ctrl_smoke.2380916201 |
|
|
Feb 07 12:58:40 PM PST 24 |
Feb 07 12:58:51 PM PST 24 |
390155092 ps |
T108 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3242042613 |
|
|
Feb 07 12:58:19 PM PST 24 |
Feb 07 12:58:25 PM PST 24 |
939549776 ps |
T24 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3151737514 |
|
|
Feb 07 12:57:58 PM PST 24 |
Feb 07 12:58:04 PM PST 24 |
29250107 ps |
T144 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.691154192 |
|
|
Feb 07 12:57:33 PM PST 24 |
Feb 07 12:57:49 PM PST 24 |
455367000 ps |
T16 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.12119898 |
|
|
Feb 07 12:57:59 PM PST 24 |
Feb 07 01:03:44 PM PST 24 |
1120540240 ps |
T145 |
/workspace/coverage/default/47.sram_ctrl_smoke.1129020822 |
|
|
Feb 07 01:00:29 PM PST 24 |
Feb 07 01:00:44 PM PST 24 |
936087536 ps |
T29 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.741914496 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 01:05:34 PM PST 24 |
2672666232 ps |
T53 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1306556656 |
|
|
Feb 07 12:57:43 PM PST 24 |
Feb 07 01:02:34 PM PST 24 |
3060278487 ps |
T14 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2119586449 |
|
|
Feb 07 12:58:53 PM PST 24 |
Feb 07 01:01:57 PM PST 24 |
7580086381 ps |
T54 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1299971896 |
|
|
Feb 07 12:57:22 PM PST 24 |
Feb 07 01:04:40 PM PST 24 |
85632645589 ps |
T31 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.4176076484 |
|
|
Feb 07 12:59:27 PM PST 24 |
Feb 07 12:59:28 PM PST 24 |
27803047 ps |
T32 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1817312795 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 12:57:40 PM PST 24 |
52741076 ps |
T5 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2789356083 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 12:57:53 PM PST 24 |
3125798665 ps |
T126 |
/workspace/coverage/default/32.sram_ctrl_executable.3937821800 |
|
|
Feb 07 12:58:46 PM PST 24 |
Feb 07 01:08:29 PM PST 24 |
3546218732 ps |
T17 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2514886346 |
|
|
Feb 07 12:59:19 PM PST 24 |
Feb 07 01:11:20 PM PST 24 |
23961500267 ps |
T146 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1571942042 |
|
|
Feb 07 12:58:09 PM PST 24 |
Feb 07 12:59:57 PM PST 24 |
132116756 ps |
T137 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2342582315 |
|
|
Feb 07 01:00:52 PM PST 24 |
Feb 07 01:04:06 PM PST 24 |
32576190598 ps |
T30 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1134968175 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 02:48:46 PM PST 24 |
1831320861 ps |
T110 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1781082152 |
|
|
Feb 07 12:59:08 PM PST 24 |
Feb 07 12:59:17 PM PST 24 |
238756397 ps |
T111 |
/workspace/coverage/default/16.sram_ctrl_smoke.1646723644 |
|
|
Feb 07 12:57:36 PM PST 24 |
Feb 07 12:57:43 PM PST 24 |
110462660 ps |
T112 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2098066704 |
|
|
Feb 07 12:59:55 PM PST 24 |
Feb 07 01:02:07 PM PST 24 |
644076909 ps |
T147 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1120765362 |
|
|
Feb 07 12:57:21 PM PST 24 |
Feb 07 12:57:31 PM PST 24 |
106397744 ps |
T71 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1105393691 |
|
|
Feb 07 01:00:38 PM PST 24 |
Feb 07 01:00:42 PM PST 24 |
180658254 ps |
T148 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2953534766 |
|
|
Feb 07 12:59:40 PM PST 24 |
Feb 07 12:59:49 PM PST 24 |
196716200 ps |
T6 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3236466511 |
|
|
Feb 07 12:57:56 PM PST 24 |
Feb 07 12:58:09 PM PST 24 |
945378450 ps |
T149 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.645794011 |
|
|
Feb 07 12:57:33 PM PST 24 |
Feb 07 01:25:10 PM PST 24 |
29369146282 ps |
T138 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2839925073 |
|
|
Feb 07 12:59:00 PM PST 24 |
Feb 07 01:04:47 PM PST 24 |
42799365260 ps |
T150 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3841965717 |
|
|
Feb 07 12:57:27 PM PST 24 |
Feb 07 12:57:37 PM PST 24 |
71937763 ps |
T151 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.4163768267 |
|
|
Feb 07 12:59:20 PM PST 24 |
Feb 07 01:00:13 PM PST 24 |
109049038 ps |
T18 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.3028773802 |
|
|
Feb 07 12:57:09 PM PST 24 |
Feb 07 12:57:11 PM PST 24 |
570418798 ps |
T36 |
/workspace/coverage/default/1.sram_ctrl_smoke.3016668244 |
|
|
Feb 07 12:57:10 PM PST 24 |
Feb 07 12:57:24 PM PST 24 |
393020682 ps |
T33 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2202299430 |
|
|
Feb 07 12:57:20 PM PST 24 |
Feb 07 12:57:23 PM PST 24 |
68833289 ps |
T26 |
/workspace/coverage/default/17.sram_ctrl_regwen.2784880804 |
|
|
Feb 07 12:57:57 PM PST 24 |
Feb 07 01:10:53 PM PST 24 |
35643494427 ps |
T25 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2436968890 |
|
|
Feb 07 12:57:07 PM PST 24 |
Feb 07 12:57:08 PM PST 24 |
17313120 ps |
T37 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3300974226 |
|
|
Feb 07 12:59:37 PM PST 24 |
Feb 07 01:00:03 PM PST 24 |
354121519 ps |
T38 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1857724171 |
|
|
Feb 07 12:57:14 PM PST 24 |
Feb 07 12:57:15 PM PST 24 |
79483988 ps |
T39 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3775260824 |
|
|
Feb 07 12:59:08 PM PST 24 |
Feb 07 12:59:09 PM PST 24 |
14496846 ps |
T40 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3639426785 |
|
|
Feb 07 12:58:01 PM PST 24 |
Feb 07 12:58:10 PM PST 24 |
334294386 ps |
T41 |
/workspace/coverage/default/13.sram_ctrl_bijection.566509290 |
|
|
Feb 07 12:57:57 PM PST 24 |
Feb 07 12:58:15 PM PST 24 |
817773822 ps |
T125 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3662062298 |
|
|
Feb 07 12:58:36 PM PST 24 |
Feb 07 12:58:46 PM PST 24 |
1363066315 ps |
T152 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.651758796 |
|
|
Feb 07 12:57:49 PM PST 24 |
Feb 07 01:11:31 PM PST 24 |
29405443341 ps |
T101 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3921700187 |
|
|
Feb 07 12:59:21 PM PST 24 |
Feb 07 01:03:04 PM PST 24 |
4894913581 ps |
T153 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.470545919 |
|
|
Feb 07 12:58:39 PM PST 24 |
Feb 07 12:59:07 PM PST 24 |
182257644 ps |
T28 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1898507955 |
|
|
Feb 07 12:57:27 PM PST 24 |
Feb 07 12:57:42 PM PST 24 |
568969166 ps |
T154 |
/workspace/coverage/default/24.sram_ctrl_bijection.1236588196 |
|
|
Feb 07 12:58:09 PM PST 24 |
Feb 07 12:59:23 PM PST 24 |
12730360770 ps |
T155 |
/workspace/coverage/default/3.sram_ctrl_smoke.2083221493 |
|
|
Feb 07 12:57:21 PM PST 24 |
Feb 07 12:57:33 PM PST 24 |
1842783518 ps |
T156 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3350237319 |
|
|
Feb 07 12:58:09 PM PST 24 |
Feb 07 12:59:30 PM PST 24 |
315179688 ps |
T157 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3950764036 |
|
|
Feb 07 01:00:22 PM PST 24 |
Feb 07 01:24:07 PM PST 24 |
3408060241 ps |
T158 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2101569578 |
|
|
Feb 07 12:57:27 PM PST 24 |
Feb 07 12:59:20 PM PST 24 |
1274977647 ps |
T27 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3596197288 |
|
|
Feb 07 12:57:57 PM PST 24 |
Feb 07 01:22:31 PM PST 24 |
18364756927 ps |
T159 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3246190116 |
|
|
Feb 07 12:57:52 PM PST 24 |
Feb 07 12:57:54 PM PST 24 |
45170666 ps |
T160 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.4074585728 |
|
|
Feb 07 01:00:50 PM PST 24 |
Feb 07 01:00:55 PM PST 24 |
98779123 ps |
T161 |
/workspace/coverage/default/25.sram_ctrl_alert_test.196329712 |
|
|
Feb 07 12:58:20 PM PST 24 |
Feb 07 12:58:22 PM PST 24 |
89692483 ps |
T116 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.603571633 |
|
|
Feb 07 12:57:30 PM PST 24 |
Feb 07 12:57:48 PM PST 24 |
2767681378 ps |
T102 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1783147926 |
|
|
Feb 07 12:58:12 PM PST 24 |
Feb 07 01:03:37 PM PST 24 |
12447255351 ps |
T162 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1667797428 |
|
|
Feb 07 12:59:03 PM PST 24 |
Feb 07 01:00:13 PM PST 24 |
685018405 ps |
T163 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1218345299 |
|
|
Feb 07 12:59:44 PM PST 24 |
Feb 07 12:59:50 PM PST 24 |
73778745 ps |
T164 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2210225239 |
|
|
Feb 07 12:58:08 PM PST 24 |
Feb 07 12:58:17 PM PST 24 |
1010842260 ps |
T130 |
/workspace/coverage/default/14.sram_ctrl_regwen.3147641563 |
|
|
Feb 07 12:57:46 PM PST 24 |
Feb 07 01:01:20 PM PST 24 |
24986893495 ps |
T165 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1971580676 |
|
|
Feb 07 12:59:57 PM PST 24 |
Feb 07 01:00:00 PM PST 24 |
41223411 ps |
T166 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2510279849 |
|
|
Feb 07 12:59:37 PM PST 24 |
Feb 07 12:59:42 PM PST 24 |
109088444 ps |
T167 |
/workspace/coverage/default/45.sram_ctrl_smoke.1172709611 |
|
|
Feb 07 01:00:12 PM PST 24 |
Feb 07 01:00:15 PM PST 24 |
103968279 ps |
T168 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.681049322 |
|
|
Feb 07 12:59:18 PM PST 24 |
Feb 07 12:59:27 PM PST 24 |
131965797 ps |
T169 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1178957132 |
|
|
Feb 07 12:59:28 PM PST 24 |
Feb 07 12:59:41 PM PST 24 |
648789318 ps |
T170 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1910027925 |
|
|
Feb 07 12:59:43 PM PST 24 |
Feb 07 12:59:53 PM PST 24 |
97512482 ps |
T72 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1202848301 |
|
|
Feb 07 12:59:03 PM PST 24 |
Feb 07 12:59:09 PM PST 24 |
64722578 ps |
T171 |
/workspace/coverage/default/32.sram_ctrl_smoke.3382490360 |
|
|
Feb 07 12:58:45 PM PST 24 |
Feb 07 12:58:53 PM PST 24 |
1472048442 ps |
T21 |
/workspace/coverage/default/20.sram_ctrl_executable.993853812 |
|
|
Feb 07 12:58:05 PM PST 24 |
Feb 07 12:58:43 PM PST 24 |
1556604255 ps |
T172 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2688791352 |
|
|
Feb 07 12:57:44 PM PST 24 |
Feb 07 01:00:19 PM PST 24 |
159181627 ps |
T22 |
/workspace/coverage/default/11.sram_ctrl_regwen.3316656454 |
|
|
Feb 07 12:57:28 PM PST 24 |
Feb 07 01:15:33 PM PST 24 |
17645359035 ps |
T173 |
/workspace/coverage/default/22.sram_ctrl_alert_test.788623181 |
|
|
Feb 07 12:58:08 PM PST 24 |
Feb 07 12:58:11 PM PST 24 |
38142933 ps |
T44 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4149042265 |
|
|
Feb 07 12:58:42 PM PST 24 |
Feb 07 02:03:54 PM PST 24 |
4463632494 ps |
T174 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2432256509 |
|
|
Feb 07 12:57:16 PM PST 24 |
Feb 07 12:57:18 PM PST 24 |
14222181 ps |
T45 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1585299565 |
|
|
Feb 07 12:56:58 PM PST 24 |
Feb 07 01:44:17 PM PST 24 |
2613491555 ps |
T113 |
/workspace/coverage/default/39.sram_ctrl_regwen.3455396928 |
|
|
Feb 07 12:59:42 PM PST 24 |
Feb 07 01:06:59 PM PST 24 |
3453221413 ps |
T114 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1210238627 |
|
|
Feb 07 12:59:47 PM PST 24 |
Feb 07 12:59:58 PM PST 24 |
4023795576 ps |
T100 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3531729728 |
|
|
Feb 07 12:34:18 PM PST 24 |
Feb 07 12:34:20 PM PST 24 |
24909645 ps |
T55 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1566644783 |
|
|
Feb 07 12:34:14 PM PST 24 |
Feb 07 12:34:17 PM PST 24 |
53739510 ps |
T46 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1434364909 |
|
|
Feb 07 12:34:30 PM PST 24 |
Feb 07 12:34:33 PM PST 24 |
227696110 ps |
T47 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3114310085 |
|
|
Feb 07 12:34:07 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
42786008 ps |
T56 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2071240637 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:34:59 PM PST 24 |
31150111 ps |
T57 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2469615479 |
|
|
Feb 07 12:34:09 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
31020899 ps |
T42 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4018711008 |
|
|
Feb 07 12:34:17 PM PST 24 |
Feb 07 12:34:21 PM PST 24 |
1238954794 ps |
T48 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2576028297 |
|
|
Feb 07 12:34:47 PM PST 24 |
Feb 07 12:34:51 PM PST 24 |
178484808 ps |
T58 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1373886398 |
|
|
Feb 07 12:34:08 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
11445396 ps |
T59 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1589257554 |
|
|
Feb 07 12:34:58 PM PST 24 |
Feb 07 12:35:01 PM PST 24 |
17477422 ps |
T60 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2658732166 |
|
|
Feb 07 12:34:11 PM PST 24 |
Feb 07 12:34:13 PM PST 24 |
133805272 ps |
T49 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1872769048 |
|
|
Feb 07 12:34:27 PM PST 24 |
Feb 07 12:34:32 PM PST 24 |
128791107 ps |
T61 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1471072777 |
|
|
Feb 07 12:34:09 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
16545166 ps |
T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.247739037 |
|
|
Feb 07 12:34:15 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
42585569 ps |
T43 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2732801635 |
|
|
Feb 07 12:34:10 PM PST 24 |
Feb 07 12:34:13 PM PST 24 |
103095615 ps |
T63 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3221221424 |
|
|
Feb 07 12:34:08 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
40379715 ps |
T50 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.285239692 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:19 PM PST 24 |
108028827 ps |
T68 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3500244555 |
|
|
Feb 07 12:35:03 PM PST 24 |
Feb 07 12:35:09 PM PST 24 |
26818613 ps |
T69 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.825670669 |
|
|
Feb 07 12:34:45 PM PST 24 |
Feb 07 12:34:48 PM PST 24 |
653992162 ps |
T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3946112139 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
83072992 ps |
T122 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3331658483 |
|
|
Feb 07 12:34:15 PM PST 24 |
Feb 07 12:34:19 PM PST 24 |
433067055 ps |
T118 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1271165510 |
|
|
Feb 07 12:34:23 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
115017883 ps |
T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3620284469 |
|
|
Feb 07 12:34:18 PM PST 24 |
Feb 07 12:34:22 PM PST 24 |
876241092 ps |
T115 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2117988025 |
|
|
Feb 07 12:34:19 PM PST 24 |
Feb 07 12:34:24 PM PST 24 |
128908793 ps |
T175 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.152078396 |
|
|
Feb 07 12:34:15 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
30521969 ps |
T103 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.828479626 |
|
|
Feb 07 12:34:43 PM PST 24 |
Feb 07 12:34:45 PM PST 24 |
23237957 ps |
T176 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1027990237 |
|
|
Feb 07 12:34:20 PM PST 24 |
Feb 07 12:34:24 PM PST 24 |
787139608 ps |
T64 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2665839930 |
|
|
Feb 07 12:34:24 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
19649072 ps |
T65 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1595003806 |
|
|
Feb 07 12:34:37 PM PST 24 |
Feb 07 12:34:39 PM PST 24 |
41864316 ps |
T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.483952384 |
|
|
Feb 07 12:34:08 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
344146655 ps |
T82 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1973290313 |
|
|
Feb 07 12:34:21 PM PST 24 |
Feb 07 12:34:23 PM PST 24 |
29647064 ps |
T83 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3336856654 |
|
|
Feb 07 12:34:58 PM PST 24 |
Feb 07 12:35:04 PM PST 24 |
1031409234 ps |
T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1162237404 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
75591225 ps |
T85 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3076114345 |
|
|
Feb 07 12:34:19 PM PST 24 |
Feb 07 12:34:23 PM PST 24 |
72367152 ps |
T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1434534311 |
|
|
Feb 07 12:34:23 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
105164546 ps |
T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.371398415 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
73803876 ps |
T66 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3560536785 |
|
|
Feb 07 12:34:27 PM PST 24 |
Feb 07 12:34:28 PM PST 24 |
45132087 ps |
T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2182589551 |
|
|
Feb 07 12:34:25 PM PST 24 |
Feb 07 12:34:27 PM PST 24 |
15113437 ps |
T177 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3749182107 |
|
|
Feb 07 12:34:19 PM PST 24 |
Feb 07 12:34:21 PM PST 24 |
25817943 ps |
T178 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2140657267 |
|
|
Feb 07 12:34:33 PM PST 24 |
Feb 07 12:34:35 PM PST 24 |
34247965 ps |
T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2440879776 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
83028568 ps |
T179 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.480347385 |
|
|
Feb 07 12:34:23 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
244043902 ps |
T180 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3028111244 |
|
|
Feb 07 12:34:46 PM PST 24 |
Feb 07 12:34:47 PM PST 24 |
80419839 ps |
T181 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3085707682 |
|
|
Feb 07 12:34:43 PM PST 24 |
Feb 07 12:34:45 PM PST 24 |
190837886 ps |
T182 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1198617174 |
|
|
Feb 07 12:34:06 PM PST 24 |
Feb 07 12:34:09 PM PST 24 |
26446764 ps |
T183 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2829268216 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:15 PM PST 24 |
22695095 ps |
T184 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2359693896 |
|
|
Feb 07 12:34:10 PM PST 24 |
Feb 07 12:34:14 PM PST 24 |
52908369 ps |
T185 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3526991995 |
|
|
Feb 07 12:34:34 PM PST 24 |
Feb 07 12:34:40 PM PST 24 |
180253484 ps |
T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2442815379 |
|
|
Feb 07 12:34:54 PM PST 24 |
Feb 07 12:34:57 PM PST 24 |
285612738 ps |
T186 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.71740887 |
|
|
Feb 07 12:34:20 PM PST 24 |
Feb 07 12:34:22 PM PST 24 |
35956032 ps |
T187 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1978980231 |
|
|
Feb 07 12:34:43 PM PST 24 |
Feb 07 12:34:46 PM PST 24 |
80423843 ps |
T188 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1022318829 |
|
|
Feb 07 12:34:17 PM PST 24 |
Feb 07 12:34:23 PM PST 24 |
405211955 ps |
T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.30654696 |
|
|
Feb 07 12:34:24 PM PST 24 |
Feb 07 12:34:25 PM PST 24 |
55803155 ps |
T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.507392945 |
|
|
Feb 07 12:34:08 PM PST 24 |
Feb 07 12:34:13 PM PST 24 |
266702917 ps |
T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2608496465 |
|
|
Feb 07 12:34:51 PM PST 24 |
Feb 07 12:34:53 PM PST 24 |
19290906 ps |
T91 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1626140475 |
|
|
Feb 07 12:34:58 PM PST 24 |
Feb 07 12:35:02 PM PST 24 |
164554860 ps |
T92 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.880416314 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
41280123 ps |
T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3280935164 |
|
|
Feb 07 12:34:14 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
271087883 ps |
T94 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3111890787 |
|
|
Feb 07 12:34:49 PM PST 24 |
Feb 07 12:34:54 PM PST 24 |
43313715 ps |
T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2440772917 |
|
|
Feb 07 12:34:16 PM PST 24 |
Feb 07 12:34:19 PM PST 24 |
130628450 ps |
T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1270442770 |
|
|
Feb 07 12:34:05 PM PST 24 |
Feb 07 12:34:06 PM PST 24 |
14900686 ps |
T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2478843014 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:15 PM PST 24 |
14672516 ps |
T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1273942128 |
|
|
Feb 07 12:34:37 PM PST 24 |
Feb 07 12:34:40 PM PST 24 |
571692397 ps |
T189 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.762053898 |
|
|
Feb 07 12:34:11 PM PST 24 |
Feb 07 12:34:13 PM PST 24 |
91278946 ps |
T190 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.82368774 |
|
|
Feb 07 12:35:03 PM PST 24 |
Feb 07 12:35:09 PM PST 24 |
112839388 ps |
T191 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1155733242 |
|
|
Feb 07 12:34:16 PM PST 24 |
Feb 07 12:34:19 PM PST 24 |
89518438 ps |
T192 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.761055239 |
|
|
Feb 07 12:34:14 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
32878203 ps |
T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.576284167 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:17 PM PST 24 |
49075392 ps |
T76 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3440586762 |
|
|
Feb 07 12:34:17 PM PST 24 |
Feb 07 12:34:20 PM PST 24 |
120836608 ps |
T193 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2656639765 |
|
|
Feb 07 12:34:47 PM PST 24 |
Feb 07 12:34:51 PM PST 24 |
289899038 ps |
T194 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.617947865 |
|
|
Feb 07 12:34:05 PM PST 24 |
Feb 07 12:34:06 PM PST 24 |
50464817 ps |
T195 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.316980596 |
|
|
Feb 07 12:34:09 PM PST 24 |
Feb 07 12:34:12 PM PST 24 |
26813150 ps |
T196 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2748501226 |
|
|
Feb 07 12:34:04 PM PST 24 |
Feb 07 12:34:08 PM PST 24 |
57569806 ps |
T197 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1617863724 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:15 PM PST 24 |
21715540 ps |
T198 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1350270730 |
|
|
Feb 07 12:34:18 PM PST 24 |
Feb 07 12:34:20 PM PST 24 |
41184055 ps |
T199 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2392069357 |
|
|
Feb 07 12:34:25 PM PST 24 |
Feb 07 12:34:27 PM PST 24 |
39666303 ps |
T200 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3409757276 |
|
|
Feb 07 12:34:23 PM PST 24 |
Feb 07 12:34:25 PM PST 24 |
80056591 ps |
T201 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4149242088 |
|
|
Feb 07 12:34:08 PM PST 24 |
Feb 07 12:34:10 PM PST 24 |
87166402 ps |
T202 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1762296829 |
|
|
Feb 07 12:34:47 PM PST 24 |
Feb 07 12:34:53 PM PST 24 |
943213256 ps |
T203 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2157451868 |
|
|
Feb 07 12:34:52 PM PST 24 |
Feb 07 12:34:59 PM PST 24 |
139623076 ps |
T204 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4142190420 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:35:01 PM PST 24 |
162523744 ps |
T205 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3512279654 |
|
|
Feb 07 12:34:56 PM PST 24 |
Feb 07 12:35:00 PM PST 24 |
53859530 ps |
T123 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.365071920 |
|
|
Feb 07 12:34:22 PM PST 24 |
Feb 07 12:34:28 PM PST 24 |
2229071609 ps |
T206 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2027242212 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:34:59 PM PST 24 |
30323728 ps |
T207 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3485809669 |
|
|
Feb 07 12:34:58 PM PST 24 |
Feb 07 12:35:01 PM PST 24 |
39746799 ps |
T208 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3599794896 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
28661645 ps |
T209 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3084573537 |
|
|
Feb 07 12:34:07 PM PST 24 |
Feb 07 12:34:10 PM PST 24 |
45481124 ps |
T210 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1416166913 |
|
|
Feb 07 12:34:17 PM PST 24 |
Feb 07 12:34:19 PM PST 24 |
26047061 ps |
T211 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1532131232 |
|
|
Feb 07 12:35:01 PM PST 24 |
Feb 07 12:35:07 PM PST 24 |
37742186 ps |
T120 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3307869916 |
|
|
Feb 07 12:34:29 PM PST 24 |
Feb 07 12:34:32 PM PST 24 |
140783346 ps |
T212 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2339334301 |
|
|
Feb 07 12:34:17 PM PST 24 |
Feb 07 12:34:20 PM PST 24 |
31666181 ps |
T213 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3951766829 |
|
|
Feb 07 12:34:28 PM PST 24 |
Feb 07 12:34:35 PM PST 24 |
167318504 ps |
T121 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2393006644 |
|
|
Feb 07 12:34:20 PM PST 24 |
Feb 07 12:34:23 PM PST 24 |
86260210 ps |
T214 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506454828 |
|
|
Feb 07 12:34:10 PM PST 24 |
Feb 07 12:34:12 PM PST 24 |
70991540 ps |
T215 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.714142279 |
|
|
Feb 07 12:34:14 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
67570533 ps |
T216 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1441388910 |
|
|
Feb 07 12:34:10 PM PST 24 |
Feb 07 12:34:12 PM PST 24 |
36075434 ps |
T217 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4161132837 |
|
|
Feb 07 12:34:09 PM PST 24 |
Feb 07 12:34:11 PM PST 24 |
22550498 ps |
T218 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2285100304 |
|
|
Feb 07 12:34:43 PM PST 24 |
Feb 07 12:34:45 PM PST 24 |
15065316 ps |
T219 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.526411370 |
|
|
Feb 07 12:34:13 PM PST 24 |
Feb 07 12:34:16 PM PST 24 |
19427447 ps |
T220 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3656329684 |
|
|
Feb 07 12:34:27 PM PST 24 |
Feb 07 12:34:29 PM PST 24 |
127842410 ps |
T221 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1188265939 |
|
|
Feb 07 12:34:24 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
15855364 ps |
T222 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2315017707 |
|
|
Feb 07 12:34:03 PM PST 24 |
Feb 07 12:34:05 PM PST 24 |
15927304 ps |
T223 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3890445332 |
|
|
Feb 07 12:34:20 PM PST 24 |
Feb 07 12:34:23 PM PST 24 |
31683336 ps |
T224 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3680092275 |
|
|
Feb 07 12:34:01 PM PST 24 |
Feb 07 12:34:04 PM PST 24 |
52283415 ps |
T225 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3706575795 |
|
|
Feb 07 12:34:29 PM PST 24 |
Feb 07 12:34:32 PM PST 24 |
153056788 ps |
T226 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.802317895 |
|
|
Feb 07 12:34:10 PM PST 24 |
Feb 07 12:34:13 PM PST 24 |
620715505 ps |
T227 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1555553464 |
|
|
Feb 07 12:34:33 PM PST 24 |
Feb 07 12:34:34 PM PST 24 |
76053398 ps |
T228 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2746294086 |
|
|
Feb 07 12:34:12 PM PST 24 |
Feb 07 12:34:15 PM PST 24 |
132493319 ps |
T229 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2879916848 |
|
|
Feb 07 12:35:06 PM PST 24 |
Feb 07 12:35:14 PM PST 24 |
928966129 ps |
T230 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3254802886 |
|
|
Feb 07 12:34:15 PM PST 24 |
Feb 07 12:34:18 PM PST 24 |
214171415 ps |
T231 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2650360565 |
|
|
Feb 07 12:34:19 PM PST 24 |
Feb 07 12:34:24 PM PST 24 |
132726480 ps |
T232 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2373787428 |
|
|
Feb 07 12:34:28 PM PST 24 |
Feb 07 12:34:30 PM PST 24 |
188067574 ps |
T233 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2969035899 |
|
|
Feb 07 12:34:28 PM PST 24 |
Feb 07 12:34:31 PM PST 24 |
100536060 ps |
T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2046150277 |
|
|
Feb 07 12:34:23 PM PST 24 |
Feb 07 12:34:26 PM PST 24 |
150965011 ps |
T234 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2435470069 |
|
|
Feb 07 12:34:52 PM PST 24 |
Feb 07 12:34:55 PM PST 24 |
41863383 ps |
T235 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1808258687 |
|
|
Feb 07 12:57:13 PM PST 24 |
Feb 07 12:59:05 PM PST 24 |
258215073 ps |
T105 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2846355242 |
|
|
Feb 07 12:58:04 PM PST 24 |
Feb 07 01:02:34 PM PST 24 |
24147774446 ps |
T77 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1129173646 |
|
|
Feb 07 12:57:13 PM PST 24 |
Feb 07 12:57:16 PM PST 24 |
122271624 ps |
T236 |
/workspace/coverage/default/25.sram_ctrl_bijection.973764977 |
|
|
Feb 07 12:58:20 PM PST 24 |
Feb 07 12:59:03 PM PST 24 |
10428225151 ps |
T237 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2687486094 |
|
|
Feb 07 12:59:01 PM PST 24 |
Feb 07 12:59:09 PM PST 24 |
814799585 ps |
T106 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1666883007 |
|
|
Feb 07 12:57:21 PM PST 24 |
Feb 07 01:04:48 PM PST 24 |
6376426994 ps |
T131 |
/workspace/coverage/default/47.sram_ctrl_regwen.4057707593 |
|
|
Feb 07 01:00:39 PM PST 24 |
Feb 07 01:30:55 PM PST 24 |
6455688959 ps |
T78 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3877292280 |
|
|
Feb 07 12:57:42 PM PST 24 |
Feb 07 12:57:47 PM PST 24 |
691196247 ps |
T238 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.159311249 |
|
|
Feb 07 12:58:06 PM PST 24 |
Feb 07 12:58:14 PM PST 24 |
241408995 ps |
T239 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1155653064 |
|
|
Feb 07 12:58:19 PM PST 24 |
Feb 07 12:58:29 PM PST 24 |
336563500 ps |
T240 |
/workspace/coverage/default/8.sram_ctrl_smoke.3886604133 |
|
|
Feb 07 12:57:25 PM PST 24 |
Feb 07 12:58:52 PM PST 24 |
3707134228 ps |
T241 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3879318325 |
|
|
Feb 07 12:58:22 PM PST 24 |
Feb 07 12:58:24 PM PST 24 |
30891310 ps |
T242 |
/workspace/coverage/default/4.sram_ctrl_partial_access.678569849 |
|
|
Feb 07 12:57:23 PM PST 24 |
Feb 07 12:58:12 PM PST 24 |
581981323 ps |
T243 |
/workspace/coverage/default/10.sram_ctrl_bijection.2246434336 |
|
|
Feb 07 12:57:26 PM PST 24 |
Feb 07 12:58:09 PM PST 24 |
1121916380 ps |
T244 |
/workspace/coverage/default/36.sram_ctrl_regwen.3598023851 |
|
|
Feb 07 01:05:14 PM PST 24 |
Feb 07 01:11:30 PM PST 24 |
36310423360 ps |
T245 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.954139264 |
|
|
Feb 07 12:58:52 PM PST 24 |
Feb 07 01:03:14 PM PST 24 |
2631676255 ps |
T79 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1568303653 |
|
|
Feb 07 12:57:53 PM PST 24 |
Feb 07 01:04:04 PM PST 24 |
1867492316 ps |
T246 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.467251970 |
|
|
Feb 07 12:57:36 PM PST 24 |
Feb 07 12:59:09 PM PST 24 |
223439005 ps |
T247 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.62322714 |
|
|
Feb 07 12:58:46 PM PST 24 |
Feb 07 01:01:16 PM PST 24 |
5862143088 ps |
T248 |
/workspace/coverage/default/48.sram_ctrl_smoke.3371094646 |
|
|
Feb 07 01:00:38 PM PST 24 |
Feb 07 01:00:50 PM PST 24 |
2102584337 ps |
T80 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2388202245 |
|
|
Feb 07 12:57:57 PM PST 24 |
Feb 07 12:58:02 PM PST 24 |
665343641 ps |
T249 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3611332965 |
|
|
Feb 07 12:58:06 PM PST 24 |
Feb 07 12:58:32 PM PST 24 |
117323344 ps |
T250 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3043074455 |
|
|
Feb 07 12:59:42 PM PST 24 |
Feb 07 01:04:02 PM PST 24 |
3647904681 ps |
T251 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2727138853 |
|
|
Feb 07 12:58:20 PM PST 24 |
Feb 07 12:58:26 PM PST 24 |
83149990 ps |
T252 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.56399652 |
|
|
Feb 07 12:59:48 PM PST 24 |
Feb 07 01:00:01 PM PST 24 |
994293906 ps |
T253 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3184863141 |
|
|
Feb 07 12:59:48 PM PST 24 |
Feb 07 12:59:56 PM PST 24 |
45900658 ps |
T254 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1304213824 |
|
|
Feb 07 12:58:09 PM PST 24 |
Feb 07 12:58:24 PM PST 24 |
968271040 ps |
T255 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3572242097 |
|
|
Feb 07 12:59:07 PM PST 24 |
Feb 07 12:59:09 PM PST 24 |
11332967 ps |
T256 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1690945556 |
|
|
Feb 07 12:57:33 PM PST 24 |
Feb 07 12:57:40 PM PST 24 |
16521025 ps |
T136 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1661192695 |
|
|
Feb 07 01:01:02 PM PST 24 |
Feb 07 01:01:06 PM PST 24 |
362076959 ps |
T257 |
/workspace/coverage/default/37.sram_ctrl_alert_test.226864565 |
|
|
Feb 07 12:59:21 PM PST 24 |
Feb 07 12:59:22 PM PST 24 |
113303347 ps |
T127 |
/workspace/coverage/default/28.sram_ctrl_regwen.3256992283 |
|
|
Feb 07 12:58:32 PM PST 24 |
Feb 07 01:06:08 PM PST 24 |
34544444556 ps |
T132 |
/workspace/coverage/default/23.sram_ctrl_regwen.1594105457 |
|
|
Feb 07 12:58:05 PM PST 24 |
Feb 07 01:06:31 PM PST 24 |
2901694933 ps |
T258 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1160957822 |
|
|
Feb 07 12:58:38 PM PST 24 |
Feb 07 01:25:17 PM PST 24 |
7265330494 ps |
T259 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1824810609 |
|
|
Feb 07 12:58:00 PM PST 24 |
Feb 07 12:58:09 PM PST 24 |
110095565 ps |
T260 |
/workspace/coverage/default/41.sram_ctrl_bijection.924175109 |
|
|
Feb 07 12:59:46 PM PST 24 |
Feb 07 01:00:17 PM PST 24 |
1211886089 ps |
T261 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.2483098868 |
|
|
Feb 07 12:59:51 PM PST 24 |
Feb 07 01:00:04 PM PST 24 |
552709882 ps |
T262 |
/workspace/coverage/default/4.sram_ctrl_regwen.976803146 |
|
|
Feb 07 12:57:19 PM PST 24 |
Feb 07 01:15:09 PM PST 24 |
69925179124 ps |
T263 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3679737512 |
|
|
Feb 07 12:57:22 PM PST 24 |
Feb 07 12:57:27 PM PST 24 |
159202864 ps |
T264 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3834212841 |
|
|
Feb 07 12:58:00 PM PST 24 |
Feb 07 12:58:06 PM PST 24 |
116051390 ps |