Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43721135	1			T1	4592		T2	129		T3	136512
triple_byte_access	2452834	1			T1	229		T2	238		T3	2693
halfword_access	3683378	1			T1	316		T2	442		T3	4173
byte_access	4915607	1			T1	407		T2	811		T3	5445
zero_access	1237572	1			T1	105		T2	409		T3	1444

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27950426

1

T1

2838

T2

877

T3

75135

auto[1]

28060100

1

T1

2811

T2

1152

T3

75132

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21810381	1			T1	2321		T2	8		T3	68190
auto[0]	triple_byte_access	1223948	1			T1	114		T2	30		T3	1351
auto[0]	halfword_access	1837420	1			T1	152		T2	127		T3	2093
auto[0]	byte_access	2455555	1			T1	202		T2	399		T3	2782
auto[0]	zero_access	623122	1			T1	49		T2	313		T3	719
auto[1]	word_access	21910754	1			T1	2271		T2	121		T3	68322
auto[1]	triple_byte_access	1228886	1			T1	115		T2	208		T3	1342
auto[1]	halfword_access	1845958	1			T1	164		T2	315		T3	2080
auto[1]	byte_access	2460052	1			T1	205		T2	412		T3	2663
auto[1]	zero_access	614450	1			T1	56		T2	96		T3	725